SEKINE Toshikazu 関根敏和

Researcher Number	00108060
Other IDs
Affiliation (based on the past Project Information) *help	2014: 岐阜大学, 工学部, 准教授
Review Section/Research Field	Except Principal Investigator Electron device/Electronic equipment
Keywords	Except Principal Investigator AES / セキュア / 断熱的論理

LSI design of secure and low-power adiabatic logic
- Principal Investigator
  
  TAKAHASHI Yasuhiro
- Project Period (FY)
  2012 – 2014
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  Gifu University

All 2015 2014 2013 2012 Other

All Journal Article Presentation Patent

[Journal Article] Low-power secure S-Box circuit using CSSAL for AES hardware design2015
- Author(s)
  C. Monteiro, Y. Takahashi, and T. Sekine
- Journal Title
  
  IET Circuits, Devices & Systems
  
  Volume: 9
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-24760274
[Journal Article] The ramped-step voltage in adiabatic logic circuits: analysis of parameters to further reduce power dissipation2013
- Author(s)
  N. A. Nayan, Y. Takahashi, and T. Sekine
- Journal Title
  
  Research J. of Applied Sciences, Engineering and Technology
  
  Volume: 5 Pages: 114-117
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-24760274
[Journal Article] Low power bit-parallel cellular multiplier implementation in secure dual-rail adiabatic logic2013
- Author(s)
  C. Monteiro, Y. Takahashi, and T. Sekine
- Journal Title
  
  IACSIT International J. Modeling and Optimization
  
  Volume: 3 Pages: 329-332
- DOI
  10.7763/ijmo.2013.v3.292
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-24760274
[Journal Article] Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level2013
- Author(s)
  C. Monteiro, Y. Takahashi, and T. Sekine
- Journal Title
  
  Microelectronics Journal,
  
  Volume: 44 Issue: 6 Pages: 496-503
- DOI
  10.1016/j.mejo.2013.04.003
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-24760274
[Patent] 差動論理によりサイドチャネル攻撃から保護される暗号回路2012
- Inventor(s)
  高橋康宏, モンテイロカンシオ, 関根敏和
- Industrial Property Rights Holder
  高橋康宏, モンテイロカンシオ, 関根敏和
- Industrial Property Rights Type
  特許
- Industrial Property Number
  2012-274909
- Filing Date
  2012-12-19
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] Measurement of CSSAL Multiplier over GF(24) LSI Implemented in 0.18 µm CMOS Technology2014
- Author(s)
  C. Monteiro, 高橋康宏, 関根敏和
- Organizer
  2014年電子情報通信学会総合大会講演論文集
- Place of Presentation
  新潟市
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] Security evaluation of CSSAL countermeasure against side-channel attacks using frequency spectrum analysis2014
- Author(s)
  C. Monteiro, Y. Takahashi, and T. Sekine
- Organizer
  電子情報通信学会EMCJ研究会
- Place of Presentation
  浜松市
- Year and Date
  2014-12-19
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] Low power CSSAL bit-parallel multiplier over GF(2^4) in 0.18 um CMOS technology2013
- Author(s)
  C. Monteiro, 高橋康宏, 関根敏和
- Organizer
  電子情報通信学会EMCJ研究会
- Place of Presentation
  岡山市
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] Low power secure AES S-box using adiabatic logic circuit2013
- Author(s)
  C. Monteiro, Y. Takahashi, and T. Sekine
- Organizer
  IEEE FTFC 2013
- Place of Presentation
  Paris, France
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] LSI iplementation of a secure low-power CSSAL cellular multiplier2013
- Author(s)
  C. Monteiro, 高橋康宏, 関根敏和
- Organizer
  電子情報通信学会CAS研究会
- Place of Presentation
  岐阜市
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] 負荷容量均一化対称構造断熱的論理回路CSSAL ～論理回路設計と暗号回路設計の事例～2013
- Author(s)
  高橋康宏, C. Monteiro, 関根敏和
- Organizer
  電子情報通信学会CAS研究会
- Place of Presentation
  岐阜市
- Invited
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] Robust secure charge-sharing symmetric adiabatic logic against side-channel attacks2013
- Author(s)
  C. Monteiro, Y. Takahashi, and T. Sekine
- Organizer
  IEEE TSP 2013
- Place of Presentation
  Roma, Italy
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] DPA resistance of charge-sharing symmetric adiabatic logic2013
- Author(s)
  C. Monteiro, Y. Takahashi, and T. Sekine
- Organizer
  IEEE ISCAS 2013
- Place of Presentation
  Beijing, China
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] Low power secure CSSAL bit-parallel multiplier over GF(2^4) in 0.18 um CMOS technology2013
- Author(s)
  C. Monteiro, Y. Takahashi, and T. Sekine
- Organizer
  IEEE ECCTD 2013
- Place of Presentation
  Dresden, Germany
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] LSI implementation of a bit-parallel cellular multiplier over GF(24) using charge-sharing symmetric adiabatic logic2013
- Author(s)
  C. Monteiro, 高橋康宏, 関根敏和
- Organizer
  2013年電子情報通信学会ソサイエティ大会
- Place of Presentation
  福岡市
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] Low power bit-parallel multiplier over GF(2^4) using CSSAL for cryptographic hardware implementation2013
- Author(s)
  C. Monteiro, Y. Takahashi, and T. Sekine
- Organizer
  IEEE Coolchips XVI,
- Place of Presentation
  横浜市
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] Secure charge-sharing symmetric adiabatic logic implementation in AES S-Box architecture for smart card2013
- Author(s)
  C. Monteiro, Y. Takahashi, and T. Sekine
- Organizer
  IEEE ICEIC 2013
- Place of Presentation
  Bali, Indonesia
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] A comparison of cellular multiplier cell for finite field GF(2^m) using secure adiabatic logics2012
- Author(s)
  C. Monteiro, 高橋康宏, 関根敏和
- Organizer
  電気学会電子回路研究会
- Place of Presentation
  米沢市
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] Investigation study of inner-cell bit-parallel multiplier over GF(2m) using secure adiabatic logic style2012
- Author(s)
  C. Monteiro, 高橋康宏, 関根敏和
- Organizer
  2012年電子情報通信学会ソサエティ大会
- Place of Presentation
  富山市
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] サブスレッショルド断熱的論理回路の性能解析と省電力効果2012
- Author(s)
  高橋康宏, 関根敏和, 横山道央
- Organizer
  2012年電子情報通信学会ソサエティ大会
- Place of Presentation
  富山市
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] Power-saving analysis of adiabatic logic in subthreshold region2012
- Author(s)
  Y. Takahashi, T. Sekine, N. A. Nayan, and M. Yokoyama
- Organizer
  IEEE ISPACS 2012
- Place of Presentation
  Tamsui, Taiwan
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] Low power CSSAL bit-parallel multiplier over GF(2^4) in 0.18 µm CMOS technology2012
- Author(s)
  C. Monteiro, 高橋康宏, 関根敏和
- Organizer
  電子情報通信学会EMCJ研究会
- Place of Presentation
  岐阜市
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] Process variation verification of low-power secure CSSAL AES S-box
- Author(s)
  C. Monteiro, Y. Takahashi, and T. Sekine
- Organizer
  IEEE MWSCAS 2014
- Place of Presentation
  College Station, TX
- Year and Date
  2014-08-03 – 2014-08-06
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] Effectiveness of dual-rail CSSAL against power analysis attack under CMOS process variation
- Author(s)
  C. Monteiro, Y. Takahashi, and T. Sekine
- Organizer
  IEEE APCCAS 2014
- Place of Presentation
  石垣市
- Year and Date
  2014-11-17 – 2014-11-20
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] An LSI implementation of a bit-parallel cellular multiplier over GF(2^4) using secure charge-sharing symmetric adiabatic logic
- Author(s)
  C. Monteiro, Y. Takahashi, and T. Sekine
- Organizer
  IEEE ISCAS 2014
- Place of Presentation
  Melbourne, Australia
- Year and Date
  2014-06-01 – 2014-06-05
- Data Source
  KAKENHI-PROJECT-24760274

1. TAKAHASHI Yasuhiro (00402214)

# of Collaborated Projects: 1 results

# of Collaborated Products: 24 results
2. YOKOYAMA Michio (40261573)

# of Collaborated Projects: 1 results

# of Collaborated Products: 2 results
3. MONTEIRO Cancio

# of Collaborated Projects: 1 results

# of Collaborated Products: 21 results

SEKINE Toshikazu 関根 敏和

Research Projects

Research Products

Co-Researchers

LSI design of secure and low-power adiabatic logic

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

[Journal Article] Low-power secure S-Box circuit using CSSAL for AES hardware design2015

Author(s)

Journal Title

Data Source

[Journal Article] The ramped-step voltage in adiabatic logic circuits: analysis of parameters to further reduce power dissipation2013

Author(s)

Journal Title

Data Source

[Journal Article] Low power bit-parallel cellular multiplier implementation in secure dual-rail adiabatic logic2013

Author(s)

Journal Title

DOI

Data Source

[Journal Article] Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level2013

Author(s)

Journal Title

DOI

Data Source

[Patent] 差動論理によりサイドチャネル攻撃から保護される暗号回路2012

Inventor(s)

Industrial Property Rights Holder

Industrial Property Rights Type

Industrial Property Number

Filing Date

Data Source

[Presentation] Measurement of CSSAL Multiplier over GF(24) LSI Implemented in 0.18 µm CMOS Technology2014

Author(s)

Organizer

Place of Presentation

Data Source

[Presentation] Security evaluation of CSSAL countermeasure against side-channel attacks using frequency spectrum analysis2014

Author(s)

Organizer

Place of Presentation

Year and Date

Data Source

[Presentation] Low power CSSAL bit-parallel multiplier over GF(2^4) in 0.18 um CMOS technology2013

Author(s)

Organizer

Place of Presentation

Data Source

[Presentation] Low power secure AES S-box using adiabatic logic circuit2013

Author(s)

Organizer

Place of Presentation

Data Source

[Presentation] LSI iplementation of a secure low-power CSSAL cellular multiplier2013

Author(s)

Organizer

Place of Presentation

Data Source

[Presentation] 負荷容量均一化対称構造断熱的論理回路CSSAL ～論理回路設計と暗号回路設計の事例～2013

Author(s)

Organizer

Place of Presentation

Data Source

[Presentation] Robust secure charge-sharing symmetric adiabatic logic against side-channel attacks2013

Author(s)

Organizer

Place of Presentation

Data Source

[Presentation] DPA resistance of charge-sharing symmetric adiabatic logic2013

Author(s)

Organizer

Place of Presentation

Data Source

[Presentation] Low power secure CSSAL bit-parallel multiplier over GF(2^4) in 0.18 um CMOS technology2013

Author(s)

Organizer

Place of Presentation

SEKINE Toshikazu 関根敏和