TAKAHASHI Yasuhiro 高橋康宏

… Alternative Names

高橋康宏タカハシヤスヒロ

Takahashi Yasuhiro 高橋康宏

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Researcher Number	00402214
Other IDs	https://orcid.org/0000-0002-1653-8425
Affiliation (Current)	2024: 岐阜大学, 工学部, 准教授
Affiliation (based on the past Project Information) *help	2022: 岐阜大学, 工学部, 准教授 2017 – 2018: 岐阜大学, 工学部, 准教授 2014: 岐阜大学, 工学部, 准教授 2012 – 2013: 岐阜大学, 工学部, 助教
Review Section/Research Field	Principal Investigator Electron device/Electronic equipment / Basic Section 60070:Information security-related
Keywords	Principal Investigator 断熱的論理 / 低消費電力 / セキュア / レイアウト / 電流変動 / レイアウト設計 / 集積回路 / 暗号回路 / デジタル回路 / 半導体集積回路 / 低電圧 / サブスレッショルド論理 / AES

集積回路レイアウトの観点からみた暗号用デジタル断熱的論理回路の電流特性の解明Principal Investigator
- Principal Investigator
  
  高橋康宏
- Project Period (FY)
  2022 – 2024
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 60070:Information security-related
- Research Institution
  Gifu University
Development of Power Consumption Model of Low-voltage and Low-power Sub-threshold Adiabatic LogicPrincipal Investigator
- Principal Investigator
  
  Takahashi Yasuhiro
- Project Period (FY)
  2017 – 2018
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  Gifu University
LSI design of secure and low-power adiabatic logicPrincipal Investigator
- Principal Investigator
  
  TAKAHASHI Yasuhiro
- Project Period (FY)
  2012 – 2014
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  Gifu University

All 2019 2018 2017 2015 2014 2013 2012 Other

All Journal Article Presentation Patent

[Journal Article] Current Pass Optimized Symmetric Pass Gate Adiabatic Logic for Cryptographic Circuits2019
- Author(s)
  Koyasu Hiroki, Takahashi Yasuhiro
- Journal Title
  
  IPSJ Transactions on System LSI Design Methodology
  
  Volume: 12 Issue: 0 Pages: 50-52
- DOI
  10.2197/ipsjtsldm.12.50
- NAID
  130007603009
- ISSN
  1882-6687
- Language
  English
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-17K14664
[Journal Article] A new adiabatic logic without charge sharing gate for cryptographic devices2018
- Author(s)
  R. Ohashi, Y. Takahashi
- Journal Title
  
  Proc. IEEE ISPACS 2018
  
  Volume: 1 Pages: 117-121
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17K14664
[Journal Article] A performance comparison of adiabatic logic circuits2018
- Author(s)
  M. Han, Y. Takahashi, T. Sekine
- Journal Title
  
  Proc. IEEJ AVIC 2018
  
  Volume: 1 Pages: 149-152
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17K14664
[Journal Article] Diode based adiabatic logic with feedback circuit in countermeasure against power analysis attacks2018
- Author(s)
  Y. Masaki, Y. Takahashi
- Journal Title
  
  Proc. IEEJ AVIC 2018
  
  Volume: 1 Pages: 165-168
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17K14664
[Journal Article] Low power source biased semi-adiabatic logic circuit for IoT devices2018
- Author(s)
  C. Monteiro, A. Maria, Y. Takahashi
- Journal Title
  
  Proc. IEEE ISPACS 2018
  
  Volume: 1 Pages: 43-47
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17K14664
[Journal Article] Current pass optimized-symmetric pass gate adiabatic logic in countermeasures against power analysis attacks2018
- Author(s)
  H. Koyasu, Y. Takahashi
- Journal Title
  
  Proc. IEEE ISPACS 2018
  
  Volume: 1 Pages: 122-126
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17K14664
[Journal Article] A verification of resonant clock driver design for the IoT era2017
- Author(s)
  Takahashi Yasuhiro, Sekine Toshikazu, Yokoyama Michio
- Journal Title
  
  Proｃ. of IEEE 12th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT2017)
  
  Volume: 1 Pages: 492-494
- DOI
  10.1109/impact.2017.8255895
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17K14664
[Journal Article] Low power Adiabatic Logic based on 2PC2AL2017
- Author(s)
  Han Mei, Takahashi Yasuhiro, Sekine Toshikazu
- Journal Title
  
  Proc. of IEEE International Conference on IC Design and Technology (ICICDT2017)
  
  Volume: 1 Pages: 1-4
- DOI
  10.1109/icicdt.2017.7993517
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17K14664
[Journal Article] Operational amplifier based LC resonant circuit for adiabatic logic2017
- Author(s)
  Takahashi Yasuhiro, Sekine Toshikazu, Han Mei
- Journal Title
  
  Proc. of IEEE 24th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES2017)
  
  Volume: 1 Pages: 110-114
- DOI
  10.23919/mixdes.2017.8005164
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17K14664
[Journal Article] Low-power secure S-Box circuit using CSSAL for AES hardware design2015
- Author(s)
  C. Monteiro, Y. Takahashi, and T. Sekine
- Journal Title
  
  IET Circuits, Devices & Systems
  
  Volume: 9
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-24760274
[Journal Article] The ramped-step voltage in adiabatic logic circuits: analysis of parameters to further reduce power dissipation2013
- Author(s)
  N. A. Nayan, Y. Takahashi, and T. Sekine
- Journal Title
  
  Research J. of Applied Sciences, Engineering and Technology
  
  Volume: 5 Pages: 114-117
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-24760274
[Journal Article] Low power bit-parallel cellular multiplier implementation in secure dual-rail adiabatic logic2013
- Author(s)
  C. Monteiro, Y. Takahashi, and T. Sekine
- Journal Title
  
  IACSIT International J. Modeling and Optimization
  
  Volume: 3 Pages: 329-332
- DOI
  10.7763/ijmo.2013.v3.292
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-24760274
[Journal Article] Low Power Supply Circuit Using Off-chip Resonant Circuit for Adiabatic Logic2013
- Author(s)
  高橋康宏, 佐藤比佐夫
- Journal Title
  
  IEEJ Transactions on Electronics, Information and Systems
  
  Volume: 133 Issue: 2 Pages: 220-225
- DOI
  10.1541/ieejeiss.133.220
- NAID
  10031142428
- ISSN
  0385-4221, 1348-8155
- Language
  Japanese
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-24760274
[Journal Article] Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level2013
- Author(s)
  C. Monteiro, Y. Takahashi, and T. Sekine
- Journal Title
  
  Microelectronics Journal,
  
  Volume: 44 Issue: 6 Pages: 496-503
- DOI
  10.1016/j.mejo.2013.04.003
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-24760274
[Journal Article] LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier2012
- Author(s)
  N. A. Nayan, Y. Takahashi, and T. Sekin
- Journal Title
  
  Microelectronics Journal
  
  Volume: 43 Issue: 4 Pages: 244-249
- DOI
  10.1016/j.mejo.2011.12.013
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-24760274
[Patent] 差動論理によりサイドチャネル攻撃から保護される暗号回路2012
- Inventor(s)
  高橋康宏, モンテイロカンシオ, 関根敏和
- Industrial Property Rights Holder
  高橋康宏, モンテイロカンシオ, 関根敏和
- Industrial Property Rights Type
  特許
- Industrial Property Number
  2012-274909
- Filing Date
  2012-12-19
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] 断熱的論理回路による暗号回路への電力解析攻撃による評価2018
- Author(s)
  子安博貴, 高橋康宏
- Organizer
  電気学会電子回路研究会
- Data Source
  KAKENHI-PROJECT-17K14664
[Presentation] ブートストラップ構造を有する断熱的暗号用論理回路2018
- Author(s)
  大橋遼介, 高橋康宏
- Organizer
  電気学会電子回路研究会
- Data Source
  KAKENHI-PROJECT-17K14664
[Presentation] ダイオードを用いた断熱的論理回路で構成したS-Boxの特性評価2018
- Author(s)
  正木豊, 高橋康宏
- Organizer
  電気学会電子回路研究会
- Data Source
  KAKENHI-PROJECT-17K14664
[Presentation] 断熱的可逆論理回路の一提案2018
- Author(s)
  西脇友崇, 高橋康宏, 関根敏和
- Organizer
  電気学会電子回路研究会
- Data Source
  KAKENHI-PROJECT-17K14664
[Presentation] A comparison of energy dissipation of 4-bit adiabatic multiplier2018
- Author(s)
  Han Mei, Takahashi Yasuhiro, Sekine Toshikazu
- Organizer
  電気学会電子回路研究会
- Data Source
  KAKENHI-PROJECT-17K14664
[Presentation] 電流経路均一化による暗号用断熱的論理回路の提案2018
- Author(s)
  子安博貴, 高橋康宏
- Organizer
  電気学会電子回路研究会
- Data Source
  KAKENHI-PROJECT-17K14664
[Presentation] Evaluation of 4-bit array multiplier of adiabatic logic family2017
- Author(s)
  Han Mei, Takahashi Yasuhiro, Sekine Toshikazu
- Organizer
  電子情報通信学会回路とシステム研究会
- Data Source
  KAKENHI-PROJECT-17K14664
[Presentation] Measurement of CSSAL Multiplier over GF(24) LSI Implemented in 0.18 µm CMOS Technology2014
- Author(s)
  C. Monteiro, 高橋康宏, 関根敏和
- Organizer
  2014年電子情報通信学会総合大会講演論文集
- Place of Presentation
  新潟市
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] Security evaluation of CSSAL countermeasure against side-channel attacks using frequency spectrum analysis2014
- Author(s)
  C. Monteiro, Y. Takahashi, and T. Sekine
- Organizer
  電子情報通信学会EMCJ研究会
- Place of Presentation
  浜松市
- Year and Date
  2014-12-19
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] Low power CSSAL bit-parallel multiplier over GF(2^4) in 0.18 um CMOS technology2013
- Author(s)
  C. Monteiro, 高橋康宏, 関根敏和
- Organizer
  電子情報通信学会EMCJ研究会
- Place of Presentation
  岡山市
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] Low power secure AES S-box using adiabatic logic circuit2013
- Author(s)
  C. Monteiro, Y. Takahashi, and T. Sekine
- Organizer
  IEEE FTFC 2013
- Place of Presentation
  Paris, France
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] LSI iplementation of a secure low-power CSSAL cellular multiplier2013
- Author(s)
  C. Monteiro, 高橋康宏, 関根敏和
- Organizer
  電子情報通信学会CAS研究会
- Place of Presentation
  岐阜市
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] 負荷容量均一化対称構造断熱的論理回路CSSAL ～論理回路設計と暗号回路設計の事例～2013
- Author(s)
  高橋康宏, C. Monteiro, 関根敏和
- Organizer
  電子情報通信学会CAS研究会
- Place of Presentation
  岐阜市
- Invited
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] Robust secure charge-sharing symmetric adiabatic logic against side-channel attacks2013
- Author(s)
  C. Monteiro, Y. Takahashi, and T. Sekine
- Organizer
  IEEE TSP 2013
- Place of Presentation
  Roma, Italy
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] DPA resistance of charge-sharing symmetric adiabatic logic2013
- Author(s)
  C. Monteiro, Y. Takahashi, and T. Sekine
- Organizer
  IEEE ISCAS 2013
- Place of Presentation
  Beijing, China
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] Low power secure CSSAL bit-parallel multiplier over GF(2^4) in 0.18 um CMOS technology2013
- Author(s)
  C. Monteiro, Y. Takahashi, and T. Sekine
- Organizer
  IEEE ECCTD 2013
- Place of Presentation
  Dresden, Germany
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] LSI implementation of a bit-parallel cellular multiplier over GF(24) using charge-sharing symmetric adiabatic logic2013
- Author(s)
  C. Monteiro, 高橋康宏, 関根敏和
- Organizer
  2013年電子情報通信学会ソサイエティ大会
- Place of Presentation
  福岡市
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] Low power bit-parallel multiplier over GF(2^4) using CSSAL for cryptographic hardware implementation2013
- Author(s)
  C. Monteiro, Y. Takahashi, and T. Sekine
- Organizer
  IEEE Coolchips XVI,
- Place of Presentation
  横浜市
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] Secure charge-sharing symmetric adiabatic logic implementation in AES S-Box architecture for smart card2013
- Author(s)
  C. Monteiro, Y. Takahashi, and T. Sekine
- Organizer
  IEEE ICEIC 2013
- Place of Presentation
  Bali, Indonesia
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] A comparison of cellular multiplier cell for finite field GF(2^m) using secure adiabatic logics2012
- Author(s)
  C. Monteiro, 高橋康宏, 関根敏和
- Organizer
  電気学会電子回路研究会
- Place of Presentation
  米沢市
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] Investigation study of inner-cell bit-parallel multiplier over GF(2m) using secure adiabatic logic style2012
- Author(s)
  C. Monteiro, 高橋康宏, 関根敏和
- Organizer
  2012年電子情報通信学会ソサエティ大会
- Place of Presentation
  富山市
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] サブスレッショルド断熱的論理回路の性能解析と省電力効果2012
- Author(s)
  高橋康宏, 関根敏和, 横山道央
- Organizer
  2012年電子情報通信学会ソサエティ大会
- Place of Presentation
  富山市
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] Power-saving analysis of adiabatic logic in subthreshold region2012
- Author(s)
  Y. Takahashi, T. Sekine, N. A. Nayan, and M. Yokoyama
- Organizer
  IEEE ISPACS 2012
- Place of Presentation
  Tamsui, Taiwan
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] Low power CSSAL bit-parallel multiplier over GF(2^4) in 0.18 µm CMOS technology2012
- Author(s)
  C. Monteiro, 高橋康宏, 関根敏和
- Organizer
  電子情報通信学会EMCJ研究会
- Place of Presentation
  岐阜市
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] Process variation verification of low-power secure CSSAL AES S-box
- Author(s)
  C. Monteiro, Y. Takahashi, and T. Sekine
- Organizer
  IEEE MWSCAS 2014
- Place of Presentation
  College Station, TX
- Year and Date
  2014-08-03 – 2014-08-06
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] Effectiveness of dual-rail CSSAL against power analysis attack under CMOS process variation
- Author(s)
  C. Monteiro, Y. Takahashi, and T. Sekine
- Organizer
  IEEE APCCAS 2014
- Place of Presentation
  石垣市
- Year and Date
  2014-11-17 – 2014-11-20
- Data Source
  KAKENHI-PROJECT-24760274
[Presentation] An LSI implementation of a bit-parallel cellular multiplier over GF(2^4) using secure charge-sharing symmetric adiabatic logic
- Author(s)
  C. Monteiro, Y. Takahashi, and T. Sekine
- Organizer
  IEEE ISCAS 2014
- Place of Presentation
  Melbourne, Australia
- Year and Date
  2014-06-01 – 2014-06-05
- Data Source
  KAKENHI-PROJECT-24760274

1. SEKINE Toshikazu (00108060)

# of Collaborated Projects: 2 results

# of Collaborated Products: 39 results
2. YOKOYAMA Michio (40261573)

# of Collaborated Projects: 1 results

# of Collaborated Products: 2 results
3. MONTEIRO Cancio

# of Collaborated Projects: 1 results

# of Collaborated Products: 21 results

TAKAHASHI Yasuhiro 高橋 康宏

高橋 康宏 タカハシ ヤスヒロ

Takahashi Yasuhiro 高橋 康宏

Research Projects

Research Products

Co-Researchers

集積回路レイアウトの観点からみた暗号用デジタル断熱的論理回路の電流特性の解明Principal Investigator

Principal Investigator

Project Period (FY)

Research Category

Review Section

Research Institution

Development of Power Consumption Model of Low-voltage and Low-power Sub-threshold Adiabatic LogicPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

LSI design of secure and low-power adiabatic logicPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

[Journal Article] Current Pass Optimized Symmetric Pass Gate Adiabatic Logic for Cryptographic Circuits2019

Author(s)

Journal Title

DOI

NAID

ISSN

Language

Data Source

[Journal Article] A new adiabatic logic without charge sharing gate for cryptographic devices2018

Author(s)

Journal Title

Data Source

[Journal Article] A performance comparison of adiabatic logic circuits2018

Author(s)

Journal Title

Data Source

[Journal Article] Diode based adiabatic logic with feedback circuit in countermeasure against power analysis attacks2018

Author(s)

Journal Title

Data Source

[Journal Article] Low power source biased semi-adiabatic logic circuit for IoT devices2018

Author(s)

Journal Title

Data Source

[Journal Article] Current pass optimized-symmetric pass gate adiabatic logic in countermeasures against power analysis attacks2018

Author(s)

Journal Title

Data Source

[Journal Article] A verification of resonant clock driver design for the IoT era2017

Author(s)

Journal Title

DOI

Data Source

[Journal Article] Low power Adiabatic Logic based on 2PC2AL2017

Author(s)

Journal Title

DOI

Data Source

[Journal Article] Operational amplifier based LC resonant circuit for adiabatic logic2017

Author(s)

Journal Title

DOI

Data Source

[Journal Article] Low-power secure S-Box circuit using CSSAL for AES hardware design2015

Author(s)

Journal Title

Data Source

[Journal Article] The ramped-step voltage in adiabatic logic circuits: analysis of parameters to further reduce power dissipation2013

Author(s)

Journal Title

Data Source

[Journal Article] Low power bit-parallel cellular multiplier implementation in secure dual-rail adiabatic logic2013

Author(s)

Journal Title

DOI

Data Source

TAKAHASHI Yasuhiro 高橋康宏

高橋康宏タカハシヤスヒロ

Takahashi Yasuhiro 高橋康宏