Nakada Takashi 中田尚

… Alternative Names

NAKADA Takashi 中田尚

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Researcher Number	00452524
Other IDs
Affiliation (Current)	2025: 大阪国際工科専門職大学, 工科学部, 准教授
Affiliation (based on the past Project Information) *help	2017 – 2020: 奈良先端科学技術大学院大学, 先端科学技術研究科, 准教授 2017: 奈良先端科学技術大学院大学, 情報科学研究科, 助教 2013 – 2015: 東京大学, 情報理工学(系)研究科, 助教 2012: 東京大学, 大学院・情報理工学系研究科, 特任助教 2012: 東京大学, 情報理工学(系)研究科, 特任助教 2007 – 2011: Nara Institute of Science and Technology, Graduate School of Information Science, Assistant Professor
Review Section/Research Field	Principal Investigator Computer system / Computer system/Network Except Principal Investigator Computer system / Computer system/Network
Keywords	Principal Investigator 計算機アーキテクチャ / シミュレーション / 高速シミュレーション / 共有キャッシュ / メニーコアプロセッサ / 性能評価 / ハイパフォーマンスコンピューティング / 超高速情報処理 / 省エネルギー / 計算機システム … More Except Principal Investigator … More 計算機システム / ハイパフォーマンス・コンピューティング / 省電力 / スケジューリング / 実行モデル / 低消費エネルギー / コンピューティング / 計算機アーキテクチャ / マルチスレッディング / シストリックリング / アナログ近似計算 / 分割推論 / ＣＧＲＡ / 近似計算 / アクセラレータ / 変分ベイズ / AXIバス / カスケーディング / 次世代計算基盤 / ストカスティック計算 / VBGMM / SIMD / チップ間インタフェース / 狭メモリバンド幅 / エッジコンピューティング / シストリックアレイ / CGRA / high-performance computing / system-on-chip / computer systems / simulation engineering / 並列処理 / マイクロプロセッサ / シミュレータ / ハイパフォーマンスコンピューティング / システムオンチップ / シミュレーション工学 / 半導体超微細化 / FPGA / 自己安定回路 / 製造ばらつき / 半導体微細化 / ディペンダブル・コンピューティング / ハードウェア設計 Less

Near-memory efficient computing platform leading edge-computing
- Principal Investigator
  
  NAKASHIMA Yasuhiko
- Project Period (FY)
  2017 – 2020
- Research Category
  
  Grant-in-Aid for Scientific Research (A)
- Research Field
  
  Computer system
- Research Institution
  Nara Institute of Science and Technology
Spatial and Temporal Control of Data Processing and Energy Consumption
- Principal Investigator
  
  NAKAMURA HIROSHI
- Project Period (FY)
  2016 – 2017
- Research Category
  
  Grant-in-Aid for Challenging Exploratory Research
- Research Field
  
  Computer system
- Research Institution
  The University of Tokyo
Performance evaluation framework for design optimization of next generation low-power many core systemsPrincipal Investigator
- Principal Investigator
  
  Nakada Takashi
- Project Period (FY)
  2013 – 2015
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Computer system
- Research Institution
  The University of Tokyo
Automatic Mapping Architecture for Ultra Low Power Many-coreProcessorPrincipal Investigator
- Principal Investigator
  
  NAKADA Takashi
- Project Period (FY)
  2010 – 2012
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Computer system/Network
- Research Institution
  The University of Tokyo
  Nara Institute of Science and Technology
Multilevel Stabilizing Architecture for Overcoming Process Variation
- Principal Investigator
  
  NAKASHIMA Yasuhiko
- Project Period (FY)
  2007 – 2009
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Nara Institute of Science and Technology
High-Performance Parallel Simulation Technology for Advanced Information System Development
- Principal Investigator
  
  NAKASHIMA Hiroshi
- Project Period (FY)
  2005 – 2007
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Kyoto University
  Toyohashi University of Technology

All 2020 2019 2018 2017 2016 2012 2011 2010 2009 2008 2007 2006 2005

All Journal Article Presentation Patent

[Journal Article] Construction of an Efficient Divided/Distributed Neural Network Model Using Edge Computing2020
- Author(s)
  SHINGAI Ryuta、HIRAGA Yuria、FUKUOKA Hisakazu、MITANI Takamasa、NAKADA Takashi、NAKASHIMA Yasuhiko
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: E103.D Issue: 10 Pages: 2072-2082
- DOI
  10.1587/transinf.2019EDP7326
- NAID
  130007920598
- ISSN
  0916-8532, 1745-1361
- Year and Date
  2020-10-01
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17H00730
[Journal Article] Bayes without Bayesian Learning for Resisting Adversarial Attacks2020
- Author(s)
  Thi Thu Thao Khong, Takashi Nakada, Yasuhiko Nakashima
- Journal Title
  
  CANDAR'20
  
  Volume: CANDAR'20
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17H00730
[Journal Article] DiaNet: An Efficient Multi-Grained Re-configurable Neural Network in Silicon2019
- Author(s)
  Zhang Renyuan、Chen Yan、Nakada Takashi、Nakashima Yasuhiko
- Journal Title
  
  IEEE International System-on-Chip Conf.(SOCC)
  
  Volume: SOCC2020 Pages: 132-137
- DOI
  10.1109/socc46988.2019.1570548015
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17H00730
[Journal Article] GPGPU Implementation of Variational Bayesian Gaussian Mixture Models2019
- Author(s)
  Nishimoto Hiroki、Nakada Takashi、Nakashima Yasuhiko
- Journal Title
  
  CANDAR'19, REGULAR PAPER
  
  Volume: CANDAR'19 Pages: 185-190
- DOI
  10.1109/candar.2019.00031
- NAID
  130008165619
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17H00730
[Journal Article] Programmable Analog Calculation Unit with Two-Stage Architecture: A Solution of Efficient Vector-Computation2019
- Author(s)
  ZHANG Renyuan、NAKADA Takashi、NAKASHIMA Yasuhiko
- Journal Title
  
  IEICE Trans. Fundamentals
  
  Volume: E102.A Issue: 7 Pages: 878-885
- DOI
  10.1587/transfun.E102.A.878
- NAID
  130007670860
- ISSN
  0916-8508, 1745-1337
- Year and Date
  2019-07-01
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17H00730
[Journal Article] A Tree-based Checkpointing Architecture for the Dependability of FPGA Computing2018
- Author(s)
  Hoang-Gia VU, Shinya TAKAMAEDA-YAMAZAKI, Takashi NAKADA, and Yasuhiko NAKASHIMA
- Journal Title
  
  IEICE TRANSACTIONS on Information and Systems
  
  Volume: Vol.E101-D No.2 Pages: 288-302
- NAID
  130006328488
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17H00730
[Journal Article] A programmable analog calculation unit for vector computations2018
- Author(s)
  Uetake Noriyuki、Zhang Renyuan、Nakada Takashi、Nakashima Yasuhiko
- Journal Title
  
  2018 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)
  
  Volume: - Pages: 1-3
- DOI
  10.1109/coolchips.2018.8373080
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17H00730
[Journal Article] Design of Programmable Analog Calculation Unit by Implementing Support Vector Regression for Approximate Computing2018
- Author(s)
  Zhang Renyuan、Uetake Noriyuki、Nakada Takashi、Nakashima Yasuhiko
- Journal Title
  
  IEEE Micro
  
  Volume: 38 Issue: 6 Pages: 73-82
- DOI
  10.1109/mm.2018.2873953
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17H00730
[Journal Article] Efficient Multitasking on FPGA Using HDL-based Checkpointing2018
- Author(s)
  Hoang Gia Vu, Takashi Nakada, and Yasuhiko Nakashima
- Journal Title
  
  ARC2018
  
  Volume: ARC2018
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17H00730
[Journal Article] A Programmable Analog Calculation Unit for Vector Computations2018
- Author(s)
  Noriyuki Uetake, Renyuan Zhang, Takashi Nakada, and Yasuhiko Nakashima
- Journal Title
  
  COOLCHIPS2018
  
  Volume: COOLCHIPS2018
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17H00730
[Journal Article] CPRring: A Structure-aware Ring-based Checkpointing Architecture for FPGA Computing2017
- Author(s)
  Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, Yasuhiko Nakashima
- Journal Title
  
  FCCM2017
  
  Volume: FCCM2017 Pages: 192-192
- DOI
  10.1109/fccm.2017.60
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17H00730
[Journal Article] A Feasibility Study of Programmable Analog Calculation Unit for Approximate Computing2017
- Author(s)
  Renyuan Zhang, Takashi Nakada and Yasuhiko Nakashima
- Journal Title
  
  CANDAR'17
  
  Volume: CANDAR'17 Pages: 180-186
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17H00730
[Journal Article] Maintaining Razor DVSEfficiency in Large IR-drop Zones by anAdaptive Redundant Data-PathIEICETRANSACTIONS on Fundamentals ofElectronics2012
- Author(s)
  Yukihiro SASAGAWA, Jun YAO, TakashiNAKADA, and Yasuhiko NAKASHIMA:RazorProtector
- Journal Title
  
  Communications andComputer Sciences
  
  Volume: Vol.E95-A No.12 Pages: 2319-2329
- Data Source
  KAKENHI-PROJECT-22700053
[Journal Article] 時分割実行機構による演算器アレイ型アクセラレータの効率化2012
- Author(s)
  岩上拓也,吉村和浩,中田尚,中島康彦:
- Journal Title
  
  情報処理学会論文誌コンピューティングシステム
  
  Volume: Vol.5,No.4 (ACS39) Pages: 13-23
- NAID
  40019469346
- Data Source
  KAKENHI-PROJECT-22700053
[Journal Article] 画像処理向け線形アレイアクセラレータの性能評価2012
- Author(s)
  中田尚
- Journal Title
  
  情報処理学会論文誌コンピューティングシステム
  
  Volume: 5 Pages: 74-85
- NAID
  40019469283
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22700053
[Journal Article] 線形演算器アレイ型アクセラレータを備えた高電力効率プロセッサの開発2012
- Author(s)
  齊藤光俊, 下岡俊介D.V.R. Naveen, 大上俊, 吉村和浩, 姚駿, 中田尚, 中島康彦
- Journal Title
  
  電子情報通信学会論文誌D
  
  Volume: Vol.J95-D,No.9
- Data Source
  KAKENHI-PROJECT-22700053
[Journal Article] 画像処理向け線形アレイアクセラレータの性能評価,2012
- Author(s)
  中田尚,吉村和浩,下岡俊介,大上俊,Naveen, D.V.R.,中島康彦
- Journal Title
  
  情報処理学会論文誌コンピューティングシステム
  
  Volume: Vol.5, No.3 (ACS38) Pages: 74-85
- NAID
  40019469283
- Data Source
  KAKENHI-PROJECT-22700053
[Journal Article] An InstructionMapping Scheme forFUArray Accelerator2011
- Author(s)
  Kazuhiro Yoshimura,Takuya Iwakami,Takashi Nakada, Jun Yao, Hajime Shimada,YasuhikoNakashima
- Journal Title
  
  IEICE Transactions on Information and Systems
  
  Volume: Vol.E94-D, No.2, Pages: 286-297
- Data Source
  KAKENHI-PROJECT-22700053
[Journal Article] 演算器アレイ型プロセッサのための命令スケジューラの設計と評価2010
- Author(s)
  吉村和浩, 上利宗久, 中田尚, 中島康彦
- Journal Title
  
  電子情報通信学会技術研究報告 Vol.109, No.474
  
  Pages: 511-516
- NAID
  110008000695
- Data Source
  KAKENHI-PROJECT-19300012
[Journal Article] An Energy Efficient SMT Processor with Heterogeneous Instruction Set Architectures2010
- Author(s)
  Kazuhiro Yoshimura, Takashi Nakada, Yasuhiko Nakashima, Toshiaki Kitamura
- Journal Title
  
  IASTED Int'l Conf. on Parallel and Distributed Computing and Networks (PDCN2010)
  
  Pages: 201-209
- Data Source
  KAKENHI-PROJECT-19300012
[Journal Article] 少品種高信頼セルを用いた高信頼回路設計手法と信頼性評価手法の提案2010
- Author(s)
  大賀健司, 姚駿, 中田尚, 嶋田創, 山下茂, 中島康彦
- Journal Title
  
  電子情報通信学会技術研究報告 Vol.109, No.474
  
  Pages: 139-146
- NAID
  110007995055
- Data Source
  KAKENHI-PROJECT-19300012
[Journal Article] An Energy Efficient SMT Processor with Heterogeneous Instruction Set Architectures2010
- Author(s)
  Kazuhiro Yoshimura, Takashi Nakada, Yasuhiko Nakashima, Toshiaki Kitamura
- Journal Title
  
  IASTED Int'l Conf. on Parallel and Distributed Computing and Networks PDCN2010
  
  Pages: 201-209
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19300012
[Journal Article] 画像処理向け線形アレイVLIWプロセッサ2009
- Author(s)
  中田尚, 上利宗久, 中島康彦
- Journal Title
  
  先進的計算基盤システムシンポジウムSACSIS2009論文集 SACSIS2009論文集
  
  Pages: 293-300
- Data Source
  KAKENHI-PROJECT-19300012
[Journal Article] VLIW型命令キューを持つスーパースカラプロセッサの命令スケジューリング機構2009
- Author(s)
  中田尚, 片岡晶人, 中島康彦
- Journal Title
  
  情報処理学会論文誌コンピューティングシステム ACS26, Vol.2, No.2
  
  Pages: 48-62
- NAID
  110007990230
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19300012
[Journal Article] 線形アレイVLIWプロセッサにおける適応性検討2009
- Author(s)
  中田尚, 中島康彦
- Journal Title
  
  情報処理学会研究報告 Vol.2009-ARC-186, No.10, HOKKE-17
  
  Pages: 1-9
- NAID
  110007997603
- Data Source
  KAKENHI-PROJECT-19300012
[Journal Article] VLIW型命令キューを持つスーパースカラプロセッサの命令スケジューリング機構2009
- Author(s)
  中田尚, 片岡晶人, 中島康彦
- Journal Title
  
  情報処理学会論文誌コンピューティングシステム ACS26,Vol.2,No.2
  
  Pages: 48-62
- NAID
  110007990230
- Data Source
  KAKENHI-PROJECT-19300012
[Journal Article] 画像処理向け線形アレイVLIWプロセッサ2009
- Author(s)
  中田尚, 上利宗久, 中島康彦
- Journal Title
  
  先進的計算基盤システムシンポジウム論文集 SACSIS2009
  
  Pages: 293-300
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19300012
[Journal Article] A Simulation-Based Analysis for Worst Case Delay of Single and Multiple Interruptions2008
- Author(s)
  Hiroshi, Nakashima, Masahiro, Konishi, Takashi, Nakada
- Journal Title
  
  IPSJ Trans System LSI Design Methodology 1(1)(in Press)
- NAID
  110009598008
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300015
[Journal Article] OROCHI : A Multiple Instruction Set SMT Processor2008
- Author(s)
  Takashi Nakada
- Journal Title
  
  Proc. of First International Workshop on New Frontiers in High-performance and Hardware-aware Computing HipHaC'08
  
  Pages: 1-8
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19300012
[Journal Article] A Functional Unit with Small Variety of Highly Reliable Cells2008
- Author(s)
  Kazunori SUZUKI, Takashi NAKADA, Masaki NAKANISHI, Shigeru YAMASHITA, Yasuhiko NAKASHIMA
- Journal Title
  
  14th Pacific Rim International Symposium on Dependable Computing (PRDC'08)
  
  Pages: 353-354
- Data Source
  KAKENHI-PROJECT-19300012
[Journal Article] OROCHI: A Multiple Instruction Set SMT Processor2008
- Author(s)
  Takashi Nakada, Yasuhiko Nakashima, Hajime Shimada, Kenji Kise, Toshiaki Kitamura
- Journal Title
  
  First International Workshop on New Frontiers in High-performance and Hardware-aware Computing(HipHaC'08)
  
  Pages: 1-8
- Data Source
  KAKENHI-PROJECT-19300012
[Journal Article] A Simulation-Based Analysis for Worst Case Delay of Single and Multiple Interruptions2008
- Author(s)
  H. Nakashima, M. Konishi, T. Nakada
- Journal Title
  
  IPSJ Trans. System LSI Design Methodology 1(1)(in press)
- NAID
  110009598008
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300015
[Journal Article] An Efficient Analysis of Worst Case Flush Timings for Branch Predictors2007
- Author(s)
  M.Konishi, T.Nakada, T.Tsumura, H.Nakashima, H.Takada
- Journal Title
  
  IPSJ Trans. Advanced Computing Systems 48・(ACS18)
- NAID
  110004829189
- Data Source
  KAKENHI-PROJECT-17300015
[Journal Article] An Efficient Analysis of Worst Case Flush Timings for Branch Predictors2007
- Author(s)
  M. Konishi, T. Nakada, T. Tsumura, H. Nakashima, H. Takada
- Journal Title
  
  IPSJ Trans. Advanced Computing Systems 48(SIG8)
  
  Pages: 127-140
- NAID
  110004829189
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300015
[Journal Article] An Efficient Analysis of Worst Case Flush Timings for Branch Predictors2007
- Author(s)
  Masahiro, Konishi, Takashi, Nakada, Tomoaki, Tsumura, Hiroshi, Nakashima, Hiroaki, Takada
- Journal Title
  
  IPSJ Trans Advanced Computing Systems 48(SIG8)
  
  Pages: 127-140
- NAID
  110004829189
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300015
[Journal Article] 時間軸分割並列マイクロプロセッサシミュレータの高速化と評価2007
- Author(s)
  矢野聖宗, 高崎透, 中田尚, 中島浩
- Journal Title
  
  情報処理学会研究報告 2007-ARC-172
  
  Pages: 187-192
- NAID
  110006249891
- Data Source
  KAKENHI-PROJECT-17300015
[Journal Article] An Accurate and Efficient Time-Division Parallelization of Cycle Accurate Architectural Simulators2007
- Author(s)
  M.Yano, T.Takasaki, T.Nakada, H.Nakashima
- Journal Title
  
  Proc. 40th Annual Simulation Symp.
  
  Pages: 247-255
- Data Source
  KAKENHI-PROJECT-17300015
[Journal Article] An Efficient Analysis of Worst Case Flush Timings for Branch Predictors2007
- Author(s)
  Masahiro Konishi, Takashi Nakada, Tomoaki Tsumura, Hiroshi Nakashima, Hiroaki Takada
- Journal Title
  
  IPSJ Trans. Advanced Computing Systems 48
  
  Pages: 127-140
- NAID
  110004829189
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300015
[Journal Article] 重複実行省略を用いた割り込みによるマイクロプロセッサの最悪性能予測2006
- Author(s)
  小西昌裕, 中田尚, 津邑公暁, 中島浩
- Journal Title
  
  情報処理学会論文誌 : コンピューティングシステム 47・SIG12
  
  Pages: 159-170
- Data Source
  KAKENHI-PROJECT-17300015
[Journal Article] CASによる最悪割込遅延解析の高速化2006
- Author(s)
  中島浩, 小西昌裕, 中田尚
- Journal Title
  
  情報処理学会研究報告 2006-ARC-169
  
  Pages: 115-120
- NAID
  110004824138
- Data Source
  KAKENHI-PROJECT-17300015
[Journal Article] 分岐予測器の最悪フラッシュタイミングの効率的解析手法2006
- Author(s)
  小西昌裕, 中島浩, 中田尚, 津邑公暁, 高田広章
- Journal Title
  
  情報処理学会研究報告 2006-EMB-1
  
  Pages: 1-6
- NAID
  110004829189
- Data Source
  KAKENHI-PROJECT-17300015
[Journal Article] 重複実行省略を用いた割り込みによるマイクロプロセッサの最悪性能予測2006
- Author(s)
  小西昌裕, 中田尚, 津邑公暁, 中島浩
- Journal Title
  
  情報処理学会論文誌:コンピューティングシステム 47(SIG12)
  
  Pages: 159-170
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300015
[Journal Article] An Accurate and Efficient Simulation-Based Analysis for Worst Case Interruption Delay2006
- Author(s)
  H.Nakashima, M.Konishi, T.Nakada
- Journal Title
  
  Proc. Intl. Conf. Compilers, Architecture and Synthesis for Embedded Systems
  
  Pages: 2-12
- Data Source
  KAKENHI-PROJECT-17300015
[Journal Article] Measuring Worst-Case Performance of Microprocessor by Interruption with Omitting Redundant Execution(in Japanese)2006
- Author(s)
  Masahiro, Konishi, Takashi, Nakada, Tomoaki, Tsumura, Hiroshi, Nakashima
- Journal Title
  
  IPSJ Trans Advanced Computing Systems 47(SIG12)
  
  Pages: 159-170
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300015
[Journal Article] Design and Implementation of a Workload Specific Simulator2006
- Author(s)
  T.Nakada, T.Tsumura, H.Nakashima
- Journal Title
  
  Proc. 39th Annual Simulation Symp.
  
  Pages: 230-243
- Data Source
  KAKENHI-PROJECT-17300015
[Journal Article] 時間軸分割並列マイクロプロセッサシミュレータの高速化手法2006
- Author(s)
  矢野聖宗, 中田尚, 津邑公暁, 中島浩
- Journal Title
  
  情報処理学会研究報告 2006-ARC-169
  
  Pages: 139-144
- NAID
  110004824142
- Data Source
  KAKENHI-PROJECT-17300015
[Journal Article] 時間軸分割並列化による高速マイクロプロセッサシミュレーション2005
- Author(s)
  高崎透, 中田尚, 津邑公暁, 中島浩
- Journal Title
  
  情報処理学会論文誌:コンピューティングシステム 46(SIG12)
  
  Pages: 84-97
- NAID
  110002769826
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300015
[Journal Article] 時間軸分割並列化による高速マイクロプロセッサシミュレーション2005
- Author(s)
  高崎透, 中田尚, 津邑公暁, 中島浩
- Journal Title
  
  情報処理学会論文誌:コンピューティングシステム 46・SIG12
  
  Pages: 84-97
- NAID
  110002769826
- Data Source
  KAKENHI-PROJECT-17300015
[Journal Article] ワークロード最適化シミュレータの設計と実装2005
- Author(s)
  中田尚, 津邑公暁, 中島浩
- Journal Title
  
  情報処理学会論文誌:コンピューティングシステム 46・SIG12
  
  Pages: 98-109
- NAID
  110002769827
- Data Source
  KAKENHI-PROJECT-17300015
[Journal Article] 時間軸分割並列化による高速マイクロプロセッサシミュレーション2005
- Author(s)
  高崎透, 中田尚, 津邑公暁, 中島浩
- Journal Title
  
  先端計算基盤シンポジウムSACSIS2005
  
  Pages: 339-348
- NAID
  110002769826
- Data Source
  KAKENHI-PROJECT-17300015
[Journal Article] Fast Simulation of High Performance Processor with Time Division Parallelization(in Japanese)2005
- Author(s)
  Toru, Takasaki, Takashi, Nakada, Tomoaki, Tsumura, Hiroshi, Nakashima
- Journal Title
  
  IPSJ Trans Advanced Computing Systems 46(SIG12)
  
  Pages: 84-97
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300015
[Journal Article] ワークロード最適化シミュレータの設計と実装2005
- Author(s)
  中田尚, 津邑公暁, 中島浩
- Journal Title
  
  先端計算基盤シンポジウムSACSIS2005
  
  Pages: 329-338
- NAID
  110002769827
- Data Source
  KAKENHI-PROJECT-17300015
[Journal Article] ワークロード最適化シミュレータの設計と実装2005
- Author(s)
  中田尚, 津邑公暁, 中島浩
- Journal Title
  
  情報処理学会論文誌:コンピューティングシステム 46(SIG12)
  
  Pages: 98-109
- NAID
  110002769827
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300015
[Journal Article] Design and Implementation of a Workload Optimized Simulator (in Japanese)2005
- Author(s)
  Takashi, Nakada, Tomoaki, Tsumura, Hiroshi, Nakashima
- Journal Title
  
  IPSJ Trans Advanced Computing Systems 46(SIG12)
  
  Pages: 98-109
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300015
[Patent] プロセッサ2008
- Inventor(s)
  中田尚, 中島康彦
- Industrial Property Rights Holder
  STARC
- Industrial Property Number
  2008-183828
- Filing Date
  2008-07-15
- Data Source
  KAKENHI-PROJECT-19300012
[Patent] データ処理装置2008
- Inventor(s)
  中島康彦, 中田尚
- Industrial Property Rights Holder
  奈良先端大
- Industrial Property Number
  2008-265312
- Filing Date
  2008-10-14
- Data Source
  KAKENHI-PROJECT-19300012
[Presentation] 分散CNNにおける通信効率化のための圧縮技術の比較検討2020
- Author(s)
  新谷隆太, 中田尚, 中島康彦
- Organizer
  信学技報, vol.119, no.147, CPSY2019-36
- Data Source
  KAKENHI-PROJECT-17H00730
[Presentation] GPGPUを用いた変分混合ガウスモデルのパラメータ推定高速化2020
- Author(s)
  西本宏樹,中田尚,中島康彦
- Organizer
  信学技報, vol.119, no.76, CPSY2019-1, pp.1-5
- Data Source
  KAKENHI-PROJECT-17H00730
[Presentation] 変分混合ガウスモデルアクセラレータ設計のための変分推論アルゴリズムの解析2018
- Author(s)
  西本宏樹, 中田尚, 中島康彦
- Organizer
  信学技報, vol.118, no.334, VLD2018-62, pp.155-160
- Data Source
  KAKENHI-PROJECT-17H00730
[Presentation] 共有 CNN を用いた高効率な分割推論実行モデル2018
- Author(s)
  平賀由利亜, 福岡久和, 三谷剛正, 中田尚, 中島康彦
- Organizer
  xSIG 2018: The 2nd. cross-disciplinary Workshop on Computing Systems, Infrastructures, and Programming
- Data Source
  KAKENHI-PROJECT-17H00730
[Presentation] A Multi-Level Power-Capping Mechanism for FPGAs2017
- Author(s)
  Keisuke Fujimoto, Takashi Nakada, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima
- Organizer
  xSIG2017
- Data Source
  KAKENHI-PROJECT-17H00730
[Presentation] A Programmable Analog Calculation Unit based on Support Vector Regression2017
- Author(s)
  Renyuan Zhang, Takashi Nakada, Yasuhiko Nakashima
- Organizer
  電子情報通信学会コンピュータシステム研究会
- Data Source
  KAKENHI-PROJECT-17H00730
[Presentation] エッジコンピューティングによる分散ニューラルネットワークの構想2017
- Author(s)
  平賀由利亜, 三谷剛正, 福岡久和, 中田尚, 中島康彦
- Organizer
  電子情報通信学会コンピュータシステム研究会
- Data Source
  KAKENHI-PROJECT-17H00730
[Presentation] Normally-off Power Management for Sensor Nodes of Global Navigation Satellite System2016
- Author(s)
  Takashi Nakada, Toshifumi Nakamoto, Toru Shimizu, Hiroshi Nakamura
- Organizer
  The 13th International SoC Design Conference
- Place of Presentation
  Jeju, South Korea
- Year and Date
  2016-10-23
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16K12405
[Presentation] An Adaptive Energy-Efficient Task Scheduling under Execution Time Variation based on Statistical Analysis2016
- Author(s)
  Takashi Nakada, Tomoki Hatanaka, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura
- Organizer
  IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
- Place of Presentation
  Tallinn, ESTONIA
- Year and Date
  2016-09-26
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16K12405
[Presentation] 仮想化機構による演算器アレイ型アクセラレータの効率化2011
- Author(s)
  岩上拓矢,吉村和浩,中田尚,中島康彦
- Organizer
  先進的計算基盤システムシンポジウムSACSIS2011論文集
- Data Source
  KAKENHI-PROJECT-22700053
[Presentation] ImprovingDVS Efficiency byTolerating IR-dropswith an Adaptive Redundant Data-Path",2011
- Author(s)
  Yukihiro SASAGAWA, Jun YAO, TakashiNAKADA, Yasuhiko NAKASHIMA
- Organizer
  WRA 2011 : 2nd Workshop on ResilientArchitectures
- Data Source
  KAKENHI-PROJECT-22700053
[Presentation] 演算器アレイ型プロセッサのための命令スケジューラの設計と評価2010
- Author(s)
  上利宗久, 中田尚, 中島康彦
- Organizer
  信学技報
- Place of Presentation
  八丈島
- Data Source
  KAKENHI-PROJECT-19300012
[Presentation] 少品種高信頼セルを用いた高信頼回路設計手法と信頼性評価手法の提案2010
- Author(s)
  大賀健司, 姚駿, 中田尚, 嶋田創, 山下茂, 中島康彦
- Organizer
  信学技報
- Place of Presentation
  八丈島
- Data Source
  KAKENHI-PROJECT-19300012
[Presentation] A Linear Array VLIW Processor for Image Processing2009
- Author(s)
  Munehisa Agari, Takashi Nakada, Yasuhiko Nakashima
- Organizer
  IEEE Symposium on Low-Power and High-Speed Chips 2009 (poster)
- Place of Presentation
  横浜
- Data Source
  KAKENHI-PROJECT-19300012
[Presentation] 異種命令混在実行プロセッサOROCHIの開発2009
- Author(s)
  吉村和浩, 市来亮人, 中田尚, 中島康彦
- Organizer
  電子情報通信学会LSIとシステムのワークショップ
- Place of Presentation
  福岡
- Year and Date
  2009-05-19
- Data Source
  KAKENHI-PROJECT-19300012
[Presentation] 異種命令混在実行プロセッサOROCHIの開発2009
- Author(s)
  吉村和浩, 市来亮人, 中田尚, 中島康彦
- Organizer
  電子情報通信学会LSIとシステムのワークショップ
- Place of Presentation
  北九州市
- Data Source
  KAKENHI-PROJECT-19300012
[Presentation] A Linear Array VLIW Processor for Image Processing2009
- Author(s)
  Munehisa Agari, Takashi Nakada, Yasuhiko Nakashima
- Organizer
  IEEE Symposium on Low-Power and High-Speed Chips 2009
- Place of Presentation
  横浜
- Year and Date
  2009-04-16
- Data Source
  KAKENHI-PROJECT-19300012
[Presentation] 二線式論理を用いた面積効率の良い高信頼演算器2009
- Author(s)
  大賀健司, 中田尚, 嶋田創, 山下茂, 中島康彦
- Organizer
  2009年度情報処理学会関西支部大会講演論文集
- Place of Presentation
  神戸
- Data Source
  KAKENHI-PROJECT-19300012
[Presentation] 線形アレイ型VLIWプロセッサの面積効率評価2009
- Author(s)
  上利宗久, 中田尚, 中島康彦
- Organizer
  平成21年度情報処理学会関西支部大会講演論文集
- Place of Presentation
  神戸
- Data Source
  KAKENHI-PROJECT-19300012
[Presentation] 線形アレイ型VLIWプロセッサの面積効率評価2009
- Author(s)
  上利宗久, 中田尚, 中島康彦
- Organizer
  平成21年度情報処理学会関西支部大会
- Place of Presentation
  神戸大学
- Year and Date
  2009-09-29
- Data Source
  KAKENHI-PROJECT-19300012
[Presentation] 線形アレイVLIWプロセッサにおける適応性検討2009
- Author(s)
  中田尚, 中島康彦
- Organizer
  情報処理学会研究報告
- Place of Presentation
  札幌
- Data Source
  KAKENHI-PROJECT-19300012
[Presentation] 二線式論理を用いた面積効率の良い高信頼演算器2009
- Author(s)
  大賀健司, 中田尚, 嶋田創, 山下茂, 中島康彦
- Organizer
  平成21年度情報処理学会関西支部大会
- Place of Presentation
  神戸大学
- Year and Date
  2009-09-29
- Data Source
  KAKENHI-PROJECT-19300012
[Presentation] 異種命令SMTプロセッサOROCHIの実装と分析2008
- Author(s)
  吉村和浩, 中田尚, 中島康彦
- Organizer
  SWoPP2008
- Place of Presentation
  佐賀市
- Data Source
  KAKENHI-PROJECT-19300012
[Presentation] 異種命令SMTプロセッサOROCHIのASIC試作における問題と対策2008
- Author(s)
  市来亮人, 吉村和浩, 中田尚, 中島康彦
- Organizer
  2008年度情報処理学会関西支部大会講演論文集
- Place of Presentation
  京都市
- Data Source
  KAKENHI-PROJECT-19300012
[Presentation] N倍速を目指すVLIWプロセッサの構想2008
- Author(s)
  上利宗久, 中田尚, 中島康彦
- Organizer
  IPSJ SIG Technical Report
- Place of Presentation
  筑紫野市
- Data Source
  KAKENHI-PROJECT-19300012
[Presentation] 異種命令混在実行プロセッサにおけるプロセススケジューリング手法2008
- Author(s)
  山原幹雄, 中田尚, 中島康彦
- Organizer
  IPSJ SIG Technical Report
- Place of Presentation
  札幌
- Data Source
  KAKENHI-PROJECT-19300012
[Presentation] 高信頼セルによる回路の信頼性言平価2008
- Author(s)
  堀田敬一, 中田尚, 中西正樹, 山下茂, 中島康彦
- Organizer
  IEICE Technical Report
- Place of Presentation
  北九州市
- Data Source
  KAKENHI-PROJECT-19300012
[Presentation] 少品種高信頼セルによる演算器の提案と評価2008
- Author(s)
  鈴木一範, 中田尚, 中西正樹, 山下茂, 中島康彦
- Organizer
  信学技報
- Place of Presentation
  屋久島町
- Data Source
  KAKENHI-PROJECT-19300012
[Presentation] A QoS Control Method for a Heterogeneous SMT Processor2008
- Author(s)
  Kazuhiro Yoshimura, Takashi Nakada, Yasuhiko Nakashima
- Organizer
  IEEE Symposium on Low-Power and High-Speed Chips 2008 (poster)
- Place of Presentation
  横浜市
- Data Source
  KAKENHI-PROJECT-19300012
[Presentation] A Hybrid Platform for Practical Evaluation of Processors2008
- Author(s)
  Akihito Ichiki, Takashi Nakada, Yasuhiko Nakashima
- Organizer
  IEEE Symposium on Low-Power and High-Speed Chips 2008 (poster)
- Place of Presentation
  横浜市
- Data Source
  KAKENHI-PROJECT-19300012
[Presentation] 高信頼セルによる演算器の耐故障性と遅延時間の評価2008
- Author(s)
  鈴木一範, 中田尚, 中西正樹, 山下茂, 中島康彦
- Organizer
  SWoPP2008
- Place of Presentation
  佐賀市
- Data Source
  KAKENHI-PROJECT-19300012
[Presentation] パイプラインプロセッサ上でのMIN-TAGE予測器の性能評価2008
- Author(s)
  牟田口公洋, 中田尚, 中島康彦
- Organizer
  IPSJ SIG Technical RePort
- Place of Presentation
  札幌
- Data Source
  KAKENHI-PROJECT-19300012
[Presentation] SRAMベースFPGAにおける耐ソフトエラーLUT構成法2007
- Author(s)
  里山宏平, 中田尚, 中西正樹, 山下茂, 中島康彦
- Organizer
  IEICE Technical Report
- Place of Presentation
  北九州市
- Data Source
  KAKENHI-PROJECT-19300012
[Presentation] 異種命令セットを同時に実行するマルチスレッディング・プロセッサの構成2007
- Author(s)
  須賀圭一, 山原幹雄, 中田尚, 中島康彦
- Organizer
  SWoPP2007
- Place of Presentation
  旭川
- Data Source
  KAKENHI-PROJECT-19300012
[Presentation] An Accurate and Efficient Time-Division Parallelization of Cycle Accurate Architectural Simulators2007
- Author(s)
  Masahiro, Yana, Toru, Takasaki, Takashi, Nakada, Hiroshi, Nakashima
- Organizer
  40th Annual. Simulation Symp
- Place of Presentation
  Norfolk, VA, USA
- Year and Date
  2007-03-28
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300015
[Presentation] 異種命令混在実行のためのVLIW型命令キューの設計2007
- Author(s)
  中田尚
- Organizer
  IPSJ SIG Technical Report, 2007-ARC-175, pp.89-94
- Place of Presentation
  北九州国際会議場
- Year and Date
  2007-11-22
- Data Source
  KAKENHI-PROJECT-19300012
[Presentation] An Accurate and Efficient Time-Division Parallelization of Cycle Accurate Architectural Simulators2007
- Author(s)
  M. Yano, T. Takasaki, T. Nakada, H. Nakashima
- Organizer
  40th Annual Simulation Symp.
- Place of Presentation
  Norfolk, VA, USA
- Year and Date
  2007-03-28
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300015
[Presentation] 異種命令混在実行のためのVLIW型命令キューの設計2007
- Author(s)
  中田尚, 中島康彦
- Organizer
  IPSJ SIG Technical Report
- Place of Presentation
  北九州市
- Data Source
  KAKENHI-PROJECT-19300012
[Presentation] 細粒度命令分解と少品種セルによる高信頼化アーキテクチャの提案2007
- Author(s)
  鈴木一範, 中田尚, 中西正樹, 山下茂, 中島康彦
- Organizer
  IPSJ SIG Technical Report
- Place of Presentation
  北九州市
- Data Source
  KAKENHI-PROJECT-19300012
[Presentation] アウトオブオーダー実行におけるマルチバンク構成レジスタファイルの評価2007
- Author(s)
  片岡晶人, 中田尚, 中島康彦
- Organizer
  2007年度情報処理学会関西支部大会講演論文集
- Place of Presentation
  大阪市
- Data Source
  KAKENHI-PROJECT-19300012
[Presentation] Design and Implementation of a Workload Specific Simulator2006
- Author(s)
  T. Nakada, T. Tsumura, H. Nakashima
- Organizer
  39th Annual Simulation Symp.
- Place of Presentation
  Huntsville, AL, USA
- Year and Date
  2006-04-05
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300015
[Presentation] An Accurate and Efficient Simulation-Based Analysis for Worst Case Interruption Delay2006
- Author(s)
  H. Nakashima, M. Konishi, T. Nakada
- Organizer
  Intl. Conf. Compilers, Architecture and Synthesis for Embedded Systems
- Place of Presentation
  Seoul, Korea
- Year and Date
  2006-10-23
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300015
[Presentation] 重複実行省略を用いた割り込みによるマイクロプロセッサの最悪性能予測2006
- Author(s)
  小西昌裕, 中田尚, 津邑公暁, 中島浩
- Organizer
  先端的計算基盤システムシンポジウムSACSIS 2006
- Place of Presentation
  大阪市
- Year and Date
  2006-05-23
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300015
[Presentation] NakashimaDesign and Implementation of a Workload Specific Simulator2006
- Author(s)
  Takashi, Nakada, Tomoaki, Tsumura, Hiroshi
- Organizer
  39th Annual Simulation Symp
- Place of Presentation
  Huntsville, AL, USA
- Year and Date
  2006-04-05
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300015
[Presentation] Measuring Worst-Case Performance of Microprocessor by Interruption with Omitting Redundant Execution (in Japanese)2006
- Author(s)
  Masahiro, Konishi, Takashi, Nakada, Tomoaki, Tsumura, Hiroshi, Nakashima
- Organizer
  Symp. Advanced Computing Systems and Infrastructures
- Place of Presentation
  Osaka
- Year and Date
  2006-05-23
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300015
[Presentation] ワークロード最適化シミュレータの設計と実装2005
- Author(s)
  中田尚, 津邑公暁, 中島浩
- Organizer
  先端的計算基盤システムシンポジウムSACSIS 2005
- Place of Presentation
  つくば市
- Year and Date
  2005-05-20
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300015
[Presentation] Fast Cache Simulation Using Workload Optimiation(in Japanese, IPSJ CS-Region Young Researcher Award)2005
- Author(s)
  Takashi, Nakada, Tomoaki, Tsumura, Hiroshi, Nakashima
- Organizer
  IPSJ SIGARC meeting
- Place of Presentation
  Takeo, Saga
- Year and Date
  2005-08-04
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300015
[Presentation] Fast Simulation of High Performance Processor with Time Division Parallelization(in Japanese)2005
- Author(s)
  Toru, Takasaki, Takashi, Nakada, Tomoaki, Tsumura, Hiroshi, Nakashima
- Organizer
  Symp. Advanced Computing Systems and Infrastructures
- Place of Presentation
  Tsukuba
- Year and Date
  2005-05-20
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300015
[Presentation] 時間軸分割並列化による高速マイクロプロセッサシミュレーション2005
- Author(s)
  高崎透, 中田尚, 津邑公暁, 中島浩
- Organizer
  先端的計算基盤システムシンポジウムSACSIS 2005
- Place of Presentation
  つくば市
- Year and Date
  2005-05-20
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300015
[Presentation] ワークロード最適化によるキャッシュシミュレータの高速化2005
- Author(s)
  中田尚, 津邑公暁, 中島浩
- Organizer
  情報処理学会計算機アーキテクチャ研究会(CS領域奨励賞受賞論文)
- Place of Presentation
  佐賀県武雄市
- Year and Date
  2005-08-04
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300015
[Presentation] Design and Implementation of a Workload Optimized Simulator(in Japanese)2005
- Author(s)
  Takashi, Nakada, Tomoaki, Tsumura, Hiroshi, Nakashima
- Organizer
  Symp. Advanced Computing Systems and Infrastructures
- Place of Presentation
  Tsukuba
- Year and Date
  2005-05-20
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300015

1. NAKASHIMA Yasuhiko (00314170)

# of Collaborated Projects: 2 results

# of Collaborated Products: 54 results
2. YAMASHITA Shigeru (30362833)

# of Collaborated Projects: 1 results

# of Collaborated Products: 10 results
3. NAKANISHI Masaki (40324967)

# of Collaborated Projects: 1 results

# of Collaborated Products: 6 results
4. NAKASHIMA Hiroshi (10243057)

# of Collaborated Projects: 1 results

# of Collaborated Products: 36 results
5. TSUMURA Tomoaki (00335233)

# of Collaborated Projects: 1 results

# of Collaborated Products: 28 results
6. NAKAMURA HIROSHI (20212102)

# of Collaborated Projects: 1 results

# of Collaborated Products: 2 results
7. ZHANG Renyuan (00709131)

# of Collaborated Projects: 1 results

# of Collaborated Products: 6 results

Nakada Takashi 中田 尚

NAKADA Takashi 中田 尚

Research Projects

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Near-memory efficient computing platform leading edge-computing

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Spatial and Temporal Control of Data Processing and Energy Consumption

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Performance evaluation framework for design optimization of next generation low-power many core systemsPrincipal Investigator

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Automatic Mapping Architecture for Ultra Low Power Many-coreProcessorPrincipal Investigator

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Multilevel Stabilizing Architecture for Overcoming Process Variation

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High-Performance Parallel Simulation Technology for Advanced Information System Development

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[Journal Article] Construction of an Efficient Divided/Distributed Neural Network Model Using Edge Computing2020

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[Journal Article] Bayes without Bayesian Learning for Resisting Adversarial Attacks2020

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[Journal Article] DiaNet: An Efficient Multi-Grained Re-configurable Neural Network in Silicon2019

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[Journal Article] GPGPU Implementation of Variational Bayesian Gaussian Mixture Models2019

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[Journal Article] Programmable Analog Calculation Unit with Two-Stage Architecture: A Solution of Efficient Vector-Computation2019

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[Journal Article] A Tree-based Checkpointing Architecture for the Dependability of FPGA Computing2018

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[Journal Article] A programmable analog calculation unit for vector computations2018

Nakada Takashi 中田尚

NAKADA Takashi 中田尚