IIZUKA Tetsuya 飯塚哲也

Researcher Number	10552177
Other IDs
Affiliation (Current)	2025: 東京大学, 大学院工学系研究科(工学部), 准教授
Affiliation (based on the past Project Information) *help	2025: 東京大学, 大学院工学系研究科(工学部), 准教授 2019 – 2023: 東京大学, 大学院工学系研究科(工学部), 准教授 2015 – 2018: 東京大学, 大規模集積システム設計教育研究センター, 准教授 2014: 東京大学, 工学(系)研究科(研究院), 准教授 2012 – 2013: 東京大学, 工学(系)研究科(研究院), 講師
Review Section/Research Field	Principal Investigator Electron device/Electronic equipment / Basic Section 60040:Computer system-related / Computer system/Network Except Principal Investigator Broad Section J
Keywords	Principal Investigator 集積回路 / 導波路 / ミリ波 / 時間-デジタル変換 / 電子デバイス・機器 / アナログ・デジタル変換回路 / 位相同期回路 / 高周波 / セキュリティ / 高速有線通信 … More / 信頼性 / 誘電体 / 通信 / 時間差積分 / 時間ーデジタル変換 / パルス幅 / 飛行時間型計測機器 / 時間－デジタル変換 / パルス縮小型 / 時間領域信号 / PUF / PUF ID / NBTI / 経年劣化 … More Except Principal Investigator リザバー / リーク付き積分 / ドリフト拡散 / 人工ニューロン / スローエレクトロニクス Less

Innovative Edge AI: Building the Science of Information Processing for Long-Timescale Human Interaction
- Principal Investigator
  
  井上公
- Project Period (FY)
  2025 – 2029
- Research Category
  
  Grant-in-Aid for Scientific Research (S)
- Review Section
  
  Broad Section J
- Research Institution
  National Institute of Advanced Industrial Science and Technology
大規模AIシステムを想定した誘電体導波路によるチップ間通信技術基盤の確立Principal Investigator
- Principal Investigator
  
  飯塚哲也
- Project Period (FY)
  2021 – 2023
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  The University of Tokyo
High-Speed and Reliable Wireline Communication System based on Plastic WaveguidePrincipal Investigator
- Principal Investigator
  
  Iizuka Tetsuya
- Project Period (FY)
  2017 – 2019
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  The University of Tokyo
A Fine-Resolution and Wide-Range Time-to-Digital Converter for Time-of-Flight Measurement EquipmentsPrincipal Investigator
- Principal Investigator
  
  Iizuka Tetsuya
- Project Period (FY)
  2014 – 2016
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  The University of Tokyo
Chip Identification System based on Physically Unclonable Function Utilizing Aging Effect on Nano-Scale TransistorsPrincipal Investigator
- Principal Investigator
  
  IIZUKA Tetsuya
- Project Period (FY)
  2012 – 2014
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Computer system/Network
- Research Institution
  The University of Tokyo

All 2023 2022 2021 2020 2019 2018 2016 2015 2013 2012 Other

All Journal Article Presentation Patent

[Journal Article] Analysis and simulation of MOSFET-based gate-voltage-independent capacitor2022
- Author(s)
  S. Li, N. Ojima, Z. Xu, and T. Iizuka
- Journal Title
  
  Japanese Journal of Applied Physics (JJAP)
  
  Volume: 1 Issue: 6 Pages: 1-13
- DOI
  10.35848/1347-4065/ac6406
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-20K14786, KAKENHI-PROJECT-21H03406
[Journal Article] A fractional-N MASH2-k FDC phase-locked loop architecture enabling higher-order quantisation noise shaping2022
- Author(s)
  R. Iwashita, Z.Xu, M. Osada, and T. Iizuka
- Journal Title
  
  IET Electronics Letters
  
  Volume: 58 Issue: 7 Pages: 274-276
- DOI
  10.1049/ell2.12436
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-20K14786, KAKENHI-PROJECT-22KJ0659, KAKENHI-PROJECT-21H03406
[Journal Article] Analysis of Offset Spurs in Phase-Locked-Loops Employing Harmonic-Mixer-Based Feedback With Sample-and-Hold Operation2022
- Author(s)
  Osada Masaru、Xu Zule、Shibata Ryoya、Iizuka Tetsuya
- Journal Title
  
  IEEE Transactions on Circuits and Systems I: Regular Papers
  
  Volume: 69 Issue: 12 Pages: 5072-5084
- DOI
  10.1109/tcsi.2022.3206837
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-22KJ0659, KAKENHI-PROJECT-21H03406
[Journal Article] Analysis of strong-arm comparator with auxiliary pair for offset calibration2022
- Author(s)
  S. Li, Z. Xu, and T. Iizuka
- Journal Title
  
  Springer Journal of Analog Integrated Circuits and Signal Processing
  
  Volume: 110 Issue: 3 Pages: 535-546
- DOI
  10.1007/s10470-022-01992-6
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-20K14786, KAKENHI-PROJECT-21H03406
[Journal Article] 4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop2022
- Author(s)
  IIZUKA Tetsuya、CHIN Meikan、NAKURA Toru、ASADA Kunihiro
- Journal Title
  
  IEICE Trans. Electron.
  
  Volume: E105.C Issue: 10 Pages: 544-551
- DOI
  10.1587/transele.2021CTP0001
- ISSN
  0916-8524, 1745-1353
- Year and Date
  2022-10-01
- Language
  English
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-21H03406
[Journal Article] Integrated On-Silicon and On-glass Antennas for Mm-Wave Applications2021
- Author(s)
  Mai-Khanh Nguyen Ngoc、Iizuka Tetsuya、Asada Kunihiro
- Journal Title
  
  REV Journal on Electronics and Communications
  
  Volume: 11 Pages: 8-15
- DOI
  10.21553/rev-jec.267
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-21H03406
[Journal Article] An All-Standard-Cell-Based Synthesizable SAR ADC with Nonlinearity-Compensated RDAC2021
- Author(s)
  Z. Xu, N. Ojima, S. Li, and T. Iizuka
- Journal Title
  
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  
  Volume: 29 Issue: 12 Pages: 2153-2162
- DOI
  10.1109/tvlsi.2021.3122027
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-20K14786, KAKENHI-PROJECT-21H03406
[Journal Article] A 3.2-to-3.8 GHz Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving -65 dBc In-Band Fractional Spur2020
- Author(s)
  Osada Masaru、Xu Zule、Iizuka Tetsuya
- Journal Title
  
  IEEE Solid-State Circuits Letters
  
  Volume: 3 Pages: 534-537
- DOI
  10.1109/lssc.2020.3037311
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-17H03244
[Journal Article] 11?Gb/s 140?GHz OOK modulator with 24.6?dB isolation utilising cascaded switch and amplifier‐based stages in 65?nm bulk CMOS2020
- Author(s)
  Yamazaki Daisuke、Otsuki Yoshitaka、Hara Takafumi、Khanh Nguyen Ngoc Mai、Iizuka Tetsuya
- Journal Title
  
  IET Circuits, Devices & Systems
  
  Volume: 14 Issue: 3 Pages: 322-326
- DOI
  10.1049/iet-cds.2019.0377
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17H03244
[Journal Article] A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math> </inline-formula>m CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration2019
- Author(s)
  Enomoto Ryuichi、Iizuka Tetsuya、Koga Takehisa、Nakura Toru、Asada Kunihiro
- Journal Title
  
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  
  Volume: 27 Issue: 1 Pages: 11-19
- DOI
  10.1109/tvlsi.2018.2867505
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17H03244
[Journal Article] A compact quick-start sub-mW pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool2019
- Author(s)
  Jing Wang、Iizuka Tetsuya、Xu Zule、Nakura Toru
- Journal Title
  
  IEICE Electron. Express
  
  Volume: 16 Issue: 19 Pages: 20190546-20190546
- DOI
  10.1587/elex.16.20190546
- NAID
  130007726347
- ISSN
  1349-2543
- Language
  English
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-17H03244
[Journal Article] A 140 GHz area-and-power-efficient VCO using frequency doubler in 65 nm CMOS2019
- Author(s)
  Otsuki Yoshitaka、Yamazaki Daisuke、Khanh Nguyen Ngoc Mai、Iizuka Tetsuya
- Journal Title
  
  IEICE Electron. Express
  
  Volume: 16 Issue: 6 Pages: 20190051-20190051
- DOI
  10.1587/elex.16.20190051
- NAID
  130007618892
- ISSN
  1349-2543
- Language
  English
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-17H03244
[Journal Article] Fault Detection of VLSI Power Supply Network Based on Current Estimation From Surface Magnetic Field2019
- Author(s)
  Takahashi Daigo、Iizuka Tetsuya、Mai-Khanh Nguyen Ngoc、Nakura Toru、Asada Kunihiro
- Journal Title
  
  IEEE Transactions on Instrumentation and Measurement
  
  Volume: Early Access Issue: 7 Pages: 1-12
- DOI
  10.1109/tim.2018.2866300
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17H03244
[Journal Article] Spacial Resolution Enhancement for Integrated Magnetic Probe by Two-Step Removal of Si-Substrate Beneath the Coil2015
- Author(s)
  Nguyen Ngoc Mai-Khanh, Tetsuya Iizuka, Shigeru Nakajima, and Kunihiro Asada
- Journal Title
  
  IEEE Transactions on Magnetics
  
  Volume: 51 Issue: 1 Pages: 6500404-6500404
- DOI
  10.1109/tmag.2014.2359245
- Peer Reviewed / Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-24700042
[Journal Article] Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme2012
- Author(s)
  Kazutoshi Kodama, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
- Journal Title
  
  IEICE Trans. Electron.
  
  Volume: E95.C Issue: 12 Pages: 1857-1863
- DOI
  10.1587/transele.E95.C.1857
- NAID
  10031161433
- ISSN
  0916-8524, 1745-1353
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-24700042
[Patent] Ａ／Ｄコンバータ、アナログ／デジタル変換方法2022
- Inventor(s)
  飯塚哲也, 柴田凌弥
- Industrial Property Rights Holder
  国立大学法人東京大学
- Industrial Property Rights Type
  特許
- Industrial Property Number
  2022-185120
- Filing Date
  2022
- Data Source
  KAKENHI-PROJECT-21H03406
[Patent] フラクショナル位相同期回路および位相同期回路装置2020
- Inventor(s)
  飯塚哲也, 徐祖楽, 長田将
- Industrial Property Rights Holder
  国立大学法人東京大学
- Industrial Property Rights Type
  特許
- Filing Date
  2020
- Overseas
- Data Source
  KAKENHI-PROJECT-17H03244
[Patent] フラクショナル位相同期回路および位相同期回路装置2019
- Inventor(s)
  飯塚哲也, 徐祖楽, 長田将
- Industrial Property Rights Holder
  国立大学法人東京大学
- Industrial Property Rights Type
  特許
- Industrial Property Number
  2019-192731
- Filing Date
  2019
- Data Source
  KAKENHI-PROJECT-17H03244
[Patent] 時間デジタル変換方法および時間デジタル変換装置2016
- Inventor(s)
  飯塚哲也、古賀丈尚、浅田邦博、名倉徹
- Industrial Property Rights Holder
  飯塚哲也、古賀丈尚、浅田邦博、名倉徹
- Industrial Property Rights Type
  特許
- Industrial Property Number
  2016-007517
- Filing Date
  2016-01-19
- Data Source
  KAKENHI-PROJECT-26820125
[Presentation] SiGe BiCMOS 130nmプロセスを用いた300GHz帯電力増幅回路の設計2023
- Author(s)
  堀川貴道, 加納創太, 飯塚哲也
- Organizer
  電子情報通信学会総合大会
- Data Source
  KAKENHI-PROJECT-21H03406
[Presentation] 伝送線路によるステージ間整合を応用したSiGe 130nmプロセスによる150GHz発振器の設計2022
- Author(s)
  加納創太, 飯塚哲也
- Organizer
  電子情報通信学会 LSIとシステムのワークショップ2022
- Data Source
  KAKENHI-PROJECT-21H03406
[Presentation] A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with －80-dBc Reference Spur2022
- Author(s)
  徐祖楽, 長田将, 飯塚哲也
- Organizer
  電子情報通信学会技術研究報告
- Invited
- Data Source
  KAKENHI-PROJECT-21H03406
[Presentation] An All-Standard-Cell-Based Synthesizable SAR ADC with Nonlinearity-Compensated RDAC2022
- Author(s)
  Zule Xu, Naoki Ojima, Shuowei Li and Tetsuya Iizuka
- Organizer
  IEEE International Symposium on Circuits and Systems (ISCAS)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-21H03406
[Presentation] An Inductorless Fractional-N PLL Using Harmonic-Mixer-Based Dual Feedback and High-OSR Delta-Sigma-Modulator with Phase-Domain Filtering2022
- Author(s)
  Masaru Osada, Zule Xu and Tetsuya Iizuka
- Organizer
  IEEE European Solid-State Circuits Conference (ESSCIRC)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-21H03406
[Presentation] A Charge-Redistribution Multi-Bit Stochastic-Resonance ADC Enhancing SNDR for Weak Input Signal2022
- Author(s)
  Ryoya Shibata, Zule Xu, Yasushi Hotta, Hitoshi Tabata and Tetsuya Iizuka
- Organizer
  IEEE International Symposium on Circuits and Systems (ISCAS)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-21H03406
[Presentation] 140-GHz Energy-Efficient OOK Receiver using Self-Mixer-Based Power Detector in 65nm CMOS2022
- Author(s)
  Nguyen Ngoc Mai-Khanh, Daisuke Yamazaki and Tetsuya Iizuka
- Organizer
  IEEE International Conference on IC Design and Technology (ICICDT)
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-21H03406
[Presentation] Does AI make analog automation different?2022
- Author(s)
  Tetsuya Iizuka and Nobukazu Takai
- Organizer
  IEEE Asian Solid-State Circuits Conference (A-SSCC) Panel Discussion
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-21H03406
[Presentation] A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving －63-dBc Reference Spur, 175-fs RMS Jitter and －240-dB FOMjitter2022
- Author(s)
  Zunsong Yang, Zule Xu, Masaru Osada and Tetsuya Iizuka
- Organizer
  IEEE Symposium on VLSI Technology and Circuits Digest of Technical Papers
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-21H03406
[Presentation] CMOS A/D 変換回路のシステマティック設計手法2022
- Author(s)
  飯塚哲也, Hao Xu, Asad Abidi
- Organizer
  電子情報通信学会総合大会
- Invited
- Data Source
  KAKENHI-PROJECT-21H03406
[Presentation] ソフトウェア無線のための広帯域受信機向け集積回路技術2022
- Author(s)
  飯塚哲也
- Organizer
  電子情報通信学会ソサイエティ大会
- Invited
- Data Source
  KAKENHI-PROJECT-21H03406
[Presentation] 帯域内位相雑音の低減に向けた3次MASH型ΔΣFDCに基づくデジタル位相同期回路の設計2022
- Author(s)
  岩下僚我, 徐祖楽, 長田将, 柴田凌弥, 熊野陽, 飯塚哲也
- Organizer
  電子情報通信学会技術研究報告
- Data Source
  KAKENHI-PROJECT-21H03406
[Presentation] A Tutorial on Systematic Design of CMOS A/D Converters: Illustrated by a 10 b, 500 MS/s SAR ADC with 2 GHz RBW2021
- Author(s)
  Tetsuya Iizuka, Hao Xu and Asad A. Abidi
- Organizer
  IEEE European Solid-State Circuits Conference (ESSCIRC)
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-21H03406
[Presentation] A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur2021
- Author(s)
  Zule Xu, Masaru Osada and Tetsuya Iizuka,
- Organizer
  IEEE Symposium on VLSI Circuits
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-21H03406
[Presentation] 低位相雑音かつ低スプリアストーンを達成する高調波ミキサを用いた二重フィードバック型フラクショナルN位相同期回路2021
- Author(s)
  長田将, 徐祖楽, 飯塚哲也
- Organizer
  電子情報通信学会総合大会
- Data Source
  KAKENHI-PROJECT-17H03244
[Presentation] Shock-Wave Transceiver Integration for mm-Wave Active Sensing Applications2021
- Author(s)
  Nguyen Ngoc Mai-Khanh, Tetsuya Iizuka and Kunihiro Asada
- Organizer
  IEEE International Conference on IC Design and Technology (ICICDT)
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-21H03406
[Presentation] Analysis of Strong-ARM Comparator with Offset Calibration Using Auxiliary Pair2021
- Author(s)
  Shuowei Li, Zule Xu, Tetsuya Iizuka
- Organizer
  電子情報通信学会総合大会
- Data Source
  KAKENHI-PROJECT-17H03244
[Presentation] Nyquist A/D Converter Design in Four Days2021
- Author(s)
  Tetsuya Iizuka, Hao Xu and Asad A. Abidi
- Organizer
  IEEE Symposium on VLSI Circuits
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-21H03406
[Presentation] A 3.2-to-3.8GHz Calibration-Free Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving -66dBc Worst-Case In-Band Fractional Spur2020
- Author(s)
  Masaru Osada, Zule Xu and Tetsuya Iizuka
- Organizer
  IEEE Symposium on VLSI Circuits
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H03244
[Presentation] A 140-GHz 14-dBm Power Amplifier using Power Combiner based on Symmetric Balun in 65-nm Bulk CMOS2020
- Author(s)
  Daisuke Yamazaki, Takamichi Horikawa and Tetsuya Iizuka
- Organizer
  IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H03244
[Presentation] スイッチ型および増幅型ステージを用いた高アイソレーションかつ低損失なDバンドOOK変調器の実装2019
- Author(s)
  山﨑大輔, 大槻宜孝, 原崇文, Nguyen Ngoc Mai-Khanh, 飯塚哲也
- Organizer
  電子情報通信学会 LSIとシステムのワークショップ2019
- Data Source
  KAKENHI-PROJECT-17H03244
[Presentation] A 0.0053-mm2 6-Bit Fully-Standard-Cell-Based Synthesizable SAR ADC in 65nm CMOS2019
- Author(s)
  Naoki Ojima, Zule Xu and Tetsuya Iizuka
- Organizer
  IEEE International New Circuits and Systems Conference (NEWCAS)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H03244
[Presentation] A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion2018
- Author(s)
  Naoki Ojima, Toru Nakura, Tetsuya Iizuka, and Kunihiro Asada
- Organizer
  26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H03244
[Presentation] 周波数2逓倍器を用いた小面積かつ低電力な140GHz電圧制御発振器の設計2018
- Author(s)
  大槻宜孝, 山﨑大輔, マイカーングエンコック, 飯塚哲也
- Organizer
  電子情報通信学会集積回路研究会（ICD）
- Data Source
  KAKENHI-PROJECT-17H03244
[Presentation] Time-Domain Approach for Analog Circuits: Fine-Resolution TDC and Quick-Start CDR Circuits2018
- Author(s)
  Tetsuya Iizuka and Kunihiro Asada
- Organizer
  IEEE International Conference on Advanced Technologies for Communications (ATC)
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H03244
[Presentation] Resonant Power Supply Noise Reduction Using a Triangular Active Charge Injection2016
- Author(s)
  Masahiro Kano, Toru Nakura, Tetsuya Iizuka, and Kunihiro Asada
- Organizer
  IEEE International Conference on Electronics, Circuits and Systems (ICECS)
- Place of Presentation
  モンテカルロ市(モナコ公国)
- Year and Date
  2016-12-11
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26820125
[Presentation] A Fine-Resolution Pulse-Shrinking Time-to-Digital Converter with Completion Detection Utilizing Built-in Offset Pulse2016
- Author(s)
  Tetsuya Iizuka, Takehisa Koga, Toru Nakura and Kunihiro Asada
- Organizer
  IEEE Asian Solid-State Circuits Conference (A-SSCC)
- Place of Presentation
  富山国際会議場(富山県富山市)
- Year and Date
  2016-11-07
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26820125
[Presentation] 高分解能パルス縮小型時間-デジタル変換器の設計2015
- Author(s)
  古賀丈尚, 飯塚哲也, 名倉徹, 浅田邦博
- Organizer
  電子情報通信学会技術研究報告
- Place of Presentation
  作並温泉一の坊(宮城県仙台市)
- Year and Date
  2015-10-26
- Data Source
  KAKENHI-PROJECT-26820125
[Presentation] A Calibration-Free Time Difference Accumulator Using Two Pulses Propagating on a Single Buffer Ring2015
- Author(s)
  Tomohiko Yano, Toru Nakura, Tetsuya Iizuka and Kunihiro Asada
- Organizer
  IEEE Asian Solid-State Circuits Conference (A-SSCC)
- Place of Presentation
  厦門市(中国)
- Year and Date
  2015-11-09
- Data Source
  KAKENHI-PROJECT-26820125
[Presentation] バッファリングを利用した出力ドリフト補正が不要な時間領域アナログ信号積分器2015
- Author(s)
  矢野智比古, 名倉徹, 飯塚哲也, 浅田邦博
- Organizer
  電子情報通信学会技術研究報告
- Place of Presentation
  京都工芸繊維大学(京都府京都市)
- Year and Date
  2015-12-17
- Data Source
  KAKENHI-PROJECT-26820125
[Presentation] LSIセキュリティ対策のための集積回路の表面磁界分布からの動作状態推定2013
- Author(s)
  中村陽二, 飯塚哲也, 浅田邦博
- Organizer
  情報処理学会 DAシンポジウム2013
- Place of Presentation
  岐阜県下呂市幸田
- Data Source
  KAKENHI-PROJECT-24700042
[Presentation] An All-Digital Time Difference Hold-and-Replication Circuit utilizing a Dual Pulse Ring Oscillator2013
- Author(s)
  Tetsuya Iizuka, Teruki Someya, Toru Nakura, and Kunihiro Asada
- Organizer
  IEEE Custom Integrated Circuits Conference (CICC)
- Place of Presentation
  米国カリフォルニア州サンノゼ
- Data Source
  KAKENHI-PROJECT-24700042
[Presentation] 制御信号の周期内切替によるデジタル制御発振器の高解像度化2012
- Author(s)
  児玉和俊, 飯塚哲也, 名倉徹, 浅田邦博
- Organizer
  電子情報通信学会 LSIとシステムのワークショップ
- Place of Presentation
  福岡県北九州市小倉
- Data Source
  KAKENHI-PROJECT-24700042
[Presentation] Spacial Resolution Enhancement for Integrated Magnetic Probe by Two-Step Removal of Si-Substrate Beneath the Coil
- Author(s)
  Nguyen Ngoc Mai-Khanh, Tetsuya Iizuka, Shigeru Nakajima, and Kunihiro Asada
- Organizer
  IEEE 10th European Conference on Magnetic Sensors and Actuators (EMSA)
- Place of Presentation
  オーストリアウィーン
- Year and Date
  2014-06-06 – 2014-06-09
- Data Source
  KAKENHI-PROJECT-24700042
[Presentation] NBTI の周波数依存性を利用した劣化過渡解析の高速化手法
- Author(s)
  森一倫, 名倉徹, 飯塚哲也, 浅田邦博
- Organizer
  電子情報通信学会総合大会論文集
- Place of Presentation
  滋賀
- Year and Date
  2015-03-10 – 2015-03-13
- Data Source
  KAKENHI-PROJECT-24700042
[Presentation] 論理シミュレーションにもとづいたNBTI劣化過渡解析の高速化手法
- Author(s)
  森一倫, 名倉徹, 飯塚哲也, 浅田邦博
- Organizer
  電子情報通信学会研究報告会集積回路研究会
- Place of Presentation
  東京
- Year and Date
  2014-12-01 – 2014-12-02
- Data Source
  KAKENHI-PROJECT-24700042

1. 井上公 (00356502)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
2. 井上悠 (90843342)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
3. 矢嶋赳彬 (10644346)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
4. 堀田育志 (30418652)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
5. 藤原寛太郎 (00557704)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
6. 田中剛平 (90444075)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
7. NGUYEN Ngoc Mai-Khanh

# of Collaborated Projects: 1 results

# of Collaborated Products: 2 results
8. 徐祖楽

# of Collaborated Projects: 0 results

# of Collaborated Products: 4 results

IIZUKA Tetsuya 飯塚 哲也

Research Projects

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Co-Researchers

Innovative Edge AI: Building the Science of Information Processing for Long-Timescale Human Interaction

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大規模AIシステムを想定した誘電体導波路によるチップ間通信技術基盤の確立Principal Investigator

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High-Speed and Reliable Wireline Communication System based on Plastic WaveguidePrincipal Investigator

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A Fine-Resolution and Wide-Range Time-to-Digital Converter for Time-of-Flight Measurement EquipmentsPrincipal Investigator

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Chip Identification System based on Physically Unclonable Function Utilizing Aging Effect on Nano-Scale TransistorsPrincipal Investigator

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[Journal Article] Analysis and simulation of MOSFET-based gate-voltage-independent capacitor2022

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[Journal Article] A fractional-N MASH2-k FDC phase-locked loop architecture enabling higher-order quantisation noise shaping2022

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[Journal Article] Analysis of Offset Spurs in Phase-Locked-Loops Employing Harmonic-Mixer-Based Feedback With Sample-and-Hold Operation2022

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[Journal Article] Analysis of strong-arm comparator with auxiliary pair for offset calibration2022

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[Journal Article] 4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop2022

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[Journal Article] Integrated On-Silicon and On-glass Antennas for Mm-Wave Applications2021

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[Journal Article] An All-Standard-Cell-Based Synthesizable SAR ADC with Nonlinearity-Compensated RDAC2021

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[Journal Article] A 3.2-to-3.8 GHz Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving -65 dBc In-Band Fractional Spur2020

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[Journal Article] 11?Gb/s 140?GHz OOK modulator with 24.6?dB isolation utilising cascaded switch and amplifier‐based stages in 65?nm bulk CMOS2020

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IIZUKA Tetsuya 飯塚哲也