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SHINJI Kimura  木村 晋二

ORCIDConnect your ORCID iD *help
… Alternative Names

木村 晋二  キムラ シンジ

KIMURA Shinji  木村 晋二

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Researcher Number 20183303
Other IDs
External Links
Affiliation (Current) 2020: 早稲田大学, 理工学術院(情報生産システム研究科・センター), 教授
Affiliation (based on the past Project Information) *help 2018 – 2020: 早稲田大学, 理工学術院(情報生産システム研究科・センター), 教授
2010 – 2015: 早稲田大学, 理工学術院, 教授
2007: Waseda University, 大学情報生産システム研究科, 教授
2007: Waseda University, Graduate School of Information, Production, and Systems, Professor
2006: 早稲田大学, 大学院情報生産システム研究科, 教授 … More
2003 – 2005: 早稲田大学, 大学院・情報生産システム研究科, 教授
2004: Waseda University, Graduate School of Information, Production and Systems, Professor, 情報生産システム研究科, 教授
2002: 早稲田大学, 情報生産システム研究科開設準備室, 教授
1993 – 2001: 奈良先端科学技術大学院大学, 情報科学研究科, 助教授
1988 – 1992: 神戸大学, 工学部, 助手
1986: Assistant, Faculty of Engineering, Kobe University, 工学部, 助手 Less
Review Section/Research Field
Principal Investigator
計算機科学 / Computer system/Network / Basic Section 60040:Computer system-related
Except Principal Investigator
計測・制御工学 / Computer system/Network / 計算機科学 / Computer system / Basic Section 60040:Computer system-related
Keywords
Principal Investigator
二分決定グラフ / 形式的検証 / BDD / 高位検証 / 無評価関数 / 順序回路の検証 / 暗黙状態数え挙げ / 並列二分決定グラフ処理 / Shannon展開法 / パイプライン処理 … More / 暗黙状態数え上げ / 並列論理設計検証 / パイプライン検証 / 論理設計検証 / 剰余BDD / 論理合成 / 論理最適化 / ハードウェア記述言語 / 並列トランスダクション / 高位設計検証 / Cベースハードウェア設計 / 再構成可能ハードウェアの検証 / 演算回路の検証手法 / 等価検証 / 無評価関数を用いた検証 / 設計検証 / 再構成可能素子の検証 / テクノロジーマッピング検証 / 映像処理向け検証 / 再構成可能アーキテクチャ検証 / マルチメディア処理向け検証 / Cプログラム検証 / High-level Design Verification / C based Hardware Design / Reconfigurable Hardware / Verification of Arithmetic Circuits / Equivalence Verification / Uninterpreted Function / 等価論理 / ハードウェアの等価検証 / 項書き換え / equivalence logic / equivalence hardware verification / uninterpreted function / term rewriting system / high level verification / データ表現形式 / 共有指数表現 / データ表現と誤差解析 / データ圧縮 / 再構成可能アーキテクチャ / データ表現と精度保証 … More
Except Principal Investigator
高位合成 / ハードウェア / ソフトウェア協調設計 / 細胞プログラミング / Pocエディタ / 汎用コプロセッサ / LSI抽象モデル / 論理合成 / High Level Synthesis / OBDD / 超並列アルゴリズム / データ構造 / 多重階層メッシュネットワーク / RDTネットワーク / 局所計算可能性 / 二分決定グラフ / 発展的ソフトウェア構成法 / パターン細胞 / 前条件・後条件 / 手指動作記述文 / 発展するソフトウェア構成法 / 能動形計算モデル / 能動関数 / 動的結合機構 / 再構成可能プロセッサ / LSI設計 / LSI実装 / LSIアーキテクチャ / コンピュータ自動設計 / ハードウエア設計 / 設計自動化 / 電子デバイス・集積化回路 / 回路設計・CAD / アルゴリズム / ハードウェア設計 / VLSI 設計技術 / 物理合成 / 微細加工技術 / 統合化合成技術 / 低エネルギー / 低消費電力 / 統合化アルゴリズム / マルチDSP / デジタル制御 / 最短スループット / 検証 / スケジューリング / 並列処理 / ディジタル信号処理プロセッサ / ディジタル制御 / タイミング / スル-プット / Multiple DSP's / Digital Control / Minimum Throughput / Verification / Scheduling / Parallel Processing / ソフトウェアコデザイン / ソフトウェア協調動作 / 再構成可能システム / ハードウェアアクセラレータ / FPGA / Cコンパイラ / 汎用コブロセッサ / ハードウェア記述言語 / 並列化コンパイラ / コデザイン / エミュレーション / コプロセッサ / Hardware / Software Codesign / Software Co-operation / Reconfigurable System / Hardware Accelerator / Field Programmable Gate Array (FPGA) / General Purpose Co-processor / C compiler / 環境適応 / 再構成可能性 / 動的変更機構 / タイミング検証 / アクティブソフトウェア / 量子アルゴリズム / 環境適用 / 能動形プログラム / 知識ベース / ハードウェアのタイミング検証 / 量子計算 / Environmental Adaptability / Re-configurability / Dynamical Re-construction / Timing Verification / Quantum Computing / 計算機援用設計(CAD) / シミュレータ / グラフィックス / マイクロプロセッサ / 感度解析手法 / 最適精密制御則 / ベクトル制御 / Computer Aided Design / Simulator / Graphics / Microprocessor / Sensitivity Analysis / Optimal Precise Control Law / 集合の演算 / 不確かさ / ロバスト制御 / 計算幾何学 / CAD / ロバスト安定 / 凸包問題 / 制御系のCAD / OPERATION ON SETS / UNCERTAINTY / ROBUST CONTROL / COMPUTATIONAL GEOMETRY / COMPUTER AIDED DESIGN / ROBUST STABILITY / ハードウェアトロイ / 機械学習 / ゲートレベル / ネットリスト / 識別器最適化 / レジスタトランスファレベル Less
  • Research Projects

    (19 results)
  • Research Products

    (93 results)
  • Co-Researchers

    (11 People)
  •  Hardware-Trojan Detection for Integrated Circuit Design Data based on Machine LearningOngoing

    • Principal Investigator
      戸川 望
    • Project Period (FY)
      2019 – 2021
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Review Section
      Basic Section 60040:Computer system-related
    • Research Institution
      Waseda University
  •  再構成アクセラレータにおけるデータ形式最適化と精度保証Principal InvestigatorOngoing

    • Principal Investigator
      木村 晋二
    • Project Period (FY)
      2018 – 2020
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Review Section
      Basic Section 60040:Computer system-related
    • Research Institution
      Waseda University
  •  Abstract LSI model and Its Associated Low-energy Integrated LSI Design Methodology

    • Principal Investigator
      Togawa Nozomu
    • Project Period (FY)
      2013 – 2015
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      Computer system
    • Research Institution
      Waseda University
  •  Abstract LSI Model and Its Associated High-Level Synthesis Algorithm for Deep Submicron Technologies

    • Principal Investigator
      TOGAWA Nozomu
    • Project Period (FY)
      2010 – 2012
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      Computer system/Network
    • Research Institution
      Waseda University
  •  Research on design and implementation of Ultra Large scale LSI

    • Principal Investigator
      GOTO Satoshi
    • Project Period (FY)
      2008 – 2010
    • Research Category
      Grant-in-Aid for Scientific Research (A)
    • Research Field
      Computer system/Network
    • Research Institution
      Waseda University
  •  High-level Hardware Verification Based on Equivalence Logic with SimilaritiesPrincipal Investigator

    • Principal Investigator
      KIMURA Shinji
    • Project Period (FY)
      2005 – 2007
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Research Field
      Computer system/Network
    • Research Institution
      Waseda University
  •  Hardware Verification with respect to Program SpecificationPrincipal Investigator

    • Principal Investigator
      KIMURA Shinji
    • Project Period (FY)
      2002 – 2004
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Research Field
      計算機科学
    • Research Institution
      Waseda University
  •  Implementation of Adaptable Hardware and Software for Changing Environment

    • Principal Investigator
      WATANABE Katsumasa
    • Project Period (FY)
      1999 – 2001
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      計算機科学
    • Research Institution
      NARA INSTITUTE OF SCIENCE AND TECHNOLOGY
  •  コンテンフに適応する発展的ソフトウェアの構成法

    • Principal Investigator
      WATANABE Katsumasa
    • Project Period (FY)
      1997
    • Research Category
      Grant-in-Aid for Scientific Research on Priority Areas
    • Research Institution
      Nara Institute of Science and Technology
  •  コンテンツに適応する発展的ソフトウェアの構成法

    • Principal Investigator
      渡邉 勝正
    • Project Period (FY)
      1997 – 1998
    • Research Category
      Grant-in-Aid for Scientific Research on Priority Areas (A)
    • Research Institution
      Nara Institute of Science and Technology
  •  論理回路の合成手法および最適化手法の高速化に関する研究Principal Investigator

    • Principal Investigator
      木村 晋二
    • Project Period (FY)
      1996
    • Research Category
      Grant-in-Aid for Encouragement of Young Scientists (A)
    • Research Field
      計算機科学
    • Research Institution
      Nara Institute of Science and Technology
  •  論理回路の縮約モデルの自動抽出とそれを用いた大規模論理回路の設計検証に関する研究Principal Investigator

    • Principal Investigator
      木村 晋二
    • Project Period (FY)
      1995
    • Research Category
      Grant-in-Aid for Encouragement of Young Scientists (A)
    • Research Field
      計算機科学
    • Research Institution
      Nara Institute of Science and Technology
  •  Research on Reconfigurable General Purpose Co-processor Systems and Their Optimized Hardware/Software Codesign Compiler

    • Principal Investigator
      WATANABE Katsumasa
    • Project Period (FY)
      1995 – 1997
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      計算機科学
    • Research Institution
      Nara Institute of Science and Technology
  •  パイプライン処理の形式的並列設計検証手法に関する研究Principal Investigator

    • Principal Investigator
      木村 晋二
    • Project Period (FY)
      1994
    • Research Category
      Grant-in-Aid for Encouragement of Young Scientists (A)
    • Research Field
      計算機科学
    • Research Institution
      Nara Institute of Science and Technology
  •  超並列アルゴリズム設計のためのデータ構造と計算モデルに関する研究

    • Principal Investigator
      安浦 寛人
    • Project Period (FY)
      1993
    • Research Category
      Grant-in-Aid for Scientific Research on Priority Areas
    • Research Institution
      Kyushu University
  •  順序機械の設計検証のための暗黙状態数え上げの並列化に関する研究Principal Investigator

    • Principal Investigator
      木村 晋二
    • Project Period (FY)
      1993
    • Research Category
      Grant-in-Aid for Encouragement of Young Scientists (A)
    • Research Field
      計算機科学
    • Research Institution
      Nara Institute of Science and Technology
  •  Studies on Digital-Controller Configuration Design and Its Synchronization Control Using Multiple Digital Signal Processors.

    • Principal Investigator
      HANEDA Hiromasa
    • Project Period (FY)
      1990 – 1992
    • Research Category
      Grant-in-Aid for General Scientific Research (C)
    • Research Field
      計測・制御工学
    • Research Institution
      Kobe University
  •  OPERATION ON SETS AND IT'S APPLICATIONS TO COMPUTER AIDED DESIGN OF ROBUST CONTROL SYSTEMS

    • Principal Investigator
      OHTA Yuzo
    • Project Period (FY)
      1988 – 1989
    • Research Category
      Grant-in-Aid for General Scientific Research (C)
    • Research Field
      計測・制御工学
    • Research Institution
      KOBE UNIVERSITY
  •  Studies on Computer-Aided Design of Microprocessor Controlled Precise AC Servo Systems.

    • Principal Investigator
      HANEDA Hiromasa
    • Project Period (FY)
      1984 – 1986
    • Research Category
      Grant-in-Aid for General Scientific Research (B)
    • Research Field
      計測・制御工学
    • Research Institution
      Kobe University

All 2020 2019 2018 2016 2015 2011 2010 2008 2007 2006 2005 2004 2003 2002 Other

All Journal Article Presentation Book

  • [Book] システムLSI設計技術、4章「ハードウェア設計技術」(木村晋二担当)2006

    • Author(s)
      藤田昌宏編著(藤田昌宏, 木村晋二他)
    • Total Pages
      50
    • Publisher
      オーム社
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Journal Article] Design of Low-Cost Approximate Multipliers Based on Probability-Driven Inexact Compressors2019

    • Author(s)
      GUO Yi、SUN Heming、LEI Ping、KIMURA Shinji
    • Journal Title

      IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

      Volume: E102.A Issue: 12 Pages: 1781-1791

    • DOI

      10.1587/transfun.e102.a.1781

      10.1587/transfun.E102.A.1781

    • ISSN
      0916-8508, 1745-1337
    • Language
      English
    • Peer Reviewed / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18H03217
  • [Journal Article] Lossy Compression for Embedded Computer Vision Systems2018

    • Author(s)
      Li Guo, Dajiang Zhou, Jinjia Zhou, Shinji Kimura, and Satoshi Goto
    • Journal Title

      IEEE Access

      Volume: 6 Pages: 39385-39397

    • DOI

      10.1109/access.2018.2852809

    • Peer Reviewed / Open Access / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18H03217, KAKENHI-PROJECT-17J10477
  • [Journal Article] ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory2015

    • Author(s)
      Masashi Tawada, Shinji Kimura, Masao Yanagisawa, and Nozomu Togawa
    • Journal Title

      IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

      Volume: E98-A Issue: 12 Pages: 2494-2504

    • DOI

      10.1587/transfun.e98.a.2494

      10.1587/transfun.E98.A.2494

    • NAID

      130005111993

    • ISSN
      0916-8508, 1745-1337
    • Language
      English
    • Peer Reviewed / Acknowledgement Compliant
    • Data Source
      KAKENHI-PROJECT-25280017
  • [Journal Article] Multi-Operand Adder Synthesis Targeting FPGAs2011

    • Author(s)
      Taeko Matsunaga, Shinji Kimura, and Yusuke Matsunaga
    • Journal Title

      IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

      Volume: vol. E94-A, no. 12 Issue: 12 Pages: 2579-2586

    • DOI

      10.1587/transfun.e94.a.2579

      10.1587/transfun.E94.A.2579

    • NAID

      10030533680

    • ISSN
      0916-8508, 1745-1337
    • Language
      English
    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22300019
  • [Journal Article] Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating2010

    • Author(s)
      Xin Man, Takashi Horiyama, and Shinji Kimura
    • Journal Title

      IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

      Volume: vol. E93-A, no. 12 Issue: 12 Pages: 2472-2480

    • DOI

      10.1587/transfun.e93.a.2472

      10.1587/transfun.E93.A.2472

    • NAID

      10027985671

    • ISSN
      0916-8508, 1745-1337
    • Language
      English
    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22300019
  • [Journal Article] Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating2010

    • Author(s)
      Xin Man, Takashi Horiyama, Shinji Kimura
    • Journal Title

      IEICE Trans.On Fundamentals

      Volume: E93-A Pages: 2472-2480

    • NAID

      10027985671

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22300019
  • [Journal Article] メデイア処理における超低消費電力SoC技術2010

    • Author(s)
      後藤敏、池永剛、吉村猛、木村晋二、戸川望
    • Journal Title

      情報処理 Vo.51,No.7

      Pages: 837-845

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-20240004
  • [Journal Article] メディア処理における超低消費電力SoC技術2010

    • Author(s)
      後藤敏、池永剛、吉村猛、木村晋二、戸川望
    • Journal Title

      情報処理

      Volume: Vo.51, No.7 Pages: 837-845

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-20240004
  • [Journal Article] Issue Mechanism for Embeded Simultaneous Multithreading Processor2008

    • Author(s)
      C. Zang, S. Imai, S. Frank, S. Kimura
    • Journal Title

      IEICE Trans. Fundamentals E91-A

      Pages: 1092-1100

    • NAID

      10026848682

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Journal Article] The Optimal Architecture Design of Two-Dimensional Matrix Multiolication Jumping Systolic Array2008

    • Author(s)
      Y. Yang, S. Kimura
    • Journal Title

      IEICE Trans. Fundamentals E91-A

      Pages: 1101-1111

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Journal Article] The Optimal Architecture Design of Two-Dimensional Matrix Multiplication Jumping Systolic Array2008

    • Author(s)
      Y.Yang, S.Kimura
    • Journal Title

      IEICE Trans.Fundamentals E91-A

      Pages: 1101-1111

    • Description
      「研究成果報告書概要(和文)」より
    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Journal Article] Issue Mechanism for Embeded Simultaneous Multithreading Processor2008

    • Author(s)
      C.Zang, S.Imai, S.Frank, S.Kimura
    • Journal Title

      IEICE Trans.Fundamentals E91-A

      Pages: 1092-1100

    • NAID

      10026848682

    • Description
      「研究成果報告書概要(和文)」より
    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Journal Article] Resynthesis Method for Circuit Acceleration on LUT-based FPGA2007

    • Author(s)
      Weijie Xing, Takashi Horiyama, Shinji Kimura, et. al.
    • Journal Title

      Integration of Mixed Infor\mation technologies (SASIMI2007)

      Pages: 375-380

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Journal Article] Active Mode Leakage Power Reduction Based on the Controlling Value of Logic Gates2007

    • Author(s)
      Lei Chen, Shinji Kimura
    • Journal Title

      Proceedings of 14th Workshop on Synthesis And System Integration of Mixed Information technologies

      Pages: 266-271

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Journal Article] Power-Conscious Synthesis of Parallel Prefix Adders under Bitwise Timing Const\ raints2007

    • Author(s)
      Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
    • Journal Title

      Proceedings of 14th Workshop on Synthesis And System Integration of Mixed Infor\mation technologies

      Pages: 7-14

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Journal Article] Issue Mechanism for Embedded Simultaneous Multithreading Processor2007

    • Author(s)
      Chengjie Zang, Shigeki Imai, and Shinji Kimura
    • Journal Title

      Proceedings of The 20th Workshop on Circuits and Systems in Karuizawa

      Pages: 325-330

    • NAID

      10026848682

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Journal Article] 回路変更を用いたプロトタイプ設計検証の高速化手法2007

    • Author(s)
      井上敬太, シン唯頡, 木村晋二
    • Journal Title

      情報処理学会研究報告 SLDM129/4

      Pages: 113-118

    • Data Source
      KAKENHI-PROJECT-17500047
  • [Journal Article] Selective Low-Care Coding : A Means for Test Date Compression in Circuits with Multiple Scan Chains2006

    • Author(s)
      Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
    • Journal Title

      IEICE Trans. Fundamentals E91-A

      Pages: 996-1004

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Journal Article] 高位検証における等価論理式への変換手法について2006

    • Author(s)
      鄭 光フン, 木村晋二
    • Journal Title

      電子情報通信学会技術研究報告 March

      Pages: 1-6

    • NAID

      110004680260

    • Data Source
      KAKENHI-PROJECT-17500047
  • [Journal Article] An Efficient Instruction Issue Mechanism for Simultaneous Multithreading Microprocessor2006

    • Author(s)
      Taeseok Jeong, Chengjie Zang, Shinji Kimura
    • Journal Title

      Proc. International SoC Design Conference

      Pages: 351-354

    • Data Source
      KAKENHI-PROJECT-17500047
  • [Journal Article] Selective Low-Care Coding:A Means for Test Data Compression in Circuits with Multiple Scan Chains2006

    • Author(s)
      Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
    • Journal Title

      IEICE Trans.Fundamentals E91-A

      Pages: 996-1004

    • Description
      「研究成果報告書概要(和文)」より
    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Journal Article] Bit-Length Optimization Method for High-Level Synthesis based on Non-Linear Programming Technique2006

    • Author(s)
      Nobuhiro DOI, Takashi HORIYAMA, Masaki NAKANISHI, and Shinji KIMURA
    • Journal Title

      IEICE Trans.Fundamentals E89-A

      Pages: 3427-3434

    • NAID

      110007537844

    • Description
      「研究成果報告書概要(和文)」より
    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Journal Article] Coverage Estimation Using Transition Perturbatio for Symbolic Model Checking in Hardware Verification2006

    • Author(s)
      Xingwen XU, Shinji KIMURA, kazunari Horikawa, Takehiko TSUCHIYA
    • Journal Title

      IEICE Trans. Fundamentals E89-A

      Pages: 3451-3457

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Journal Article] Performance and Energy Efficient Data Cache Architecture for Embedded Simultaneous Multithreading Microprocessor2006

    • Author(s)
      Chengjie Zang, Shigeki Imai, Shinji Kimura
    • Journal Title

      Proceedings of 13th Workshop on Synthesis And System Integration of Mixed Information technologies

      Pages: 268-273

    • Data Source
      KAKENHI-PROJECT-17500047
  • [Journal Article] Coverage Estimation Using Transition Perturbation for Symbolic Model Checking in Hardware Verification2006

    • Author(s)
      Xingwen XU, Shinji KIMURA, Kazunari HORIKAWA, and Takehiko TSUCHIYA
    • Journal Title

      IEICE Trans.Fundamentals E89-A

      Pages: 3451-3457

    • NAID

      110007537847

    • Description
      「研究成果報告書概要(和文)」より
    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Journal Article] Bit-Length Optimization Method for High-Level Synthesis based on Non-Linear Programming Technique2006

    • Author(s)
      Nobuhiro DOI, Takashi HORUYAMA, Masaki NAKANISHI, Shinji KIMURA
    • Journal Title

      IEICE Trans. Fundamentals E89-A

      Pages: 3427-3434

    • NAID

      110007537844

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Journal Article] Bit-Length optimization Method for High-Level Synthesis based on Non-Linear Programming Technique2006

    • Author(s)
      Masaki NAKANISHI, SHinji Kimura
    • Journal Title

      IEICE Trans. Fundamentals E89-A, No.12

      Pages: 3427-3434

    • NAID

      110007537844

    • Data Source
      KAKENHI-PROJECT-17500047
  • [Journal Article] Transition-Based Coverage Estimation for Symbolic Model Checking2006

    • Author(s)
      Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya.
    • Journal Title

      Proceeding of ASP-DAC2006 Jan.

      Pages: 1-6

    • Data Source
      KAKENHI-PROJECT-17500047
  • [Journal Article] 浮動小数点演算と演算チェイニングを考慮した粗粒度再構成可能ハードウェア2005

    • Author(s)
      阿久津日出実, 木村晋二
    • Journal Title

      電信情報通信学会技術研究報告 March

      Pages: 1-6

    • NAID

      110004680268

    • Data Source
      KAKENHI-PROJECT-17500047
  • [Journal Article] 非線形計画法と整数解の探索に基づく高位合成向けビット長最適化2005

    • Author(s)
      土井伸洋, 堀山貴志, 中西正樹, 木村晋二
    • Journal Title

      情報処理学会システムLSI設計技術研究会報告

      Pages: 1-6

    • Data Source
      KAKENHI-PROJECT-14580377
  • [Journal Article] Transition Traversal Coverage Estimation for Symbolic Model Checking2005

    • Author(s)
      Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya
    • Journal Title

      Proceeding of the 6th International Conference on ASIC Oct.

      Pages: 850-853

    • Data Source
      KAKENHI-PROJECT-17500047
  • [Journal Article] ビット長に制約がある場合の実数演算の固定小数点演算化2005

    • Author(s)
      土井伸洋, 堀山貴史, 中西正樹, 木村晋二
    • Journal Title

      DAシンポジウム2005論文集 July

      Pages: 49-54

    • Data Source
      KAKENHI-PROJECT-17500047
  • [Journal Article] Duplicated Register File Design for Embedded Simultaneous Multithreading Microprocessor2005

    • Author(s)
      Chengjie Zang, Shigeki Imai, Shinji Kimura
    • Journal Title

      Proceedings of International Conference on ASIC Oct.

      Pages: 160-163

    • Data Source
      KAKENHI-PROJECT-17500047
  • [Journal Article] Structural Coverage of Traversed Transitions for Symbolic Model Checking2005

    • Author(s)
      Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya
    • Journal Title

      IEICE Technical Report(デザインガイア2005) Vol.105, No.443, Nov.

      Pages: 65-70

    • NAID

      110003479962

    • Data Source
      KAKENHI-PROJECT-17500047
  • [Journal Article] A Hybrid Dictionary Test Data Compression for Multiscan-based Designs2004

    • Author(s)
      Y.Shi, S.Kimura, M.Yanagisawa, T.Ohtsuki
    • Journal Title

      IEICE Trans.Fundamentals E87-A, No.12

      Pages: 3193-3199

    • NAID

      110003212857

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-14580377
  • [Journal Article] A Hybrid Dictionary Test Data Compression for Multiscan-based Designs2004

    • Author(s)
      Y.Shi, S.Kimura, M.Yanagisawa, T.Ohtsuki
    • Journal Title

      IEICE Trans. Fundamentals E87-A, No.12

      Pages: 3193-3199

    • NAID

      110003212857

    • Data Source
      KAKENHI-PROJECT-14580377
  • [Journal Article] A Hybrid Dictionary Test Data Compression for Multiscan-based Designs2004

    • Author(s)
      Y.Shi, S.Kimura, M.Yanagisawa, T.Ohtsuki
    • Journal Title

      IEICE Trans.Fundamentals Vol.E87-A, No.12

      Pages: 3193-3199

    • NAID

      110003212857

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-14580377
  • [Journal Article] Reconfigurable Architecture for Bit-Level Data Processing2004

    • Author(s)
      S.Kimura
    • Journal Title

      Proceedings of 1st Silicon-Seabelt Workshop on VLSI Designs

      Pages: 1-6

    • Data Source
      KAKENHI-PROJECT-14580377
  • [Journal Article] 浮動小数点演算での誤差の増減を考慮した変数ビット長の最適化2004

    • Author(s)
      土井伸洋, 堀山貴史, 中西正樹, 木村晋二
    • Journal Title

      DAシンポジウム2004論文集

      Pages: 85-90

    • Data Source
      KAKENHI-PROJECT-14580377
  • [Journal Article] A Selective Scan Chain Reconfiguration through Run-Length Coding for Test Data Compression and Scan Power Reduction2004

    • Author(s)
      Y.Shi, S.Kimura, M.Yanagisawa, T.Ohtsuki
    • Journal Title

      IEICE Trans.Fundamentals E87-A, No.12

      Pages: 3208-3215

    • NAID

      110003212859

    • Data Source
      KAKENHI-PROJECT-14580377
  • [Journal Article] An Optimization Method in Floating-point to Fixed-point Conversion using Positive and Negative Error Analysis and Sharing of Operations2004

    • Author(s)
      N.Doi, T.Horiyama, M.Nakanishi, S.Kimura
    • Journal Title

      Proc.of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'2004)

      Pages: 466-471

    • Data Source
      KAKENHI-PROJECT-14580377
  • [Journal Article] A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation2003

    • Author(s)
      Y.Shi, Z.Zhang, S.Kimura, M.Yanagisawa, T.Ohtsuki
    • Journal Title

      IEICE Trans.Fundamentals E86-A, No.12

      Pages: 3056-3662

    • NAID

      110003212586

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-14580377
  • [Journal Article] Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High Level Synthesis2003

    • Author(s)
      N.Doi, T.Horiyama, N.Nakanishi, S.Kimura, K.Watanabe
    • Journal Title

      IEICE Trans.Fundamentals Vol.E86-A, No.12

      Pages: 3176-3183

    • NAID

      110003212600

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-14580377
  • [Journal Article] Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High Level Synthesis2003

    • Author(s)
      N.Doi, T.Horiyama, N.Nakanishi, S.Kimura, K.Watanabe
    • Journal Title

      IEICE Trans.Fundamentals E86-A, No.12

      Pages: 3176-3183

    • NAID

      110003212600

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-14580377
  • [Journal Article] An On-Chip High Speed Serial Communication Method Based on Independent Ring Oscillators2003

    • Author(s)
      S.Kimura, T.Hayakawa, T.Horiyama, M.Nakanishi, K.Watanabe
    • Journal Title

      Proc.of International Solid State Circuit Conference

      Pages: 390-391

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-14580377
  • [Journal Article] A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation2003

    • Author(s)
      Y.Shi, Z.Zhang, S.Kimura, M.Yanagisawa, T.Ohtsuki
    • Journal Title

      IEICE Trans.Fundamentals Vol.E86-A, No.12

      Pages: 3056-3662

    • NAID

      110003212586

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-14580377
  • [Journal Article] An On-Chip High Speed Serial Communication Method Based on Independent Ring Oscillators2003

    • Author(s)
      S.Kimura, T.Hayakawa, T.Horiyama, M.Nakanishi, K.Watanabe
    • Journal Title

      Proc.of International Solid State Circuit Conference 03 22.3

      Pages: 390-391

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-14580377
  • [Journal Article] Bit Length Optimization of Fractional Parts on Floating to Fixed Point Conversion for High-Level Synthesis2003

    • Author(s)
      N.Doi, T.Horiyama, M.Nakanishi, S.Kimura, K.Watanabe
    • Journal Title

      Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'2003)

      Pages: 129-136

    • NAID

      110003212600

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-14580377
  • [Journal Article] Look Up Table Compaction Based on Folding of Logic Functions2002

    • Author(s)
      S.Kimura, A.Ishii, T.Horiyama, M.Nakanishi, H.Kajihara, K.Watanabe
    • Journal Title

      IEICE Trans.Fundamentals Vol.E85-A, No.12

      Pages: 2701-2707

    • NAID

      110003212441

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-14580377
  • [Journal Article] Look Up Table Compaction Based on Folding of Logic Functions2002

    • Author(s)
      S.Kimura, A.Ishii, T.Horiyama, M.Nakanishi, H.Kajihara, K.Watanabe
    • Journal Title

      IEICE Trans.Fundamentals E85-A, No.12

      Pages: 2701-2707

    • NAID

      110003212441

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-14580377
  • [Journal Article] Folding of Logic Functions and Its Application to Look Up Table Compaction2002

    • Author(s)
      S.Kimura, T.Horiyama, M.Nakanishi, H.Kajihara
    • Journal Title

      Proc.on ICCAD 2002 (International Conference on Computer Aided Design)

      Pages: 694-697

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-14580377
  • [Presentation] Small-Area and Low-Power FPGA-Based Multipliers using Approximate Elementary Modules2020

    • Author(s)
      Guo Yi、Sun Heming、Kimura Shinji
    • Organizer
      Proc. of ASP-DAC 2020
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18H03217
  • [Presentation] Approximate Floating Point Multiplier based on Shifting Addition Using Carry Signal from Second-Highest-Bit2020

    • Author(s)
      Jie LI, Yi GUO, and Shinji KIMURA
    • Organizer
      IEICE Tech. Report, VLD2019-120
    • Data Source
      KAKENHI-PROJECT-18H03217
  • [Presentation] Low Cost Approximate Multiplier Design using Probability Driven Inexac t Compressors2018

    • Author(s)
      Yi Guo, Heming Sun, Li Guo, Shinji Kimura
    • Organizer
      APCCAS 2018
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18H03217
  • [Presentation] Embedded Frame Compression for Energy-Efficient Computer Vision Systems2018

    • Author(s)
      Li Guo, Dajiang Zhou, Jinjia Zhou, Shinji Kimura
    • Organizer
      ISCAS 2018
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18H03217
  • [Presentation] Sparseness Ratio Allocation and Neuron Re-pruning for Neural Networks Compression2018

    • Author(s)
      Li Guo, Dajiang Zhou, Jinjia Zhou, Shinji Kimura
    • Organizer
      ISCAS 2018
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18H03217
  • [Presentation] Energy-Efficient and High Performance Approximate Multiplier Using Compre ssors Based on Input Reordering2018

    • Author(s)
      Zhenhao Liu, Yi Guo, Xiaoting Sun and Shinji Kimura
    • Organizer
      TENCON 2018
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18H03217
  • [Presentation] A Radix-4 Partial Product Generation-Based Approximate Multiplier for High-Speed and Low-Power Digital Signal Processing2018

    • Author(s)
      Xiaoting Sun, Yi Guo, Zhenhao Liu, Shinji Kimura
    • Organizer
      ICECS 2018
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18H03217
  • [Presentation] 冗長符号化を用いたマルチレベルセル不揮発性メモリ書き込み量削減2016

    • Author(s)
      多和田雅師, 木村晋二, 柳澤政生, 戸川望
    • Organizer
      電子情報通信学会VLSI設計技術研究会
    • Place of Presentation
      横浜市
    • Year and Date
      2016-01-19
    • Data Source
      KAKENHI-PROJECT-25280017
  • [Presentation] 回路面積を考慮した不揮発性メモリ書き込み削減符号生成手法2015

    • Author(s)
      多和田雅師, 木村晋二, 柳澤政生, 戸川望
    • Organizer
      電子情報通信学会VLSI設計技術研究会
    • Place of Presentation
      長崎市
    • Year and Date
      2015-12-01
    • Data Source
      KAKENHI-PROJECT-25280017
  • [Presentation] Optimal planar jumping systolic array design for matrix multiplication2007

    • Author(s)
      Yun Yang and Shinji Kimura
    • Organizer
      The 20th Workshop on Circuits and Systems in Karuizawa(KARUIZAWA-2007)
    • Place of Presentation
      軽井沢
    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] 回路変更を用いたプロトタイプ設計検証の高速化手法"2007

    • Author(s)
      井上 敬太, シン 唯頡, 木村 晋二
    • Organizer
      情報処理学会研究報告(No. SLDM129/4, pp.113-118)
    • Place of Presentation
      広島
    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] Active Mode Leakage Power Reduction Based on the Controlling Value of Logic Gates2007

    • Author(s)
      Lei Chen, Shinji Kimura
    • Organizer
      Proc. of 14th Workshop on Synthesis And System Integration of Mixed Information technologies(SASIMI2007)
    • Place of Presentation
      札幌
    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] Power-Conscious Synthesis of Parallel Prefix Adders under Bitwise Timing Constraints2007

    • Author(s)
      Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
    • Organizer
      Proc. of 14th Workshop on Synthesis And System Integration of Mixed Information technologies(SASIMI2007)
    • Place of Presentation
      札幌
    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] Issue Mechanism for Embedded Simultaneous Multithreading Processor2007

    • Author(s)
      Chengjie Zang, Shigeki Imai, and Shinji Kimura
    • Organizer
      The 20th Workshop on Circuits and Systems in Karuizawa(KARUIZAWA-2007)
    • Place of Presentation
      軽井沢
    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] Active Mode Leakage Power Reduction Based on the Controlling Value of Logic Gates2007

    • Author(s)
      Lei Chen, Shinji Kimura
    • Organizer
      Proc. of 14th Workshop on Synthesis And System Integration of Mixed Information technologies(SASIMI2007)
    • Place of Presentation
      Sapporo
    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] Resynthesis Method for Circuit Acceleration on LUT-based FPGA2007

    • Author(s)
      Weijie Xing, Takashi Horiyama, Shunichi Kuromaru, Tomoo Kimura, Shinji Kimura
    • Organizer
      Proc. of 14th Workshop on Synthesis And System Integration of Mixed Information technologies(SASIMI2007)
    • Place of Presentation
      札幌
    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] Resynthesis Method for Circuit Acceleration on LUT-based FPGA2007

    • Author(s)
      Weijie Xing, Takashi Horiyama, Shunichi Kuromaru, Tomoo Kimura, Shinji Kimura
    • Organizer
      Proc. of 14th Workshop on Synthesis And System Integration of Mixed Information technologies(SASIMI2007)
    • Place of Presentation
      Sapporo
    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] Power-Conscious Synthesis of Parallel Prefix Adders under Bitwise Timing Constraints2007

    • Author(s)
      Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
    • Organizer
      Proc. of 14th Workshop on Synthesis And System Integration of Mixed Information technologies(SASIMI2007)
    • Place of Presentation
      Sapporo
    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] 高位検証における等価論理式への変換手法について2006

    • Author(s)
      鄭、木村
    • Organizer
      信学技法(Vol. 105, No.644, pp.79-84)
    • Place of Presentation
      沖縄
    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] Performance and Energy Efficient Data Cache Architecture for Embedded Simultaneous Multithreading Microprocessor2006

    • Author(s)
      Chengjie Zang, Shigeki Imai and Shinji Kimura
    • Organizer
      Proc. of International SoC Design Conference (ISOCC2006)
    • Place of Presentation
      ソウル(韓国)
    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] FCSCAN : An Efficient Multiscan-based Test Compression Technique for Test Cost Reduction2006

    • Author(s)
      Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
    • Organizer
      Proc. of Asia and South Pacific Design Automation Conference 2006
    • Place of Presentation
      Yokohama
    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] An Efficient Instruction Issue Mechanism for Simultaneous Multithreading Microprocessor2006

    • Author(s)
      Taeseok Jeong, Chengjie Zang and Shinji Kimura
    • Organizer
      Proc. Of International SoC Design Conference(ISOCC2006)
    • Place of Presentation
      ソウル(韓国)
    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] FCSCAN:An Efficient Multiscan-based Test Compression Technique for Test Cost Reduction2006

    • Author(s)
      Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
    • Organizer
      Proc. of Asia and South Pacific Design Automation Conference 2006
    • Place of Presentation
      横浜
    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] Performance and Energy Efficient Data Cache Architecture for Embedded Simultaneous Multithreading Microprocessor2006

    • Author(s)
      Chengjie Zang, Shigeki Imai, Shinji Kimura
    • Organizer
      ProInternational SoC Design Conference(ISOCC2006)
    • Place of Presentation
      Seoul
    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] Performance and Energy Efficient Data Cache Architecture for Embedded Simultaneous Multithreading Microprocessor2006

    • Author(s)
      Chengjie Zang, Shigeki Imai, Shinji Kimura
    • Organizer
      Proc. of 13th Workshop on Synthesis And System Integration of Mixed Information technologies(SASIMI2006)
    • Place of Presentation
      Kanazawa
    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] Performance and Energy Efficient Data Cache Architecture for Embedded Simultaneous Multithreading Microprocessor2006

    • Author(s)
      Chengjie Zang, Shigeki Imai, and Shinji Kimura
    • Organizer
      Proc. of 13th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2006)
    • Place of Presentation
      金沢
    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] Transition-Based Coverage Estimation for Symbolic Model Checking2006

    • Author(s)
      Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya
    • Organizer
      Proc. of Asia and South Pacific Design Automation Conference 2006
    • Place of Presentation
      横浜
    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] 動的再構成可能配線について2006

    • Author(s)
      木村 晋二
    • Organizer
      信学技報VLD2006-2(pp. 7-12)
    • Place of Presentation
      沖縄
    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] Transition-Based Coverage Estimation for Symbolic Model Checking2006

    • Author(s)
      Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya
    • Organizer
      Proc. of Asia and South Pacific Design Automation Conference 2006
    • Place of Presentation
      Yokohama
    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] An Efficient Instruction Issue Mechanism for Simultaneous Multithreading Microprocessor2006

    • Author(s)
      Taeseok Jeong, Chengjie Zang, Shinji Kimura
    • Organizer
      ProInternational SoC Design Conference(ISOCC2006)
    • Place of Presentation
      Seoul
    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] 浮動小数点演算と演算チェイニングを考慮した粗粒度再構成可能ハードウェア2006

    • Author(s)
      阿久津 日出実、木村 晋二
    • Organizer
      信学技法(Vol. 105, No.645, pp.43-48)
    • Place of Presentation
      横浜
    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] Transition Traversal Coverage Estimation for Symbolic Model Checking2005

    • Author(s)
      Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya
    • Organizer
      Proc. of 6th International Conference on ASIC(ASICON)
    • Place of Presentation
      上海(中国)
    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] Extended Abstract:Transition Traversal Coverage Estimation for Symbolic Model Checking2005

    • Author(s)
      Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya
    • Organizer
      Proc. of 3rd ACM&IEEE International Conference on Formal Methods and Models for Co-Design(MEMOCODE2005)
    • Place of Presentation
      ヴェローナ(イタリア)
    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] ビット長に制約がある場合の実数演算の固定小数点演算化2005

    • Author(s)
      土井 伸洋, 堀山 貴史, 中西 正樹, 木村 晋二
    • Organizer
      DAシンポジウム2005論文集(pp. 49-54)
    • Place of Presentation
      浜松市
    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] Functional State Coverage Estimation for CTL Model Checking2005

    • Author(s)
      Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya
    • Organizer
      Proc, of 20th International Technical Conference on Circuits/Systems, Compu-ters and Communications (ITC-CSCC 2005)
    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] Extended Abstract : Transition Traversal Coverage Estimation for Symbolic Model Checking2005

    • Author(s)
      Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya
    • Organizer
      Proc. of 3rd ACM&IEEE International Conference on Formal Methods and Models for Co-Design(MEMOCODE 2005)
    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] Duplicated Register File Design for Embedded Simultaneous Multithreading Microprocessor2005

    • Author(s)
      Chengjie Zang, Shigeki Imai, and Shinji Kimura
    • Organizer
      Proc. of 6th International Conference on ASIC(ASICON)
    • Place of Presentation
      上海(中国)
    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] Functional State Coverage Estimation for CTL Model Checking2005

    • Author(s)
      Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya
    • Organizer
      Proc. of 20th International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC2005)
    • Place of Presentation
      済州島(韓国)
    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] Duplicated Register File Design for Embedded Simultaneous Multithreading Microprocessor2005

    • Author(s)
      Chengjie Zang, Shigeki Imai, Shinji Kimura
    • Organizer
      Proc. of 6th International Conference on ASIC(ASICON)
    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] Structural Coverage of Traversed Transitions for Symbolic Model Checking2005

    • Author(s)
      Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya
    • Organizer
      IEICE Technical Report(デザインガイア2005, Vol105, No. 443, VLD2005-87/ICD2005-182, pp.65-70)
    • Place of Presentation
      北九州市
    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-17500047
  • [Presentation] 不揮発メモリの書き込み削減手法のための小面積なエンコーダ/デコーダ回路構成

    • Author(s)
      多和田雅師, 木村晋二, 柳澤政生, 戸川望
    • Organizer
      電子情報通信学会VLSI設計技術研究会
    • Place of Presentation
      別府市
    • Year and Date
      2014-11-26 – 2014-11-28
    • Data Source
      KAKENHI-PROJECT-25280017
  • 1.  WATANABE Katsumasa (60026078)
    # of Collaborated Projects: 4 results
    # of Collaborated Products: 0 results
  • 2.  TAKAGI Kazuyoshi (70273844)
    # of Collaborated Projects: 4 results
    # of Collaborated Products: 0 results
  • 3.  TOGAWA Nozomu (30298161)
    # of Collaborated Projects: 4 results
    # of Collaborated Products: 4 results
  • 4.  HANEDA Hiromasa (10031113)
    # of Collaborated Projects: 3 results
    # of Collaborated Products: 0 results
  • 5.  KUNISHIMA Takeo (20263436)
    # of Collaborated Projects: 2 results
    # of Collaborated Products: 0 results
  • 6.  OHTA Yuzo (80111772)
    # of Collaborated Projects: 2 results
    # of Collaborated Products: 0 results
  • 7.  GOTO Satoshi (10367170)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 2 results
  • 8.  TAKESHI Yoshimura (80367177)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 2 results
  • 9.  HORIYAMA Takashi (60314530)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 10.  NAKANISHI Masaki (40324967)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 11.  安浦 寛人 (80135540)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results

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