Ohtake Satoshi 大竹哲史

… Alternative Names

OHTAKE Satoshi 大竹哲史

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Researcher Number	20314528
Other IDs
External Links
Affiliation (Current)	2025: 大分大学, 理工学部, 教授
Affiliation (based on the past Project Information) *help	2018 – 2023: 大分大学, 理工学部, 教授 2017 – 2018: 大分大学, 理工学部, 准教授 2011 – 2016: 大分大学, 工学部, 准教授 2007 – 2010: Nara Institute of Science and Technology, 情報科学研究科, 助教 2000 – 2006: 奈良先端科学技術大学院大学, 情報科学研究科, 助手
Review Section/Research Field	Principal Investigator Basic Section 60040:Computer system-related / Computer system/Network / Computer system / 計算機科学 Except Principal Investigator Computer system/Network / Computer system / Intensification of Artifact Systems / 計算機科学
Keywords	Principal Investigator 劣化検知 / フィールドテスト / FPGA / レジスタ転送レベル / 遅延故障 / データパス / テスト容易化設計 / VLSIテスト / テストプログラム生成 / 命令レベルテスト … More / プロセッサテスト / FPGA高信頼化 / 高信頼化 / 集積回路 / 信頼性予測 / 劣化情報取得 / 動的回路再構成 / 高信頼化設計 / 劣化検知機構 / 再構成可能集積回路 / 劣化検 / ＢＩＳＴ / ＦＰＧＡ / 耐故障設計 / 対故障設計 / BIST / 故障診断 / 特定用途依存テスト / 通用消費電力 / 通常消費電力 / 組込み自己テスト / テスト生成制約 / 遅延故障テスト / VLSIテスト技術 / 不均一ビット幅 / コントローラ / 縮退故障 / 組合せ回路テスト生成 / 完全故障検出効率 / 平行構造順序回路 / 組合せテスト生成複雑度 / 回路擬似変換 / 階層テスト生成 / 2パターンテスト / パス遅延故障 / テスト生成アルゴリズム … More Except Principal Investigator VLSI / テスト容易化設計 / 組込み自己テスト / 計算機システム / ディペンダブル・コンピューティング / データマイニング / システムオンチップ / VLSIのテスト / 設計自動化 / 組み込み自己テスト / 予防安全 / VLSIテスト / フィールド高信頼化 / 先進運転支援システム / 故障診断 / 先進自動運転 / LSIのテスト / 組込み自己診断法 / 機能安全 / 組込み自己診断 / 故障検査 / ＬＳＩテスト / バーインテスト / アダプティブテスト / テストコスト削減 / LSIテスト / CORE-BAES DESIGN / CO-OPTIMIZATION / TEST ACCESS MECHANISM / TEST ARCHITECTURE / CONSECUTIVE TRANSPARENCY / CONSECUTIVE TESTABILITY / DESIGN FOR TESTABILITY / SYSTEM-ON-CHIP / コアベース設計 / 相互最適化 / テストアクセス機構 / テストアーキテクチャ / 連続透明 / 連続可検査 / 高信頼性ネットワーク / ディペンダブルコンピューティング / スキャン設計 / 安全性(セキュリティ) / テスト容易性 / ネットワークオンチップ / VLSI設計技術 / 遅延故障 / プロセッサ / テスト生成 / 実動作速度テスト / 誤りマスク / テストプログラムテンプレート / 命令レベル自己テスト / プロセッサ自己テスト / テストスケジューリング / SoC / レジスタ転送レベル / 低消費電力 Less

Studies on instruction-level self-degradation detection mechanism and automated test program generation for processorsPrincipal Investigator
- Principal Investigator
  
  大竹哲史
- Project Period (FY)
  2023 – 2025
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Oita University
Preventive safety for VLSIs Based on Adaptive Test during Field Operation
- Principal Investigator
  
  梶原誠司
- Project Period (FY)
  2018 – 2022
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Intensification of Artifact Systems
- Research Institution
  Kyushu Institute of Technology
Studies on Reliability Enhancement of Reconfigurable Integrated Circuits in the IoT EraPrincipal Investigator
- Principal Investigator
  
  Ohtake Satoshi
- Project Period (FY)
  2018 – 2023
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Oita University
Built-In Self Diagnosis for Functional Safety Assurance
- Principal Investigator
  
  Takahashi Hiroshi
- Project Period (FY)
  2016 – 2018
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system
- Research Institution
  Ehime University
Reliability prediction using manufacturing test results of VLSIs
- Principal Investigator
  
  Kajihara Seiji
- Project Period (FY)
  2015 – 2017
- Research Category
  
  Grant-in-Aid for Challenging Exploratory Research
- Research Field
  
  Computer system
- Research Institution
  Kyushu Institute of Technology
Studies on Reliability Enhancement of Circuits Programmed on FPGAsPrincipal Investigator
- Principal Investigator
  
  Ohtake Satoshi
- Project Period (FY)
  2014 – 2017
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system
- Research Institution
  Oita University
Studies on Normal-Operation-Aware Accurate Delay Fault Testing for VLSIsPrincipal Investigator
- Principal Investigator
  
  OHTAKE Satoshi
- Project Period (FY)
  2010 – 2013
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Oita University
  Nara Institute of Science and Technology
Basic Studies on Testability and Security for Network-on-Chip
- Principal Investigator
  
  FUJIWARA Hideo
- Project Period (FY)
  2008 – 2010
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Nara Institute of Science and Technology
Software-Based Self-Test for Processors to guarantee high fault efficiency for structured faults
- Principal Investigator
  
  INOUE Michiko
- Project Period (FY)
  2006 – 2008
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system/Network
- Research Institution
  Nara Institute of Science and Technology
大規模・高性能VLSIのレジスタ転送レベルにおけるテスト容易化設計に関する研究Principal Investigator
- Principal Investigator
  
  大竹哲史
- Project Period (FY)
  2005 – 2007
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Nara Institute of Science and Technology
BASIC STUDIES ON TEST ARCHITECTURE AND DESIGN FOR TESTABILITY FOR SYSTEM-ON-CHIP
- Principal Investigator
  
  FUJIWARA Hideo
- Project Period (FY)
  2003 – 2006
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  NARA INSTITUTE OF SCIENCE AND TECHNOLOGY
低消費電力性とテスト容易性をともに考慮したVLSI高位設計
- Principal Investigator
  
  INOUE Michiko
- Project Period (FY)
  2002 – 2004
- Research Category
  
  Grant-in-Aid for Exploratory Research
- Research Field
  
  計算機科学
- Research Institution
  Nara Institute of Science and Technology
大規模・高性能VLSIの遅延故障に対するテスト容易化設計に関する研究Principal Investigator
- Principal Investigator
  
  大竹哲史
- Project Period (FY)
  2000 – 2001
- Research Category
  
  Grant-in-Aid for Encouragement of Young Scientists (A)
- Research Field
  
  計算機科学
- Research Institution
  Nara Institute of Science and Technology

[Journal Article] Hardware Implementation of Constant Monitoring System of Fetal Heart Sounds2023
- Author(s)
  Funakoshi Miyabi, Satoshi Ohtake
- Journal Title
  
  2023 International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan)
  
  Volume: - Pages: 663-664
- DOI
  10.1109/icce-taiwan58799.2023.10227017
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18K11220
[Journal Article] A Built-In Self-Diagnostic Mechanism for Delay Faults Based on Self-Generation of Expected Signatures2019
- Author(s)
  Hiramoto Yushiro、Ohtake Satoshi、Takahashi Hiroshi
- Journal Title
  
  Proceedings of IEEE 28th Asian Test Symposium
  
  Volume: - Pages: 31-36
- DOI
  10.1109/ats47505.2019.000-4
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18K11220
[Journal Article] 遅延故障BIST 高品質化のためのLFSR シード生成法2017
- Author(s)
  渡邊恭之介，大竹哲史
- Journal Title
  
  電子情報通信学会技術報告
  
  Volume: 117 Pages: 49-54
- Data Source
  KAKENHI-PROJECT-26330067
[Journal Article] An approach to LFSR-based X-masking for built-in self-test2017
- Author(s)
  Daichi Shimazu and Satoshi Ohtake
- Journal Title
  
  Proceedings of 18th IEEE Latin American Test Symposium
  
  Volume: - Pages: 1-4
- DOI
  10.1109/latw.2017.7906741
- Peer Reviewed / Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-26330067
[Journal Article] 論理回路の組込み自己診断に関する提案2016
- Author(s)
  香川敬祐, 矢野郁也, 王森レイ，樋上喜信，高橋寛，大竹哲史
- Journal Title
  
  電子情報通信学会技術研究報告
  
  Volume: DC2016-76 Pages: 11-16
- Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-16K00074
[Journal Article] A method of one-pass seed generation for LFSR-based deterministic/pseudo-random testing of static faults2015
- Author(s)
  Takanori Moriyasu and Satoshi Ohtake
- Journal Title
  
  Proceedings of IEEE Latin American Test Symposium
  
  Volume: なし
- Peer Reviewed / Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-26330067
[Journal Article] 階層BIST向けLFSRシード生成法2015
- Author(s)
  佐脇光亮, 大竹哲史
- Journal Title
  
  電子情報通信学会技術報告(DC2014-85)
  
  Volume: 114 Pages: 43-48
- Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-26330067
[Journal Article] 遅延故障BIST向けLFSR/MISRシード生成2015
- Author(s)
  嶋津大地, 大竹哲史
- Journal Title
  
  電子情報通信学会技術報告
  
  Volume: Vol.115, No.339 Pages: 213-218
- Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-26330067
[Journal Article] A delay measurement mechanism for asynchronous circuits of bundled-data model2015
- Author(s)
  Syuichi Sato and Satoshi Ohtake
- Journal Title
  
  Proceedings of IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2015
  
  Volume: なし Pages: 243-248
- DOI
  10.1109/ddecs.2015.55
- Peer Reviewed / Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-26330067
[Journal Article] FPGAテストのための耐ソフトエラーBIST2015
- Author(s)
  上田大樹, 嶋津大地, 大竹哲史
- Journal Title
  
  電子情報通信学会技術報告
  
  Volume: Vol.115, No.339 Pages: 219-224
- Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-26330067
[Journal Article] A method of diagnostic test generation for transition faults2015
- Author(s)
  Renji Ono and Satoshi Ohtake
- Journal Title
  
  Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing 2015
  
  Volume: なし Pages: 273-278
- DOI
  10.1109/prdc.2015.47
- Peer Reviewed / Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-26330067
[Journal Article] A Method of LFSR Seed Generation for Scan-Based BIST Using Constrained ATPG2013
- Author(s)
  Takanori Moriyasu, Satoshi Ohtake
- Journal Title
  
  Fifth International Workshop on Virtual Environment and Network-Oriented Applications
  
  Volume: なし
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22700054
[Journal Article] A method of LFSR seed generation for scan -based BIST using constrained ATPG2013
- Author(s)
  Takanori Moriyasu and Satoshi Ohtake
- Journal Title
  
  Proceedings of 2013 Seventh International Conference on Complex, Intelligent, an d Software Intensive Systems
  
  Volume: なし Pages: 755-759
- DOI
  10.1109/cisis.2013.136
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22700054
[Journal Article] F-scan test generation model for delay fault testing at RTL using standard full scan ATPG2011
- Author(s)
  Marie Engelene Jimenez Obien, Satoshi Ohtake and Hideo Fujiwara
- Journal Title
  
  Proceedings of IEEE European Test Symposium
  
  Pages: 203-203
- DOI
  10.1109/ets.2011.61
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22700054
[Journal Article] Bipartite full scan design : A DFT method for asynchronous circuits2011
- Author(s)
  Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara
- Journal Title
  
  Proceedings of IEEE Asian Test Symposium
  
  Pages: 206-211
- DOI
  10.1109/ats.2010.44
- Data Source
  KAKENHI-PROJECT-22700054
[Journal Article] F-Scan : A DFT Method for Functional Scan at RTL2011
- Author(s)
  Marie Engelene Jimenez Obien, Satoshi Ohtake, Hideo Fujiwara
- Journal Title
  
  IEICE Trans. on Inf. and Syst. Vol.E94-D, No.1
  
  Pages: 104-113
- NAID
  10027989592
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300018
[Journal Article] Delay Testing: Improving Test Quality and Avoiding Over-testing2011
- Author(s)
  Seiji Kajihara, (他2名)
- Journal Title
  
  IPSJ Transactions on System LSI Design Methodology
  
  Volume: 4 Pages: 117-130
- DOI
  10.2197/ipsjtsldm.4.117
- NAID
  110009598052
- ISSN
  1882-6687
- Language
  English
- Data Source
  KAKENHI-PROJECT-21300015, KAKENHI-PROJECT-22700054
[Journal Article] Delay fault ATPG for F-scannable RTL circuits2010
- Author(s)
  Marie Engelene Jimenez Obien, Satoshi Ohtake and Hideo Fujiwara
- Journal Title
  
  Proceedings of IEEE International Symposium on Communications and Information Technologies (ISCIT'10), IEEE Xplore
  
  Pages: 717-722
- DOI
  10.1109/iscit.2010.5665081
- Data Source
  KAKENHI-PROJECT-22700054
[Journal Article] Constrained ATPG for functional RTL circuits using F-scan2010
- Author(s)
  Marie Engelene Jimenez Obien, Satoshi Ohtake, Hideo Fujiwara
- Journal Title
  
  Proceedings of IEEE International Test Conference
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22700054
[Journal Article] Bipartite full scan design : A DFT method for asynchronous circuits2010
- Author(s)
  Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara
- Journal Title
  
  Proceedings of IEEE Asian Test Symposium
  
  Pages: 206-211
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22700054
[Journal Article] Delay fault ATPG for F-scannable RTL circuits2010
- Author(s)
  Marie Engelene Jimenez Obien, Satoshi Ohtake, Hideo Fujiwara
- Journal Title
  
  Proceedings of IEEE International Symposium on Communications and Information Technologies
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22700054
[Journal Article] Constrained ATPG for functional RTL circuits using F-scan2010
- Author(s)
  Marie Engelene Jimenez Obien, Satoshi Ohtake and Hideo Fujiwara
- Journal Title
  
  Proceedings of IEEE International Test Conference
  
  Volume: Paper 21.1 Pages: 1-10
- DOI
  10.1109/test.2010.5699265
- Data Source
  KAKENHI-PROJECT-22700054
[Journal Article] A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification2010
- Author(s)
  Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara
- Journal Title
  
  IEICE Trans. on Information and Systems Vol.E93-D, No.7
  
  Pages: 1857-1865
- NAID
  10027363954
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300018
[Journal Article] Unsensitizable Path Identification at RTL Using High-Level Synthesis Information2009
- Author(s)
  S. Ohtake
- Journal Title
  
  Digest of papers of 16th IEEE International Test Synthesis Workshop (CD-ROM)
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18500038
[Journal Article] Design for testability method to avoid error masking of software-based self-test for processors2008
- Author(s)
  Masato Nakazato, Michiko Inoue, Satoshi Ohtake and Hideo Fujiwara
- Journal Title
  
  IEICE Trans. on Information and Systems Vol.E91-D, No.3
  
  Pages: 763-770
- NAID
  10026802191
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18500038
[Journal Article] RTL don't care path identification and synthesis for transforming don't care paths into false paths2007
- Author(s)
  Yuki Yoshikawa, Satoshi Ohtake Hideo Fujiwara,
- Journal Title
  
  8th IEEE Workshop on RTL and High Level Testing
  
  Pages: 9-15
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17700062
[Journal Article] Efficient path delay test generation based on stuck-at test generation using checker circuitry2007
- Author(s)
  Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko Hideo Fujiwara
- Journal Title
  
  IEEE/ACM International Conference on Computer -Aided Design
  
  Pages: 418-423
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17700062
[Journal Article] False path identification using RTL information and its application to over-testing reduction for delay faults2007
- Author(s)
  Yuki Yoshikawa, Satoshi Ohtake Hideo Fujiwara,
- Journal Title
  
  IEEE 16th Asian Test Symposium
  
  Pages: 65-68
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17700062
[Journal Article] A DFT method based on partially strong testability of RTL data paths to guarantee complete fault efficiency2006
- Author(s)
  Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara
- Journal Title
  
  Trans. of IEICE Vol. 89-D, No. 8
  
  Pages: 1643-1653
- NAID
  110007380504
- Data Source
  KAKENHI-PROJECT-17700062
[Journal Article] Non-scan design for single-port-change delay fault testability2006
- Author(s)
  YUKi YosniKawa, Satosni Ohtake, Michiko Inoue, Hideo Fuiiwara
- Journal Title
  
  IPSJ Journal Vol. 47, No. 6
  
  Pages: 1619-1628
- NAID
  130000022321
- Data Source
  KAKENHI-PROJECT-17700062
[Journal Article] Non-Scan Design for Single-Port-Change Delay Fault Testability2006
- Author(s)
  Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara
- Journal Title
  
  IPSJ (Information Processing Society of Japan) Journal (Special Issue on Design Methodology of System LSIs) Vol.47, No.6
  
  Pages: 1619-1628
- NAID
  130000022321
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] A DET Method Based on Partially Strong Testability of RTL Data Paths to Guarantee Complete Fault Efficiency2006
- Author(s)
  Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara
- Journal Title
  
  Trans. of IEICE (DI) Vol.J89-D, No.8
  
  Pages: 1643-1653
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] Design for testability of software-based self-test for processors2006
- Author(s)
  Masato NaKazato, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara
- Journal Title
  
  15th IEEE Asian Test Symposium
  
  Pages: 375-380
- NAID
  110004748904
- Data Source
  KAKENHI-PROJECT-17700062
[Journal Article] Low-cost hardening of image processing applications against soft errors systems2006
- Author(s)
  Ilia Polian, Bernd BECKER, Masato Nakazato, Satoshi Ohtake, Hideo Fujiwara
- Journal Title
  
  The 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI
  
  Pages: 274-279
- Data Source
  KAKENHI-PROJECT-17700062
[Journal Article] A new test generation model for broadside transition testing of partial scan circuits2006
- Author(s)
  Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
- Journal Title
  
  IFIP International Conference on Very Large Scale Integration
  
  Pages: 308-313
- Data Source
  KAKENHI-PROJECT-17700062
[Journal Article] An approach to reduce over-testing of path delay faults in data paths using RT-level information2006
- Author(s)
  Yuki Yoshikawa, Satoshi Ohtake, Hideo Fujiwara
- Journal Title
  
  11th IEEE European Test Symposium
  
  Pages: 146-151
- Data Source
  KAKENHI-PROJECT-17700062
[Journal Article] A DFT method for data paths based on partially strong testability to guarantee complete fault efficiency2005
- Author(s)
  Hiroyuki lwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara
- Journal Title
  
  IEEE the 14th Asian Test Symposium
  
  Pages: 306-311
- Data Source
  KAKENHI-PROJECT-17700062
[Journal Article] Design for testability based on single-port-change delay testing for data paths2005
- Author(s)
  Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue, Hideo Fiujiwara
- Journal Title
  
  IEEE the 14th Asian Test Symposium
  
  Pages: 254-259
- Data Source
  KAKENHI-PROJECT-17700062
[Journal Article] A Test Generation Method for Path Delay Faults Using Stuck-at Fault Test Generation Algorithms2005
- Author(s)
  Kouhei Ohtani, Satoshi Ohtake, Hideo Fujiwara
- Journal Title
  
  Trans. of IEICE (DI) (in Japanese) Vol.J88-D-I, No.6
  
  Pages: 1057-1064
- NAID
  110003203379
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency2004
- Author(s)
  Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara
- Journal Title
  
  Journal of Electronic Testing : Theory and Applications Vol.20, No.3
  
  Pages: 315-323
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] A Design Scheme for Delay Testing of Controllers Using StateTransition Information2004
- Author(s)
  Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
- Journal Title
  
  IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences Vol.E87-A, No.12
  
  Pages: 3200-3207
- NAID
  110003212858
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] A Non-Scan DFT Method at Register-Transfer Level to Achieve 100% Fault Efficiency,2003
- Author(s)
  Satoshi Ohtake, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara
- Journal Title
  
  IPSJ (Information Processing Society of Japan) Journal. Vol.44, No.5
  
  Pages: 1266-1275
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] Design for two-pattern testability of controller-data path circuits2003
- Author(s)
  Md.Altaf-Ul-Amin, Satoshi Ohtake, Hideo Fujiwara
- Journal Title
  
  IEICE Trans. on Information and Systems Vol.E86-D, No.6
  
  Pages: 1042-1049
- NAID
  110004024945
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] A Test Generation Method for Path Delay Faults in Sequential Circuits with Discontinuous Reconvergence Structure2003
- Author(s)
  Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
- Journal Title
  
  Trans, of IEICE (DI) (in Japanese) Vol.J86-D-I, No.12
  
  Pages: 872-883
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] A Non-Scan DFT Method at Register-Transfer Level to Achieve 100% Fault Efficiency2003
- Author(s)
  Satoshi Ohtake
- Journal Title
  
  Information Processing Society of Japan Journal 44, 5
  
  Pages: 1266-1275
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] A new class of sequential circuits with combinational test generation complexity for path delay faults2003
- Author(s)
  Shunjiro Miwa, Satoshi Ohtake, Hideo Fujiwara
- Journal Title
  
  Trans. of IEICE (DI) (in Japanese) Vol.186-D-I, No.11
  
  Pages: 809-820
- NAID
  110003171214
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Patent] 回路診断テスト装置、及び回路診断テスト方法2019
- Inventor(s)
  大竹哲史
- Industrial Property Rights Holder
  大竹哲史
- Industrial Property Rights Type
  特許
- Filing Date
  2019
- Data Source
  KAKENHI-PROJECT-16K00074
[Patent] 回路診断テスト装置、及び回路診断テスト方法2019
- Inventor(s)
  大竹哲史，平本悠翔郎
- Industrial Property Rights Holder
  大分大学
- Industrial Property Rights Type
  特許
- Industrial Property Number
  2019-027786
- Filing Date
  2019
- Data Source
  KAKENHI-PROJECT-18K11220
[Patent] スキャンBIST のLFSR シード生成法2013
- Inventor(s)
  大竹哲史, 森保孝憲
- Industrial Property Rights Type
  特許
- Industrial Property Number
  2013-148812
- Filing Date
  2013-07-17
- Data Source
  KAKENHI-PROJECT-22700054
[Patent] 遅延故障に対するスキャンBISTのLFSRシード生成法2013
- Inventor(s)
  大竹哲史, 本田太郎
- Industrial Property Rights Holder
  大分大学
- Industrial Property Rights Type
  特許
- Industrial Property Number
  2013-148663
- Filing Date
  2013-07-17
- Data Source
  KAKENHI-PROJECT-22700054
[Patent] スキャンBISTのLFSRシード生成法2013
- Inventor(s)
  大竹哲史, 森保孝憲
- Industrial Property Rights Holder
  大分大学
- Industrial Property Rights Type
  特許
- Industrial Property Number
  2013-148812
- Filing Date
  2013-07-17
- Data Source
  KAKENHI-PROJECT-22700054
[Patent] 遅延故障に対するスキャンBISTのLFSR シード生成法2013
- Inventor(s)
  大竹哲史, 本田太郎
- Industrial Property Rights Type
  特許
- Industrial Property Number
  2013-148663
- Filing Date
  2013-07-17
- Data Source
  KAKENHI-PROJECT-22700054
[Presentation] 胎児心音常時モニタリングシステムのハードウェア実装2023
- Author(s)
  舩越雅，大竹哲史
- Organizer
  火の国情報シンポジウム
- Data Source
  KAKENHI-PROJECT-18K11220
[Presentation] SATを用いた遅延故障BIST向けLFSRシード生成法2021
- Author(s)
  岩本岬汰郎，大竹哲史
- Organizer
  電子情報通信学会
- Data Source
  KAKENHI-PROJECT-18K11220
[Presentation] Compacted Seed Generation for Built-in Self-Diagnosis of Delay Faults2019
- Author(s)
  Yuta Nakano, Satoshi Ohtake
- Organizer
  IEEE Workshop on RTL and High Level Testing
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11220
[Presentation] 遅延故障向け組込み自己診断のための圧縮シード生成法2019
- Author(s)
  中野雄太，大竹哲史
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Data Source
  KAKENHI-PROJECT-18K11220
[Presentation] 期待署名自己生成に基づく組込み自己診断機構2019
- Author(s)
  平本悠翔郎, 大竹哲史, 高橋　寛
- Organizer
  電子情報通信学会DC研究会
- Data Source
  KAKENHI-PROJECT-18KT0014
[Presentation] 期待署名自己生成に基づく組込み自己診断機構2018
- Author(s)
  平本悠翔郎, 大竹哲史, 高橋　寛
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Data Source
  KAKENHI-PROJECT-18K11220
[Presentation] 期待署名自己生成に基づく組込み自己診断機構2018
- Author(s)
  平本悠翔郎，大竹哲史，高橋　寛
- Organizer
  電子情報通信学会技術報告
- Data Source
  KAKENHI-PROJECT-16K00074
[Presentation] 機械学習を用いたフェールチップ判別の性能向上に関する検討2017
- Author(s)
  柚留木大地, 大竹哲史, 中村芳行
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  東京都
- Data Source
  KAKENHI-PROJECT-15K12004
[Presentation] 機械学習を用いたフェールチップ判別における適用識別器と判別確度の決定法2017
- Author(s)
  柚留木大地, 大竹哲史, 中村芳行
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Data Source
  KAKENHI-PROJECT-15K12004
[Presentation] オンチップ故障診断のためのLFSRシード生成法2016
- Author(s)
  南薗隼人，大竹哲史
- Organizer
  電子情報通信学会
- Place of Presentation
  立命館大学大阪いばらきキャンパス（大阪府茨木市）
- Year and Date
  2016-11-28
- Data Source
  KAKENHI-PROJECT-26330067
[Presentation] A field test architecture for circuits configured on FPGAs2015
- Author(s)
  Sho Kano and Satoshi Ohtake
- Organizer
  16th IEEE Workshop on RTL and High Level Testing (WRTLT'15)
- Place of Presentation
  ムンバイ，インド
- Year and Date
  2015-11-25
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26330067
[Presentation] 遷移故障向け診断テスト生成の一手法2014
- Author(s)
  小野廉二, 大竹哲史
- Organizer
  情報処理学会九州支部火の国情報シンポジウム
- Place of Presentation
  大分大学工学部（大分県大分市）
- Data Source
  KAKENHI-PROJECT-22700054
[Presentation] 遷移故障向け診断テスト生成の一手法2014
- Author(s)
  小野廉二, 大竹哲史
- Organizer
  情報処理学会研究会報告(九州支部火の国情報シンポジウム2014 論文集)
- Place of Presentation
  (4A-4, 1-6)
- Data Source
  KAKENHI-PROJECT-22700054
[Presentation] 束データ方式の非同期式回路に対する遅延測定機構2014
- Author(s)
  佐藤秀一, 大竹哲史
- Organizer
  情報処理学会九州支部火の国情報シンポジウム
- Place of Presentation
  大分大学工学部（大分県大分市）
- Data Source
  KAKENHI-PROJECT-22700054
[Presentation] 束データ方式の非同期式回路に対する遅延測定機構2014
- Author(s)
  佐藤秀一, 大竹哲史
- Organizer
  情報処理学会研究会報告(九州支部火の国情報シンポジウム2014 論文集)
- Place of Presentation
  (1A-2, 1-8)
- Data Source
  KAKENHI-PROJECT-22700054
[Presentation] 制約付きテスト生成を用いたスキャンBIST のLFSR シード生成法2013
- Author(s)
  森保孝憲, 大竹哲史
- Organizer
  電子情報通信学会技術報告(DC2013-11)
- Place of Presentation
  (Vol.113, No.104, 7-12)
- Data Source
  KAKENHI-PROJECT-22700054
[Presentation] RTL 情報を用いた高品質遷移故障テスト生成法2013
- Author(s)
  中島寛之, 大竹哲史
- Organizer
  電子情報通信学会技術報告(DC2013-60)
- Place of Presentation
  (Vol.113, No.321, 239-244)
- Data Source
  KAKENHI-PROJECT-22700054
[Presentation] 遅延故障BIST向けLFSRシード生成法2013
- Author(s)
  本田太郎, 大竹哲史
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  鹿児島県文化センター（鹿児島県鹿児島市）
- Data Source
  KAKENHI-PROJECT-22700054
[Presentation] 遅延故障BIST 向けLFSR シード生成法2013
- Author(s)
  本田太郎, 大竹哲史
- Organizer
  電子情報通信学会技術報告(DC2013-58)
- Place of Presentation
  (Vol.113, No.321, 227-231)
- Data Source
  KAKENHI-PROJECT-22700054
[Presentation] RTL情報を用いた高品質遷移故障テスト生成法2013
- Author(s)
  中島寛之, 大竹哲史
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  鹿児島県文化センター（鹿児島県鹿児島市）
- Data Source
  KAKENHI-PROJECT-22700054
[Presentation] 同期式設計から変換されたQDI 回路のテスト生成法2012
- Author(s)
  内田行紀, 村田絵理, 大竹哲史, 中島康彦
- Organizer
  電子情報通信学会技術報告(DC2011-83)
- Place of Presentation
  (Vol.111, No.435, 43-48)
- Data Source
  KAKENHI-PROJECT-22700054
[Presentation] 同期式設計から変換されたQDI回路のテスト生成法2012
- Author(s)
  内田行紀、村田絵理、大竹哲史、中島康彦
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  機会振興会館
- Year and Date
  2012-02-13
- Data Source
  KAKENHI-PROJECT-22700054
[Presentation] 組込み自己テストにおける温度均一化制御2011
- Author(s)
  村田絵理、大竹哲史、中島康彦
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会(デザインガイア2011)
- Place of Presentation
  ニューウェルシティ宮崎
- Year and Date
  2011-11-30
- Data Source
  KAKENHI-PROJECT-22700054
[Presentation] 組込み自己テストにおける温度均一化制御2011
- Author(s)
  村田絵理, 大竹哲史, 中島康彦
- Organizer
  電子情報通信学会技術報告(DC2011-62)
- Place of Presentation
  (Vol.111, No.325, 197-202)
- Data Source
  KAKENHI-PROJECT-22700054
[Presentation] Delay Fault ATPG for F-Scannable RTL Circuits2010
- Author(s)
  Marie Engelene Jimenez Obien, Satoshi Ohtake, Hideo Fujiwara
- Organizer
  IEEE Int.Symp. on Communications and Information Technologies
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Bipartite Full Scan Design : A DFT Method for Asynchronous Circuits2010
- Author(s)
  Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara
- Organizer
  Proc. of IEEE the 19th Asian Test Symposium
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] A Method of Unsensitizable Path Identification using High Level Design Information2010
- Author(s)
  Satoshi Ohtake, Naotsugu Ikeda, Michiko Inoue, Hideo Fujiwara
- Organizer
  5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] full scan design method for asynchronous sequential circuits based on C-element scan paths2010
- Author(s)
  Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara
- Organizer
  Technical Report of IEICE (DC2010-8)
- Place of Presentation
  (Vol.110, No.106, 1-6)
- Data Source
  KAKENHI-PROJECT-22700054
[Presentation] Constrained ATPG for Functional RTL Circuits Using F-Scan2010
- Author(s)
  Marie Engelene J.Obien, Satoshi Ohtake, Hideo Fujiwara
- Organizer
  2010 IEEE International Test Conference
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] A Synthesis Method to Propagate False Path Information from RTL to Gate Level2010
- Author(s)
  Satoshi Ohtake
- Organizer
  13th IEEE International Symposium on Design and Diagnosis of Electronic Circuits and Systems
- Place of Presentation
  Vienna, Austria
- Year and Date
  2010-04-15
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] A Synthesis Method to Propagate False Path Information from RTL to Gate Level2010
- Author(s)
  Satoshi Ohtake, Hiroshi Iwata, Hideo Fujiwara
- Organizer
  13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Enhancing False Path Identification from RTL for Reducing Design and Test Futileness2010
- Author(s)
  Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara
- Organizer
  The 5th IEEE International Symposium on Electronic Design, Test & Applications
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Unsensitizable Path Identification at RTL Using High-Level Synthes is Information2009
- Author(s)
  Satoshi Ohtake, Naotsugu Ikeda, Michiko Inoue, Hideo Fuji waral
- Organizer
  Digest of papers of 16th IEEE International Test Synthesis Workshop
- Data Source
  KAKENHI-PROJECT-18500038
[Presentation] A Synthesis Method to Alleviate Over-testing of Delay Faults Based on RTL Don't Care Path Identification2009
- Author(s)
  Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara
- Organizer
  IEEE 27th VLSI Test Symposium
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Fast False Path Identification Based on Functional Unsensitizability Using RTL Information2009
- Author(s)
  Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara
- Organizer
  14th Asia and South Pacific Design Automation Conference
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] RTL false path identification using high level synthesis information2008
- Author(s)
  Naotsugu Ikeda, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  機会振興会館
- Data Source
  KAKENHI-PROJECT-17700062
[Presentation] Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-Cycle Paths2008
- Author(s)
  Thomas Edison Yu, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara
- Organizer
  Proc. of IEEE the 17th Asian Test Symposium
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Design for testability of software-based self-test for processors2006
- Author(s)
  Masato Nakazato, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara
- Organizer
  15th IEEE Asian Test Symposium(ATS'06)
- Data Source
  KAKENHI-PROJECT-18500038
[Presentation] プロセッサの命令レベル自己テストのためのテスト容易化設計2006
- Author(s)
  中里昌人, 大竹哲史, 井上美智子, 藤原秀雄
- Organizer
  信学技報(ICD2006-40~59)
- Data Source
  KAKENHI-PROJECT-18500038
[Presentation] 制約付きテスト生成を用いたスキャンBISTのLFSRシード生成法
- Author(s)
  森保孝憲、大竹哲史
- Organizer
  電子情報通信学会DC研究会
- Place of Presentation
  東京
- Data Source
  KAKENHI-PROJECT-22700054
[Presentation] FPGA搭載回路のフィールド自己テスト
- Author(s)
  鹿野礁, 大竹哲史
- Organizer
  第71回FTC研究会
- Place of Presentation
  かんぽの宿青梅（東京都青梅市）
- Year and Date
  2014-07-17 – 2014-07-19
- Data Source
  KAKENHI-PROJECT-26330067
[Presentation] A method of LFSR seed generation for delay fault BIST using constrained ATPG
- Author(s)
  Taro Honda and Satoshi Ohtake
- Organizer
  14th IEEE Workshop on RTL and High Level Testing
- Place of Presentation
  Hangzhou Jinxi Hotel (中華人民共和国浙江省杭州市)
- Year and Date
  2014-11-19 – 2014-11-20
- Data Source
  KAKENHI-PROJECT-26330067
[Presentation] 制約付きテスト生成を用いたスキャンBISTのLFSRシード生成法
- Author(s)
  森保孝憲, 大竹哲史
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  機械振興会館（東京都港区）
- Data Source
  KAKENHI-PROJECT-22700054
[Presentation] 階層BIST向けLFSRシード生成法
- Author(s)
  佐脇光亮, 大竹哲史
- Organizer
  第72回FTC研究会
- Place of Presentation
  かんぽの宿山鹿（熊本県山鹿市）
- Year and Date
  2015-01-22 – 2015-01-24
- Data Source
  KAKENHI-PROJECT-26330067
[Presentation] A delay measurement mechanism for asynchronous circuits of bundled-data model
- Author(s)
  Shuichi Sato and Satoshi Ohtake
- Organizer
  14th IEEE Workshop on RTL and High Level Testing
- Place of Presentation
  Hangzhou Jinxi Hotel (中華人民共和国浙江省杭州市)
- Year and Date
  2014-11-19 – 2014-11-20
- Data Source
  KAKENHI-PROJECT-26330067

1. INOUE Michiko (30273840)

# of Collaborated Projects: 4 results

# of Collaborated Products: 9 results
2. YONEDA Tomokazu (20359871)

# of Collaborated Projects: 4 results

# of Collaborated Products: 2 results
3. FUJIWARA Hideo (70029346)

# of Collaborated Projects: 2 results

# of Collaborated Products: 20 results
4. Kajihara Seiji (80252592)

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
5. Takahashi Hiroshi (80226878)

# of Collaborated Projects: 1 results

# of Collaborated Products: 2 results
6. 樋上喜信 (40304654)

# of Collaborated Projects: 1 results

# of Collaborated Products: 1 results
7. 王森レイ (90735581)

# of Collaborated Projects: 1 results

# of Collaborated Products: 1 results
8. 三宅庸資 (60793403)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
9. SATO Shuichi

# of Collaborated Projects: 1 results

# of Collaborated Products: 7 results
10. MORIYASU Takanori

# of Collaborated Projects: 1 results

# of Collaborated Products: 1 results
11. HONDA Taro

# of Collaborated Projects: 1 results

# of Collaborated Products: 1 results
12. ONO Renji

# of Collaborated Projects: 1 results

# of Collaborated Products: 1 results
13. KANO Sho

# of Collaborated Projects: 1 results

# of Collaborated Products: 3 results
14. SAWAKI Kosuke

# of Collaborated Projects: 1 results

# of Collaborated Products: 2 results
15. UEDA Hiroki

# of Collaborated Projects: 1 results

# of Collaborated Products: 1 results
16. SHIMAZU Daichi

# of Collaborated Projects: 1 results

# of Collaborated Products: 3 results
17. MINAMIZONO Hayato

# of Collaborated Projects: 1 results

# of Collaborated Products: 1 results
18. WATANABE Kyonosuke

# of Collaborated Projects: 1 results

# of Collaborated Products: 1 results
19. SATO Yasuo

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
20. NAKAMURA Yoshiyuki

# of Collaborated Projects: 1 results

# of Collaborated Products: 2 results

Ohtake Satoshi 大竹 哲史

OHTAKE Satoshi 大竹 哲史

Research Projects

Research Products

Co-Researchers

Studies on instruction-level self-degradation detection mechanism and automated test program generation for processorsPrincipal Investigator

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Preventive safety for VLSIs Based on Adaptive Test during Field Operation

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Studies on Reliability Enhancement of Reconfigurable Integrated Circuits in the IoT EraPrincipal Investigator

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Built-In Self Diagnosis for Functional Safety Assurance

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Reliability prediction using manufacturing test results of VLSIs

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Studies on Reliability Enhancement of Circuits Programmed on FPGAsPrincipal Investigator

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Studies on Normal-Operation-Aware Accurate Delay Fault Testing for VLSIsPrincipal Investigator

Principal Investigator

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Basic Studies on Testability and Security for Network-on-Chip

Principal Investigator

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Software-Based Self-Test for Processors to guarantee high fault efficiency for structured faults

Principal Investigator

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大規模・高性能VLSIのレジスタ転送レベルにおけるテスト容易化設計に関する研究Principal Investigator

Principal Investigator

Project Period (FY)

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Research Institution

BASIC STUDIES ON TEST ARCHITECTURE AND DESIGN FOR TESTABILITY FOR SYSTEM-ON-CHIP

Principal Investigator

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Research Institution

低消費電力性とテスト容易性をともに考慮したVLSI高位設計

Principal Investigator

Project Period (FY)

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Research Field

Research Institution

大規模・高性能VLSIの遅延故障に対するテスト容易化設計に関する研究Principal Investigator

Principal Investigator

Project Period (FY)

Ohtake Satoshi 大竹哲史

OHTAKE Satoshi 大竹哲史