YONEDA Tomokazu 米田友和

Researcher Number	20359871
Other IDs
External Links
Affiliation (based on the past Project Information) *help	2013 – 2015: 奈良先端科学技術大学院大学, 情報科学研究科, 助教 2007 – 2011: Nara Institute of Science and Technology, 情報科学研究科, 助教 2008: Nara Institute of Science and Technology, 情報科学研究科, 助教授 2002 – 2006: 奈良先端科学技術大学院大学, 情報科学研究科, 助手
Review Section/Research Field	Principal Investigator Computer system/Network Except Principal Investigator Computer system/Network / Computer system / 計算機科学
Keywords	Principal Investigator システムオンチップ / テストアーキテクチャ / テスト容易化設計 / 三次元集積化 / 3次元集積化 / 高品質遅延テスト / ネットワークオンチップ / マルチクロックドメイン / テストスケジューリング / 設計自動化 … More Except Principal Investigator … More テスト容易化設計 / システムオンチップ / VLSIのテスト / 設計自動化 / VLSI / CORE-BAES DESIGN / CO-OPTIMIZATION / TEST ACCESS MECHANISM / TEST ARCHITECTURE / CONSECUTIVE TRANSPARENCY / CONSECUTIVE TESTABILITY / DESIGN FOR TESTABILITY / SYSTEM-ON-CHIP / コアベース設計 / 相互最適化 / テストアクセス機構 / テストアーキテクチャ / 連続透明 / 連続可検査 / ディペダブル・コンピューティング / ディペンダブル・コンピューティング / 計算機システム / 組み込みメモリ / IRドロップ / 組み込み自己テスト / LSI信頼性 / 高信頼性ネットワーク / ディペンダブルコンピューティング / スキャン設計 / 安全性(セキュリティ) / テスト容易性 / ネットワークオンチップ / VLSI設計技術 / 遅延故障 / プロセッサ / テスト生成 / 実動作速度テスト / 誤りマスク / テストプログラムテンプレート / 命令レベル自己テスト / プロセッサ自己テスト / テストスケジューリング / SoC / レジスタ転送レベル / 低消費電力 Less

Research on Built-in Self-Test to Enhance LSI Reliability through its Lifecycle
- Principal Investigator
  
  Inoue Michiko
- Project Period (FY)
  2013 – 2015
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system
- Research Institution
  Nara Institute of Science and Technology
Research on Test Methodology for 3D Integrated SoCsPrincipal Investigator
- Principal Investigator
  
  YONEDA Tomokazu
- Project Period (FY)
  2009 – 2011
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Nara Institute of Science and Technology
Basic Studies on Testability and Security for Network-on-Chip
- Principal Investigator
  
  FUJIWARA Hideo
- Project Period (FY)
  2008 – 2010
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Nara Institute of Science and Technology
Software-Based Self-Test for Processors to guarantee high fault efficiency for structured faults
- Principal Investigator
  
  INOUE Michiko
- Project Period (FY)
  2006 – 2008
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system/Network
- Research Institution
  Nara Institute of Science and Technology
Research on Design for Testability for Multi-Clock Domain SoCsPrincipal Investigator
- Principal Investigator
  
  YONEDA Tomokazu
- Project Period (FY)
  2006 – 2008
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Nara Institute of Science and Technology
BASIC STUDIES ON TEST ARCHITECTURE AND DESIGN FOR TESTABILITY FOR SYSTEM-ON-CHIP
- Principal Investigator
  
  FUJIWARA Hideo
- Project Period (FY)
  2003 – 2006
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  NARA INSTITUTE OF SCIENCE AND TECHNOLOGY
低消費電力性とテスト容易性をともに考慮したVLSI高位設計
- Principal Investigator
  
  INOUE Michiko
- Project Period (FY)
  2002 – 2004
- Research Category
  
  Grant-in-Aid for Exploratory Research
- Research Field
  
  計算機科学
- Research Institution
  Nara Institute of Science and Technology

All 2016 2015 2014 2013 2011 2010 2009 2008 2007 2006 2005 2004 Other

All Journal Article Presentation

[Journal Article] Design and Optimization of Transparency-Based TAM for SoC Test2010
- Author(s)
  Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara
- Journal Title
  
  IEICE Trans. on Inf. and Syst. Vol.E93-D, No.6
  
  Pages: 1549-1559
- NAID
  10027987897
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300018
[Journal Article] Design and Optimization of Transparency-Based TAM for SoC Test2010
- Author(s)
  Tomokazu Yoneda
- Journal Title
  
  IEICE Trans.on Inf.and Syst.
  
  Volume: E93-D Pages: 1549-1559
- NAID
  10027987897
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300018
[Journal Article] Effective Domain Partitioning for Multi-clock Domain IP Core Wrapper Design Under Power Constraints2008
- Author(s)
  T.E. Yu, T. Yoneda, D. Zhao, H. Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems Vol. E91-D, No. 3
  
  Pages: 807-814
- NAID
  10026802270
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18700046
[Journal Article] NoC-compatible Wrapper Design and Optimization Under Channel Bandwidth and Test Time Constraints2008
- Author(s)
  Fawnizu Azmadi Hussin, Tomokazu Yoneda, and Hideo Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems Vol.E91-D, No.7
  
  Pages: 2008-2017
- NAID
  10026805045
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18700046
[Journal Article] On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time2008
- Author(s)
  F.A. Hussin, T. Yoneda, H. Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems (To appear)
- NAID
  10026805015
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18700046
[Journal Article] A Non-Scan Design-for-Testability for Register-Transfer Level Circuits to Guarantee Linear-Depth Time Expansion Models2008
- Author(s)
  Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi
- Journal Title
  
  IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems Vol.27, No.9
  
  Pages: 1535-1544
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300018
[Journal Article] Test Scheduling for Multi-Clock Domain SoCs under Power Constraint2008
- Author(s)
  T. Yoneda, K. Masuda, H. Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems Vol. E91-D, No. 3
  
  Pages: 747-755
- NAID
  10026802150
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18700046
[Journal Article] Test Scheduling for Multi-Clock Domain SoCs under Power Constraint2008
- Author(s)
  Tomokazu Yoneda, Kimihiko Masuda and Hideo Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems Vol.E91-D, No.3
  
  Pages: 747-755
- NAID
  10026802150
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18700046
[Journal Article] On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time2008
- Author(s)
  Fawnizu Azmadi Hussin, Tomokazu Yoneda, and Hideo Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems Vol.E91-D, No.7
  
  Pages: 1999-2007
- NAID
  10026805015
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18700046
[Journal Article] NoC-compatible Wrapper Design and Optimization Under Channel Bandwidth and Test Time Constraints2008
- Author(s)
  Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems Vol.E91-D, No.7
  
  Pages: 2008-2017
- NAID
  10026805045
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300018
[Journal Article] Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips2008
- Author(s)
  Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty and Hideo Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems Vol.E91-D, No.10
  
  Pages: 2440-2448
- NAID
  10026805953
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18700046
[Journal Article] On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time2008
- Author(s)
  Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems Vol.E91-D, No.7
  
  Pages: 1999-2007
- NAID
  10026805015
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300018
[Journal Article] Effective Domain Partitioning for Multi-clock Domain IP Core Wrapper Design Under Power Constraints2008
- Author(s)
  Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao and Hideo Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems Vol.E91-D, No.3
  
  Pages: 807-814
- NAID
  10026802270
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18700046
[Journal Article] Scheduling power-constrained tests through the soc functional bus2008
- Author(s)
  Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu and Hideo Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems Vol.E91-D, No.3
  
  Pages: 736-746
- NAID
  10026802124
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18700046
[Journal Article] Scheduling power constrained tests through the soc functional bus2008
- Author(s)
  F.A. Hussin, T. Yoneda, A. Orailoglu, H. Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems Vol. E91-D, No. 3
  
  Pages: 736-746
- NAID
  10026802124
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18700046
[Journal Article] Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips2008
- Author(s)
  Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems Vol.E91-D, No.10
  
  Pages: 2440-2448
- NAID
  10026805953
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300018
[Journal Article] NoC-compatible Wrapper Design and Optimization Under Channel Bandwidth and Test Time Constraints2008
- Author(s)
  F.A. Hussin. T. Yoneda, H. Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems (To appear)
- NAID
  10026805045
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18700046
[Journal Article] Power-aware multi-frequency heterogeneous soc test framework design with floor-ceiling packing2007
- Author(s)
  D.Zhao, R.Huang, T.Yoneda, H.Fujiwara
- Journal Title
  
  Proceedings of the 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007) (To appear)
- Data Source
  KAKENHI-PROJECT-18700046
[Journal Article] Core-based testing of multiprocessor system-on-chips utilizing hierarchical functional buses2007
- Author(s)
  F.A.Hussin, T.Yoneda, A.Orailoglu, H.Fujiwara
- Journal Title
  
  Proceedings of the 12th Asia and South Pacific Design Automation Conference 2007 (ASP-DAC'07)
  
  Pages: 720-725
- Data Source
  KAKENHI-PROJECT-18700046
[Journal Article] NoC wrapper optimization under channel bandwidth and test time constraints2007
- Author(s)
  F.A.Hussin, T.Yoneda, H.Fujiwara
- Journal Title
  
  Technical Report of IEICE (DC2006-80) Vol. 106, No. 528
  
  Pages: 1-6
- NAID
  110006224499
- Data Source
  KAKENHI-PROJECT-18700046
[Journal Article] An soc test scheduling algorithm using reconfigurable union wrappers2007
- Author(s)
  T.Yoneda, M.Imanishi, H.Fujiwara
- Journal Title
  
  Proceedings of the Design, Automation and Test in Europe (DATE' 07)
  
  Pages: 231-236
- Data Source
  KAKENHI-PROJECT-18700046
[Journal Article] Optimization of noc wrapper design under bandwidth and test time constraints2007
- Author(s)
  F.A.Hussin, T.Yoneda, H.Fujiwara
- Journal Title
  
  Proceedings of the The IEEE European Test Symposium 2007 (To appear)
- Data Source
  KAKENHI-PROJECT-18700046
[Journal Article] TAM design and optimization for transparency-based soc test2007
- Author(s)
  T.Yoneda, A.Shuto, H.Ichihara, T.Inoue, H.Fujiwara
- Journal Title
  
  Proceedings of the IEEE 25th VLSI Test Symposium (VTS'07) (To appear)
- Data Source
  KAKENHI-PROJECT-18700046
[Journal Article] Using domain partitioning in wrapper design for IP cores under power constraints2007
- Author(s)
  T.E.Yu, T.Yoneda, D.Zhao, H.Fujiwara
- Journal Title
  
  Proceedings of the IEEE 25th VLSI Test Symposium (VTS'07) (To appear)
- Data Source
  KAKENHI-PROJECT-18700046
[Journal Article] Designing power-aware wrapper for multi-clock domain cores using clock domain partitioning2006
- Author(s)
  T.E.Yu, T.Yoneda, D.Zhao, H.Fujiwara
- Journal Title
  
  Digest of Papers, IEEE 7th Workshop on RTL and High Level Testing (WRTLT'06)
  
  Pages: 43-48
- Data Source
  KAKENHI-PROJECT-18700046
[Journal Article] A Memory Grouping Method for reducing Memory BIST Logic of System-on-Chips2006
- Author(s)
  Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems Vol.E89-D, No.4
  
  Pages: 1490-1497
- NAID
  110007504501
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] Power-conscious microprocessor-based testing of system-on-chip2006
- Author(s)
  F.A.Hussin, T.Yoneda, A.Orailoglu, H.Fujiwara
- Journal Title
  
  Technical Report of IEICE (VLD2006-6) Vol. 106, No. 32
  
  Pages: 25-30
- NAID
  110004821860
- Data Source
  KAKENHI-PROJECT-18700046
[Journal Article] メモリコアに対する組込み自己修復を考慮したSoCのテストスケジューリング2006
- Author(s)
  福田雄介, 米田友和, 藤原秀雄
- Journal Title
  
  信学技報(DC2006-48) Vol. 106, No. 387
  
  Pages: 59-64
- NAID
  110005717338
- Data Source
  KAKENHI-PROJECT-18700046
[Journal Article] Power-constrained SOC test schedules through utilization of functional buses2006
- Author(s)
  F.A.Hussin, T.Yoneda, A.Orailoglu, H.Fujiwara
- Journal Title
  
  Proceedings of the 24th IEEE International Conference on Computer Design (ICCD'06)
  
  Pages: 230-236
- Data Source
  KAKENHI-PROJECT-18700046
[Journal Article] A DET Method Based on Partially Strong Testability of RTL Data Paths to Guarantee Complete Fault Efficiency2006
- Author(s)
  Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara
- Journal Title
  
  Trans. of IEICE (DI) Vol.J89-D, No.8
  
  Pages: 1643-1653
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] An optimal test bus design for transparency-based soc test2006
- Author(s)
  T.Yoneda, A.Shuto, H.Ichihara, T.Inoue, H.Fujiwara
- Journal Title
  
  Digest of Papers, IEEE 7th Workshop on RTL and High Level Testing (WRTLT'06)
  
  Pages: 21-26
- Data Source
  KAKENHI-PROJECT-18700046
[Journal Article] 消費電力を考慮したマルチクロッグドメインSoCのテストスケジューリング2005
- Author(s)
  増田公彦, 米田友和, 藤原秀雄
- Journal Title
  
  信学技報(DC2004-103) Vol.104, No.664
  
  Pages: 69-74
- Data Source
  KAKENHI-PROJECT-14658092
[Journal Article] レジスタ転送レベル回路に対する連続透明化設計法2004
- Author(s)
  米田友和
- Journal Title
  
  電子情報通信学会論文誌(DI) Vol.J87-D-I, No.12
  
  Pages: 1110-1118
- NAID
  110003203297
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] Design for consecutive transparency method of RTL circuits2004
- Author(s)
  Tomokazu Yoneda, Hideo Fujiwara
- Journal Title
  
  Trans. of IEICE (DI) (in Japanese) Vol.J87-D-I, No.12
  
  Pages: 1110-1118
- NAID
  110003203297
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] レジスタ転送レベル回路に対する連続透明化設計法2004
- Author(s)
  米田友和
- Journal Title
  
  電子情報通信学会論文誌(DI) J87-D-I, 12
  
  Pages: 1110-1118
- NAID
  110003203297
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Presentation] ゼロ遅延論理シミュレーションに基づく遅延故障インジェクション環境2016
- Author(s)
  川崎真司, 米田友和, 大和勇太, 井上美智子
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  機械振興会館（東京都港区）
- Year and Date
  2016-02-17
- Data Source
  KAKENHI-PROJECT-25280015
[Presentation] 重み付きランダムパターンとリシードを組み合わせた組込み自己テスト手法2016
- Author(s)
  里中沙矢香, 米田友和, 大和勇太, 井上美智子
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  機械振興会館（東京都港区）
- Year and Date
  2016-02-17
- Data Source
  KAKENHI-PROJECT-25280015
[Presentation] Reliability enhancement of embedded memory with combination of aging-aware adaptive in-field self-repair and ECC2016
- Author(s)
  Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato and Michiko Inoue
- Organizer
  the 21st IEEE European Test Symposium
- Place of Presentation
  Amsterdam, The Netherlands
- Year and Date
  2016-05-24
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280015
[Presentation] An ECC-Based memory architecture with online self-repair capabilities for reliability enhancement2015
- Author(s)
  Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato and Michiko Inoue
- Organizer
  the 20th IEEE European Test Symposium
- Place of Presentation
  Cluj-Napoca, Romania
- Year and Date
  2015-05-25
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280015
[Presentation] メモリの隣接パタン依存故障テストに対するバックグラウンド列の生成2015
- Author(s)
  上岡真也, 米田友和, 大和勇太, 井上美智子
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  福江文化会館（長崎県五島市）
- Year and Date
  2015-12-01
- Data Source
  KAKENHI-PROJECT-25280015
[Presentation] Reliability of ECC-based memory architectures with online self-repair capabilities2014
- Author(s)
  Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato and Michiko Inoue
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  高岡テクノドーム（富山県高岡市）
- Year and Date
  2014-12-19
- Data Source
  KAKENHI-PROJECT-25280015
[Presentation] Memory block based scan-BIST architecture for application-dependent FPGA testing2014
- Author(s)
  Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama, Michiko Inoue
- Organizer
  ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
- Place of Presentation
  Monterey, California, USA
- Data Source
  KAKENHI-PROJECT-25280015
[Presentation] Efficient scan-based BIST architecture for application-dependent FPGA test2013
- Author(s)
  Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama, Michiko Inoue
- Organizer
  The Forteenth Workshop on RTL and High Level Testing
- Place of Presentation
  台湾・宜蘭
- Data Source
  KAKENHI-PROJECT-25280015
[Presentation] FPGA向けアプリケーション依存テストのための効率的なスキャンBISTアーキテクチャ2013
- Author(s)
  伊藤渓太, 米田友和, 大和勇太, 畠山一実, 井上美智子
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  石川県七尾市
- Data Source
  KAKENHI-PROJECT-25280015
[Presentation] Faster-Than-At-Speed Test for Increased Test Quality and In-Field Reliability2011
- Author(s)
  Tomokazu Yoneda, Keigo Hori, Michiko Inoue and Hideo Fujiwara
- Organizer
  IEEE International Test Conference(ITC' 11)
- Place of Presentation
  アメリカアナハイム
- Year and Date
  2011-09-20
- Data Source
  KAKENHI-PROJECT-21700059
[Presentation] Faster-Than-At-Speed Test for Increased Test Quality and In-Field Reliability2011
- Author(s)
  Tomokazu Yoneda
- Organizer
  IEEE International Test Conference
- Place of Presentation
  アメリカアナハイム
- Year and Date
  2011-09-20
- Data Source
  KAKENHI-PROJECT-21700059
[Presentation] Temperature-variation-aware test pattern optimization2011
- Author(s)
  Tomokazu Yonedaノルウェートロンハイム., Makoto Nakao, Michiko Inoue, Yasuo Sato and Hideo Fujiwara
- Organizer
  IEEE European Test Symposium(ETS' 11)
- Place of Presentation
  ノルウェートロンハイム
- Year and Date
  2011-05-25
- Data Source
  KAKENHI-PROJECT-21700059
[Presentation] A Test Pattern Optimization to Reduce Spatial and Temporal Temperature Variations2011
- Author(s)
  Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato and Hideo Fujiwara
- Organizer
  IEEE International Workshop on Reliability Aware System Design and Test(RASDAT' 11)
- Place of Presentation
  インドチェンナイ
- Year and Date
  2011-01-06
- Data Source
  KAKENHI-PROJECT-21700059
[Presentation] Temperature-Variation-Aware Test Pattern Optimization2011
- Author(s)
  Tomokazu Yoneda
- Organizer
  IEEE European Test Symposium
- Place of Presentation
  ノルウェートロンハイム
- Year and Date
  2011-05-25
- Data Source
  KAKENHI-PROJECT-21700059
[Presentation] Aging Test Strategy and Adaptive Test Scheduling for SoC Failure Prediction2010
- Author(s)
  Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara
- Organizer
  IEEE International On-Line Testing Symposium
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Test Pattern Selection to Optimize Delay Test Quality with a Limited Size of Test Set2010
- Author(s)
  Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata, Hideo Fujiwara
- Organizer
  2010 IEEE European Test Symposium
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Seed ordering and selection for high quality delay test2010
- Author(s)
  Tomokazu Yoneda, Michiko Inoue, Akira Taketani and Hideo Fujiwara
- Organizer
  IEEE 19th Asian Test Symposium(ATS2010)
- Place of Presentation
  中国上海
- Year and Date
  2010-12-04
- Data Source
  KAKENHI-PROJECT-21700059
[Presentation] Thermal-Uniformity Aware X-Filling to Reduce Temperature-Induced Delay Variation for Accurate At-Speed Testing2010
- Author(s)
  Tomokazu Yoneda
- Organizer
  IEEE VLSI Test Symposium
- Place of Presentation
  アメリカサンタクルーズ
- Year and Date
  2010-04-20
- Data Source
  KAKENHI-PROJECT-21700059
[Presentation] Seed Ordering and Selection for High Quality Delay Test2010
- Author(s)
  Tomokazu Yoneda, Michiko Inoue, Akira Taketani, Hideo Fujiwara
- Organizer
  Proc. of IEEE the 19th Asian Test Symposium
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Seed Ordering and Selection for High Quality Delay Test2010
- Author(s)
  Tomokazu Yoneda
- Organizer
  IEEE Asian Test Symposium
- Place of Presentation
  中国上海
- Year and Date
  2010-12-04
- Data Source
  KAKENHI-PROJECT-21700059
[Presentation] Thermal-uniformity aware x-filling to reduce temperature-induced delay variation for accurate at-speed testing2010
- Author(s)
  Tomokazu Yoneda, Michiko Inoue, Yasuo Sato and Hideo Fujiwara
- Organizer
  28th IEEE VLSI Test Symposium(VTS' 10)
- Place of Presentation
  アメリカサンタクルーズ
- Year and Date
  2010-04-20
- Data Source
  KAKENHI-PROJECT-21700059
[Presentation] RedSOCs-3D : Thermal-safe Test Scheduling for 3D-Stacked SoC2010
- Author(s)
  Fawnizu Azmadi Hussin, Thomas Edison Chua Yu, Tomokazu Yoneda and Hideo Fujiwara
- Organizer
  IEEE Asia Pacific Conference on Circuits and Systems(APCCAS2010)
- Place of Presentation
  マレーシアクアラルンプール
- Year and Date
  2010-12-07
- Data Source
  KAKENHI-PROJECT-21700059
[Presentation] Thermal-Uniformity-Aware X-Filling to Reduce Temperature-Induced Delay Variation for Accurate At-Speed Testing2010
- Author(s)
  Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Hideo Fujiwara
- Organizer
  28th IEEE VLSI Test Symposium
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Optimizing Delay Test Quality with a Limited Size of Test Set2010
- Author(s)
  Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata and Hideo Fujiwara
- Organizer
  IEEE European Test Symposium(ETS' 10)
- Place of Presentation
  チェコプラハ
- Year and Date
  2010-05-27
- Data Source
  KAKENHI-PROJECT-21700059
[Presentation] RedSOCs-3D : Thermal-safe Test Scheduling for 3D-Stacked SoC2010
- Author(s)
  Fawnizu Azmadi Hussin, Thomas Edison Chua Yu, Tomokazu Yoneda, Hideo Fujiwara
- Organizer
  2010 Asia Pacific Conference on Circuits and Systems
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Thermal-Uniformity-Aware X-Filling to Reduce Temperature-Induced Delay Variation for Accurate At-Speed Testing2010
- Author(s)
  Tomokazu Yoneda
- Organizer
  28th IEEE VLSI Test Symposium
- Place of Presentation
  Santa Cruz, USA
- Year and Date
  2010-04-19
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Seed Ordering and Selection for High Quality Delay Test2010
- Author(s)
  Tomokazu Yoneda
- Organizer
  IEEE the 19th Asian Test Symposium
- Place of Presentation
  上海、中国
- Year and Date
  2010-12-02
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Optimizing Delay Test Quality with a Limited Size of Test Set2010
- Author(s)
  Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata and Hideo Fujiwara
- Organizer
  IEEE International Workshop on Reliability Aware System Design and Test(RASDAT' 10)
- Place of Presentation
  インドバンガロール
- Year and Date
  2010-01-08
- Data Source
  KAKENHI-PROJECT-21700059
[Presentation] Partial scan approach for secret information protection2009
- Author(s)
  Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa and Hideo Fujiwara
- Organizer
  Proceedings of the 14th IEEE European Test Symposium(ETS'09)
- Data Source
  KAKENHI-PROJECT-18500038
[Presentation] Test Infrastructure Design for Core-Based System-on-Chip Under Cycle-Accurate Thermal Constraints2009
- Author(s)
  Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty and Hideo Fujiwara
- Organizer
  14th Asia and South Pacific Design Automation Conference (ASP-DAC2009)
- Data Source
  KAKENHI-PROJECT-18700046
[Presentation] Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints2009
- Author(s)
  T. E. Yu, T. Yoneda, K. Chakrabarty and H. Fuiiwara
- Organizer
  14th Asia and South Pacific Design Automation Conference 2009 (ASP-DAC'09)
- Place of Presentation
  横浜、神奈川
- Year and Date
  2009-01-22
- Data Source
  KAKENHI-PROJECT-18700046
[Presentation] Partial Scan Approach for Secret Information Protection2009
- Author(s)
  Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara
- Organizer
  2009 IEEE European Test Symposium
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Test Infrastructure Design for Core-Based System-on-Chip Under Cycle-Accurate Thermal Constraints2009
- Author(s)
  Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara
- Organizer
  14th Asia and South Pacific Design Automation Conference
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] マルチクロック・ドメイン・コアテストのための再構成可能ラッパーの一構成法2008
- Author(s)
  吉田宜司, 米田友和, 藤原秀雄
- Organizer
  デザインガイア2008(ディペンダブルコンピューティング研究会)
- Place of Presentation
  北九州学術研究都市、福岡
- Year and Date
  2008-11-18
- Data Source
  KAKENHI-PROJECT-18700046
[Presentation] Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-Cycle Paths2008
- Author(s)
  Thomas Edison Yu, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara
- Organizer
  Proc. of IEEE the 17th Asian Test Symposium
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Wrapper and TAM co-optimization for reuse of soc functional interconnects2008
- Author(s)
  Tomokazu Yoneda and Hideo Fujiwara
- Organizer
  Design, Automation and Test in Europe (DATE'08)
- Data Source
  KAKENHI-PROJECT-18700046
[Presentation] Wrapper and TAM co-optimization for reuse of soc functional interconnects2008
- Author(s)
  T. Yoneda, H. Fujiwara
- Organizer
  Design, Automation and Test in Europe (DATE'08)
- Place of Presentation
  Munich, Germany
- Data Source
  KAKENHI-PROJECT-18700046
[Presentation] A reconfigurable wrapper design for multi-dock domain cores2008
- Author(s)
  T. Yoshida, T. Yoneda and H. Fujiwara
- Organizer
  9th IEEE Workshop on RTL and High Level Testing (WRTLT'08)
- Place of Presentation
  札幌、北海道
- Year and Date
  2008-11-27
- Data Source
  KAKENHI-PROJECT-18700046
[Presentation] An SoC Test Scheduling Algorithm using Reconfigurable Union Wrappers2007
- Author(s)
  T. Yoneda, M. Imanishi, H. Fujiwara
- Organizer
  Design, Automation and Test in Europe (DATE'07)
- Place of Presentation
  Nice, France
- Data Source
  KAKENHI-PROJECT-18700046
[Presentation] Test scheduling for memory cores with built-in self-repair2007
- Author(s)
  Tomokazu Yoneda, Yusuke Fukuda and Hideo Fujiwara
- Organizer
  IEEE 16th Asian Test Symposium (ATS'07)
- Data Source
  KAKENHI-PROJECT-18700046
[Presentation] Optimization of noc wrapper design under bandwidth and test time constraints2007
- Author(s)
  Fawnizu Azmadi Hussin, Tomokazu Yoneda and Hideo Fujiwara
- Organizer
  The IEEE European Test Symposium 2007 (ETS'07)
- Data Source
  KAKENHI-PROJECT-18700046
[Presentation] An SoC Test Scheduling Algorithm using Reconfigurable Union Wrappers2007
- Author(s)
  Tomokazu Yoneda, Masahiro Imanishi and Hideo Fujiwara
- Organizer
  Design, Automation and Test in Europe (DATE'07)
- Data Source
  KAKENHI-PROJECT-18700046
[Presentation] Test scheduling for memory cores with built-in self-repair2007
- Author(s)
  T. Yoneda, Y. Fukuda, H. Fujiwara
- Organizer
  IEEE 16th Asian Test Symposium (ATS'07)
- Place of Presentation
  Beijing, China
- Data Source
  KAKENHI-PROJECT-18700046
[Presentation] Using domain partitoning in wrapper design for IP cores under power constraints2007
- Author(s)
  T.E. Yu, T. Yoneda, D. Zhao, H. Fujiwara
- Organizer
  IEEE 25th VLSI Test Symposium (VTS'07)
- Place of Presentation
  Berkekey, USA
- Data Source
  KAKENHI-PROJECT-18700046
[Presentation] Area overhead and test time co-optimization through noc bandwidth sharing2007
- Author(s)
  F.A. Hussin, T. Yoneda, H. Fujiwara
- Organizer
  IEEE 16th Asian Test Symopsium (ATS'07)
- Place of Presentation
  Beijing, China
- Data Source
  KAKENHI-PROJECT-18700046
[Presentation] Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses2007
- Author(s)
  Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, and Hideo Fujiwara
- Organizer
  12th Asia and South Pacific Design Automation Conference 2007 (ASP-DAC'07)
- Data Source
  KAKENHI-PROJECT-18700046
[Presentation] TAM design and optimization for transparency-based soc test2007
- Author(s)
  T. Yoneda, A. Shuto, H. Ichihara, T. Inoue, H. Fujiwara
- Organizer
  IEEE 25th VLSI Test Symposium (VTS'07)
- Place of Presentation
  Berkekey, USA
- Data Source
  KAKENHI-PROJECT-18700046
[Presentation] Area overhead and test time co-optimization through noc bandwidth sharing2007
- Author(s)
  Fawnizu Azmadi Hussin, Tomokazu Yoneda and Hideo Fujiwara
- Organizer
  IEEE 16th Asian Test Symposium (ATS'07)
- Data Source
  KAKENHI-PROJECT-18700046
[Presentation] Thermal-safe test access mechanism and wrapper co-optimization for system-on-chip2007
- Author(s)
  Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty and Hideo Fujiwara
- Organizer
  IEEE 16th Asian Test Symposium (ATS'07)
- Data Source
  KAKENHI-PROJECT-18700046
[Presentation] Power-aware multi-frequency heterogeneous SoC test framework design with floor-ceiling packing2007
- Author(s)
  Danella Zhao, Ronghua Huang, Tomokazu Yoneda, and Hideo Fujiwara
- Organizer
  2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007)
- Data Source
  KAKENHI-PROJECT-18700046
[Presentation] TAM design and optimization for transparency-based soc test2007
- Author(s)
  Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue and Hideo Fujiwara
- Organizer
  IEEE 25th VLSI Test Symposium (VTS'07)
- Data Source
  KAKENHI-PROJECT-18700046
[Presentation] Optimization of noc wrapper design under bandwidth and test time constraints2007
- Author(s)
  F.A. Hussin, T. Yoneda, H. Fujiwara
- Organizer
  The IEEE European Test Symopsium 2007 (ETS'07)
- Place of Presentation
  Freiburg, Germany
- Data Source
  KAKENHI-PROJECT-18700046
[Presentation] Poweraware multi-frequency heterogeneous SoC test framework designwith floor-ceiling packing2007
- Author(s)
  D. Zhao, R. Huang, T. Yoneda, H. Fujiwara
- Organizer
  2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007)
- Place of Presentation
  New Orleans, USA
- Data Source
  KAKENHI-PROJECT-18700046
[Presentation] Using domain partitioning in wrapper design for IP cores under power constraints2007
- Author(s)
  Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao and Hideo Fujiwara
- Organizer
  IEEE 25th VLSI Test Symposium (VTS'07)
- Data Source
  KAKENHI-PROJECT-18700046
[Presentation] Power-constrained SOC test schedules through utilization of functional buses2006
- Author(s)
  Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu and Hideo Fujiwara
- Organizer
  24th IEEE International Conference on Computer Design (ICCD'06)
- Data Source
  KAKENHI-PROJECT-18700046
[Presentation] An online repair strategy and reliability for ECC-Based memory architectures
- Author(s)
  Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato and Michiko Inoue
- Organizer
  IEEE Workshop on RTL and High Level Testing
- Place of Presentation
  Hangzhou, China
- Year and Date
  2014-11-19 – 2014-11-20
- Data Source
  KAKENHI-PROJECT-25280015
[Presentation] Parallel path delay fault simulation for multi/many-core processors with SIMD units
- Author(s)
  Yussuf Ali, Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue
- Organizer
  IEEE Asian Test Symposium
- Place of Presentation
  Hangzhou, China
- Year and Date
  2014-11-16 – 2014-11-19
- Data Source
  KAKENHI-PROJECT-25280015
[Presentation] An ECC-Based memory architecture with online self-repair capabilities for reliability enhancement
- Author(s)
  Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato and Michiko Inoue
- Organizer
  IEEE European Test Symposium
- Place of Presentation
  Cluj-Napoca, Romania
- Year and Date
  2015-05-25 – 2015-05-29
- Data Source
  KAKENHI-PROJECT-25280015

1. INOUE Michiko (30273840)

# of Collaborated Projects: 5 results

# of Collaborated Products: 19 results
2. OHTAKE Satoshi (20314528)

# of Collaborated Projects: 4 results

# of Collaborated Products: 2 results
3. FUJIWARA Hideo (70029346)

# of Collaborated Projects: 2 results

# of Collaborated Products: 16 results
4. YAMATO Yuta (20707244)

# of Collaborated Projects: 1 results

# of Collaborated Products: 12 results

YONEDA Tomokazu 米田 友和

Research Projects

Research Products

Co-Researchers

Research on Built-in Self-Test to Enhance LSI Reliability through its Lifecycle

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Research on Test Methodology for 3D Integrated SoCsPrincipal Investigator

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Basic Studies on Testability and Security for Network-on-Chip

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Software-Based Self-Test for Processors to guarantee high fault efficiency for structured faults

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Research on Design for Testability for Multi-Clock Domain SoCsPrincipal Investigator

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BASIC STUDIES ON TEST ARCHITECTURE AND DESIGN FOR TESTABILITY FOR SYSTEM-ON-CHIP

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低消費電力性とテスト容易性をともに考慮したVLSI高位設計

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[Journal Article] Design and Optimization of Transparency-Based TAM for SoC Test2010

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NAID

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[Journal Article] Design and Optimization of Transparency-Based TAM for SoC Test2010

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NAID

Data Source

[Journal Article] Effective Domain Partitioning for Multi-clock Domain IP Core Wrapper Design Under Power Constraints2008

Author(s)

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NAID

Data Source

[Journal Article] NoC-compatible Wrapper Design and Optimization Under Channel Bandwidth and Test Time Constraints2008

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NAID

Data Source

[Journal Article] On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time2008

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NAID

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[Journal Article] A Non-Scan Design-for-Testability for Register-Transfer Level Circuits to Guarantee Linear-Depth Time Expansion Models2008

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[Journal Article] Test Scheduling for Multi-Clock Domain SoCs under Power Constraint2008

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NAID

Data Source

YONEDA Tomokazu 米田友和