Nakahara Hiroki 中原啓貴

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NAKAHARA Hiroki 中原啓貴

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Researcher Number	20624414
Other IDs
Affiliation (Current)	2025: 東北大学, 未踏スケールデータアナリティクスセンター, 教授
Affiliation (based on the past Project Information) *help	2023 – 2024: 東北大学, 未踏スケールデータアナリティクスセンター, 教授 2016 – 2022: 東京工業大学, 工学院, 准教授 2014 – 2015: 愛媛大学, 理工学研究科, 講師 2012 – 2013: 鹿児島大学, 理工学研究科, 助教
Review Section/Research Field	Principal Investigator Basic Section 60040:Computer system-related / Sections That Are Subject to Joint Review: Basic Section60040:Computer system-related , Basic Section60090:High performance computing-related / Basic Section 60090:High performance computing-related / Computer system / Computer system/Network
Keywords	Principal Investigator FPGA / Machine Learning / AI / 計算機システム / 深層学習 / CNN / Deep Learning / 組込みシステム / Transformer / Noise Convolution … More / 高性能計算 / 画像圧縮 / LSI / ノイズCNN / 雑音畳み込み / ニューラルネットワーク / Machine learning / DSP / Signal Processing / 再構成可能LSI / 信号処理 / 分光器 / 電波天文 / RNS / FFT / Spectrometer / Digital Signal / Radio Telescope / プロセッサ / 多値決定グラフ / コンパイラ / 組込みプロセッサ / 決定グラフ / パケット分類 / 組み込みシステム / CPU / MDD / BDD / Processor / Multi-valued Logic / Decision Diagram Less

Development of a Binary Vision Transformer HardwarePrincipal Investigator
- Principal Investigator
  
  中原啓貴
- Project Period (FY)
  2024 – 2028
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Review Section
  
  Basic Section 60040:Computer system-related
  Basic Section 60090:High performance computing-related
  Sections That Are Subject to Joint Review: Basic Section60040:Computer system-related , Basic Section60090:High performance computing-related
- Research Institution
  Tohoku University
On a noise convolutional neural networkPrincipal Investigator
- Principal Investigator
  
  Nakahara Hiroki
- Project Period (FY)
  2019 – 2023
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Tohoku University
  Tokyo Institute of Technology
Development of Next Generation Spectrometer for Radio TelescopePrincipal Investigator
- Principal Investigator
  
  NAKAHARA HIROKI
- Project Period (FY)
  2015 – 2018
- Research Category
  
  Grant-in-Aid for Young Scientists (A)
- Research Field
  
  Computer system
- Research Institution
  Tokyo Institute of Technology
  Ehime University
A general purpose processor based on a multi-valued decision diagramPrincipal Investigator
- Principal Investigator
  
  NAKAHARA Hiroki
- Project Period (FY)
  2012 – 2014
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Ehime University
  Kagoshima University

All 2023 2022 2021 2020 2019 2018 2017 2016 2015 2014 2013 2012 Other

All Journal Article Presentation

[Journal Article] Remarn: A Reconfigurable Multi-threaded Multi-core Accelerator for Recurrent Neural Networks2023
- Author(s)
  Zhiqiang Que, Hiroki Nakahara, Hongxiang Fan, He Li, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Eriko Nurvitadhi, Wayne Luk:
- Journal Title
  
  ACM Trans. Reconfigurable Technol.
  
  Volume: 16 Pages: 1-26
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19H04078
[Journal Article] Optimizations of Ternary Generative Adversarial Networks2022
- Author(s)
  Kennichi Nakamura, Hiroki Nakahara
- Journal Title
  
  IEEE Int. Symp. on Multi-valued Logic (ISMVL)
  
  Pages: 158-163
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19H04078
[Journal Article] Multilayer Perceptron Training Accelerator Using Systolic Array2022
- Author(s)
  Takeshi Senoo, Akira Jinguji, Ryosuke Kuramochi, Hiroki Nakahara
- Journal Title
  
  EICE Trans. Inf. Syst.
  
  Volume: 105-D(12) Pages: 2048-2056
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19H04078
[Journal Article] Recurrent Neural Networks With Column-Wise Matrix-Vector Multiplication on FPGAs2022
- Author(s)
  Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Andrew Boutros, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Wayne Luk
- Journal Title
  
  IEEE Trans. Very Large Scale Integr. Syst.
  
  Volume: 30(2) Pages: 227-237
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19H04078
[Journal Article] Fast Interface with Ensemble Ternary Neural Network2022
- Author(s)
  Ryota Kayanoma, Hiroki Nakahara
- Journal Title
  
  IEEE Int. Symp. on Multi-valued Logic (ISMVL)
  
  Pages: 182-187
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19H04078
[Journal Article] FPGA-Based Inter-layer Pipelined Accelerators for Filter-Wise Weight-Balanced Sparse Fully Convolutional Networks with Overlapped Tiling2021
- Author(s)
  Masayuki Shimoda, Youki Sada, Hiroki Nakahara
- Journal Title
  
  J. Signal Process. Syst.
  
  Volume: 93(5) Pages: 499-512
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19H04078
[Journal Article] A Low-Latency Inference of Randomly Wired Convolutional Neural Networks on an FPGA2021
- Author(s)
  Ryosuke Kuramochi, Hiroki Nakahara
- Journal Title
  
  IEICE Trans. Inf. Syst.
  
  Volume: 104-D(12) Pages: 2068-2077
- NAID
  130008123389
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19H04078
[Journal Article] Weight Sparseness for a Feature-Map-Split-CNN Toward Low-Cost Embedded FPGAs2021
- Author(s)
  Akira Jinguji, Shimpei Sato, Hiroki Nakahara
- Journal Title
  
  IEICE Trans. Inf. Syst.
  
  Volume: 104-D(12) Pages: 2040-2047
- NAID
  130008123390
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19H04078
[Journal Article] Energy-Efficient ECG Signals Outlier Detection Hardware Using a Sparse Robust Deep Autoencoder2021
- Author(s)
  Naoto Soga, Shimpei Sato, Hiroki Nakahara
- Journal Title
  
  IEICE Trans. Inf. Syst
  
  Volume: 104-D(8) Pages: 1121-1129
- NAID
  130008070358
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19H04078
[Journal Article] SENTEI: Filter-Wise Pruning with Distillation towards Efficient Sparse Convolutional Neural Network Accelerators2020
- Author(s)
  Masayuki Shimoda, Youki Sada, Ryosuke Kuramochi, Shimpei Sato, Hiroki Nakahara
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: E103.D Issue: 12 Pages: 2463-2470
- DOI
  10.1587/transinf.2020PAP0013
- NAID
  130007948567
- ISSN
  0916-8532, 1745-1361
- Year and Date
  2020-12-01
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19H04078
[Journal Article] GUINNESS: A GUI Based Binarized Deep Neural Network Framework for Software Programmers2019
- Author(s)
  Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Shimpei Sato
- Journal Title
  
  IEICE Trans. Inf. Syst.
  
  Volume: 102-D(5) Pages: 1003-1011
- NAID
  130007641155
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19H04078
[Journal Article] Power Efficient Object Detector with an Event-Driven Camera for Moving Object Surveillance on an FPGA2019
- Author(s)
  Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
- Journal Title
  
  IEICE Trans. Inf. Syst.
  
  Volume: 102-D(5) Pages: 1020-1028
- NAID
  130007641234
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19H04078
[Journal Article] BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W2018
- Author(s)
  Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura
- Journal Title
  
  IEEE Journal of Solid-State Circuits
  
  Volume: 53(4) Pages: 983-994
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-15H05304
[Journal Article] A Threshold Neuron Pruning for a Binarized Deep Neural Network on an FPGA2018
- Author(s)
  Tomoya Fujii, Shimpei Sato, Hiroki Nakahara
- Journal Title
  
  IEICE Transactions
  
  Volume: 101-D(2) Pages: 376-386
- NAID
  130006328491
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-15H05304
[Journal Article] An FPGA Realization of a Random Forest with k-Means Clustering Using a High-Level Synthesis Design2018
- Author(s)
  Akira Jinguji, Shimpei Sato, Hiroki Nakahara
- Journal Title
  
  IEICE Transactions
  
  Volume: 101-D(2) Pages: 354-362
- NAID
  130006328469
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-15H05304
[Journal Article] LUT cascades based on edge-valued multi-valued decision diagrams: Application to packet classification2016
- Author(s)
  H.　Nakahara, T.　Sasao, H.　Iwamoto, and M.　Matsuura
- Journal Title
  
  IEEE Journal on Emerging and Selected Topics in Circuits and Systems
  
  Volume: ６ Issue: 1 Pages: 73-86
- DOI
  10.1109/jetcas.2016.2528638
- Peer Reviewed / Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-26330072, KAKENHI-PROJECT-15H05304
[Journal Article] LUT Cascades Based on Edge-Valued Multi-Valued Decision Diagrams: Application to Packet Classification2016
- Author(s)
  Hiroki Nakahara, Tsutomu Sasao, Hisashi Iwamoto, Munehiro Matsuura
- Journal Title
  
  IEEE J. Emerg. Sel. Topics Circuits Syst.
  
  Volume: 6 Pages: 73-86
- Peer Reviewed / Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-15H05304
[Journal Article] An FFT Circuit for a Spectrometer of a Radio Telescope using the Nested RNS including the Constant Division2016
- Author(s)
  Hiroki Nakahara, Hiroyuki Nakanishi, Kazumasa Iwai, Tsutomu Sasao
- Journal Title
  
  SIGARCH Computer Architecture News
  
  Volume: 44 Pages: 44-49
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-15H05304
[Journal Article] An Update Method for a Low Power Cam Emulator Using an LUT Cascade Based on an EVMDD (k)2016
- Author(s)
  Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Hisashi Iwamoto
- Journal Title
  
  Multiple-Valued Logic and Soft Computing
  
  Volume: 26 Pages: 109-123
- Peer Reviewed / Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-15H05304
[Journal Article] A memory-based IPv6 lookup architecture using parallel index generation units2015
- Author(s)
  H. Nakahara, T. Sasao, M. Matsuura, H. Iwamoto, Y. Terao
- Journal Title
  
  IEICE Transactions on Information and Systems
  
  Volume: E98-D Pages: 262-271
- NAID
  130004841817
- Peer Reviewed / Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-24700050
[Journal Article] An Update Method for a Low Power CAM Emulator using an LUT Cascade Based on an EVMDD (k)2015
- Author(s)
  H. Nakahara, T. Sasao, M. Matsuura, and H. Iwamoto
- Journal Title
  
  Journal of Multiple-Valued Logic and Soft Computing
  
  Volume: 26 Pages: 109-123
- Peer Reviewed / Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-15H05304
[Journal Article] A packet classifier based on prefetching EVMDD(k) machines2014
- Author(s)
  H. Nakahara, T. Sasao, M. Matsuura
- Journal Title
  
  IEICE Transactions on Information and Systems
  
  Volume: E97-D Pages: 2243-2252
- NAID
  130004685470
- Peer Reviewed / Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-24700050
[Journal Article] A Heterogeneous Multi-valued Decision Diagram Machine for Encoded Characteristic Function for Non-zero Outputs2014
- Author(s)
  Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
- Journal Title
  
  J. of Multi.-Valued Logic & Soft Computing
  
  Volume: 1 Pages: 1-15
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-24700050
[Journal Article] A heterogeneous multi-valued decision diagram machine for encoded characteristic function for non-zero outputs2014
- Author(s)
  H. Nakahara, T. Sasao, M. Matsuura
- Journal Title
  
  Journal of Multiple-Valued Logic and Soft Computing
  
  Volume: ２３ Pages: 365-377
- Peer Reviewed / Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-24700050
[Journal Article] A Virus Scanning Engine Using an MPU and an IGU Based on Row-Shift Decomposition2013
- Author(s)
  Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
- Journal Title
  
  IEICE TRANS. INF. & SYST.
  
  Volume: E96-D Pages: 1667-1675
- NAID
  130003370948
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-24700050
[Journal Article] A Heterogeneous Multi-valuedDecision Diagram Machine for Encoded Characteristic Function for Non-zero Outputs2013
- Author(s)
  Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
- Journal Title
  
  Journal of Multiple-Valued Logic and Soft Computing
  
  Volume: 20
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-24700050
[Journal Article] A virus scanning engine using an MPU and an IGU based on row-shift decomposition2013
- Author(s)
  Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
- Journal Title
  
  IEICE Transactions on Information and Systems
  
  Volume: 96
- NAID
  130003370948
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-24700050
[Journal Article] A comparison of multi-valued and heterogeneous decision diagram machines2012
- Author(s)
  Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
- Journal Title
  
  Journal of Multiple-Valued Logic and Soft Computing
  
  Volume: 19 Pages: 203-217
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-24700050
[Presentation] A Consideration on Ternary Adversarial Generative Networks2023
- Author(s)
  Kennichi Nakamura, Hiroki Nakahara
- Organizer
  ISMVL
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19H04078
[Presentation] A Light-Weight Vision Transformer Toward Near Memory Computation on an FPGA2023
- Author(s)
  Takeshi Senoo, Ryota Kayanoma, Akira Jinguji, Hiroki Nakahara
- Organizer
  ARC
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19H04078
[Presentation] A Multilayer Perceptron Training Accelerator using Systolic Array2021
- Author(s)
  Takeshi Senoo, Akira Jinguji, Ryosuke Kuramochi, Hiroki Nakahara
- Organizer
  IEEE APCCAS
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19H04078
[Presentation] Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner2021
- Author(s)
  Kota Ando, Jaehoon Yu, Kazutoshi Hirose, Hiroki Nakahara, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
- Organizer
  IEEE HCS
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19H04078
[Presentation] A High-Throughput Detection Circuit based on 2q+1-Valued Deep Neural Networks2021
- Author(s)
  Naoto Soga, Ryosuke Kuramochi, Hiroki Nakahara
- Organizer
  IEEE ISMVL
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19H04078
[Presentation] Fast Monocular Depth Estimation on an FPGA2020
- Author(s)
  Youki Sada, Naoto Soga, Masayuki Shimoda, Akira Jinguji, Shimpei Sato, Hiroki Nakahara
- Organizer
  IPDPS Workshops 2020
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19H04078
[Presentation] 2n+1-valued SSS-Net: Uniform Shift, Channel Sparseness, and Channel Shuffle2020
- Author(s)
  Hiroki Nakahara
- Organizer
  ISMVL2020
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19H04078
[Presentation] High-Throughput Convolutional Neural Network on an FPGA by Customized JPEG Compression2020
- Author(s)
  Hiroki Nakahara, Zhiqiang Que, Wayne Luk
- Organizer
  FCCM2020
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19H04078
[Presentation] Optimizing Reconfigurable Recurrent Neural Networks2020
- Author(s)
  Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Xinyu Niu, Wayne Luk
- Organizer
  FCCM2020
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19H04078
[Presentation] An FPGA-Based Low-Latency Accelerator for Randomly Wired Neural Networks2020
- Author(s)
  Ryosuke Kuramochi, Hiroki Nakahara
- Organizer
  FPL2020
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19H04078
[Presentation] FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network.2019
- Author(s)
  Hiroki Nakahara, Youki Sada, Masayuki Shimoda, Kouki Sayama, Akira Jinguji, Shimpei Sato
- Organizer
  FPL2019
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19H04078
[Presentation] Noise Convolutional Neural Networks and FPGA Implementation2019
- Author(s)
  Atsuki Munakata, Hiroki Nakahara, Shimpei Sato
- Organizer
  ISMVL 2019
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19H04078
[Presentation] Deep Learning Accelerator for an Intelligent Camera2019
- Author(s)
  Hiroki Nakahara
- Organizer
  HEART 2019
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19H04078
[Presentation] An FPGA-based Fine Tuning Accelerator for a Sparse CNN2019
- Author(s)
  Hiroki Nakahara, Akira Jinguji, Masayuki Shimoda, Shimpei Sato
- Organizer
  FPGA 2019
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H05304
[Presentation] A Dataflow Pipelining Architecture for Tile Segmentation with a Sparse MobileNet on an FPGA2019
- Author(s)
  Youki Sada, Masayuki Shimoda, Akira Jinguji, Hiroki Nakahara
- Organizer
  FPT 2019
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19H04078
[Presentation] Filter-Wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation2019
- Author(s)
  Masayuki Shimoda, Youki Sada, Hiroki Nakahara
- Organizer
  ARC 2019
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H05304
[Presentation] Filter-Wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation2019
- Author(s)
  Masayuki Shimoda, Youki Sada, Hiroki Nakahara
- Organizer
  ARC2019
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19H04078
[Presentation] A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA2018
- Author(s)
  Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Shimpei Sato
- Organizer
  FPGA
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H05304
[Presentation] A Performance Per Power Efficient Object Detector on an FPGA for Robot Operating System (ROS)2018
- Author(s)
  Haoxuan Cheng, Shimpei Sato, Hiroki Nakahara
- Organizer
  HEART 2018
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H05304
[Presentation] A Ternary Weight Binary Input Convolutional Neural Network: Realization on the Embedded Processor2018
- Author(s)
  Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara
- Organizer
  ISMVL 2018
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H05304
[Presentation] Demonstration of Object Detection for Event-Driven Cameras on FPGAs and GPUs2018
- Author(s)
  Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
- Organizer
  FPL 2018
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H05304
[Presentation] Power Efficient Object Detector with an Event-Driven Camera on an FPGA2018
- Author(s)
  Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
- Organizer
  HEART 2018
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H05304
[Presentation] A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA2018
- Author(s)
  Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Shimpei Sato
- Organizer
  FPGA 2018
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H05304
[Presentation] A High-speed Low-power Deep Neural Network on an FPGA based on the Nested RNS: Applied to an Object Detector2018
- Author(s)
  Hiroki Nakahara, Tsutomu Sasao
- Organizer
  ISCAS 2018
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H05304
[Presentation] A Demonstration of FPGA-Based You Only Look Once Version2 (YOLOv2)2018
- Author(s)
  Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato
- Organizer
  FPL 2018
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H05304
[Presentation] New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications2018
- Author(s)
  Taro Fujii, Takao Toi, Teruhito Tanaka, Katsumi Togawa, Toshiro Kitaoka, Kengo Nishino, Noritsugu Nakamura, Hiroki Nakahara, Masato Motomura
- Organizer
  VLSI Circuits 2018
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H05304
[Presentation] An object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGA2017
- Author(s)
  Hiroki Nakahara, Haruyoshi Yonekawa, Shimpei Sato
- Organizer
  FPT
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H05304
[Presentation] On-Chip Memory Based Binarized Convolutional Deep Neural Network Applying Batch Normalization Free Technique on an FPGA2017
- Author(s)
  Haruyoshi Yonekawa, Hiroki Nakahara
- Organizer
  IPDPS Workshops
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H05304
[Presentation] A fully connected layer elimination for a binarizec convolutional neural network on an FPGA2017
- Author(s)
  Hiroki Nakahara, Tomoya Fujii, Shimpei Sato
- Organizer
  FPL
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H05304
[Presentation] A Random Forest Using a Multi-valued Decision Diagram on an FPGA2017
- Author(s)
  Hiroki Nakahara, Akira Jinguji, Simpei Sato, Tsutomu Sasao
- Organizer
  ISMVL
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H05304
[Presentation] An FPGA Realization of a Deep Convolutional Neural Network Using a Threshold Neuron Pruning2017
- Author(s)
  Tomoya Fujii, Simpei Sato, Hiroki Nakahara, Masato Motomura
- Organizer
  ARC
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H05304
[Presentation] An FFT Circuit Using Nested RNS in a Digital Spectrometer for a Radio Telescope2016
- Author(s)
  Hiroki Nakahara, Tsutomu Sasao, Hiroyuki Nakanishi, Kazumasa Iwai, Tohru Nagao, Naoya Ogawa
- Organizer
  International Symposium on Multiple-Valued Logic
- Place of Presentation
  北海道（北海道大学）
- Year and Date
  2016-05-18
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H05304
[Presentation] A deep convolutional neural network based on nested residue number system2015
- Author(s)
  H. Nakahara and T. Sasao
- Organizer
  25th International Conference on Filed-Programmable Logic and Applications (FPL 2015)
- Place of Presentation
  Royal Institution (London,England)
- Year and Date
  2015-09-02
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H05304
[Presentation] An RNS FFT circuit using LUT cascades based on a modulo EVMDD2015
- Author(s)
  H. Nakahara, T. Sasao, H. Nakanishi, and K. Iwai
- Organizer
  The 45th IEEE International Symposium on Multiple-valued Logic (ISMVL 2015)
- Place of Presentation
  University of Waterloo (Waterloo,Canada)
- Year and Date
  2015-05-18
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H05304
[Presentation] A HIGH-SPEED FFT BASED ON A SIX-STEP ALGORITHM: APPLIED TO A RADIO TELESCOPE FOR A SOLAR RADIO BURST2013
- Author(s)
  Hiroki Nakahara, Kazumasa Iwai, Hiroyuki Nakanishi
- Organizer
  The International Conference on Field-Programmable Technology (FPT)
- Place of Presentation
  京都
- Invited
- Data Source
  KAKENHI-PROJECT-24700050
[Presentation] A Packet Classifier using Parallel EVMDD (k) Machine2013
- Author(s)
  Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
- Organizer
  2013 IEEE 7th International Symposium on Embedded Multicore/ Manycore System-on-Chip
- Place of Presentation
  東京
- Invited
- Data Source
  KAKENHI-PROJECT-24700050
[Presentation] A PACKET CLASSIFIER USING LUT CASCADES BASED ON EVMDDS (k)2013
- Author(s)
  Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
- Organizer
  2013 IEEE 23rd International Conference on Filed-Programmable Logic and Applications
- Place of Presentation
  Porto, ポルトガル
- Invited
- Data Source
  KAKENHI-PROJECT-24700050
[Presentation] A Machine to Evaluate Decomposed Multi-Terminal Multi-valued Decision Diagrams for Characteristic Functions2013
- Author(s)
  Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
- Organizer
  2013 IEEE 43rd International Symposium on Multiple-Valued Logic
- Place of Presentation
  富山
- Invited
- Data Source
  KAKENHI-PROJECT-24700050
[Presentation] 分割MTMDDs for CFに基づく多値プロセッサのコード生成フローに関して
- Author(s)
  中原啓貴, 笹尾勤,松浦宗寛,中嶋亮太
- Organizer
  電子情報通信学会「第26回多値論理とその応用研究会」
- Place of Presentation
  東京
- Data Source
  KAKENHI-PROJECT-24700050
[Presentation] An AWF digital spectrometer for a radio telescope
- Author(s)
  H. Nakahara, H. Nakanishi, K. Iwai
- Organizer
  2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig 2014)
- Place of Presentation
  カンクン（メキシコ）
- Year and Date
  2014-12-08 – 2014-12-10
- Data Source
  KAKENHI-PROJECT-24700050
[Presentation] Automatic adjustment system for optical interconnection transmitter using improved particle swarm optimization
- Author(s)
  K. Ohhata, H. Nakahara, T. Inoue, T. Yazaki, N. Chujo, T. Nishimoto
- Organizer
  International Symposium on Integrated Circuits (ISIC 2014)
- Place of Presentation
  シンガポール(シンガポール)
- Year and Date
  2014-11-20 – 2014-11-21
- Data Source
  KAKENHI-PROJECT-24700050
[Presentation] An update method for a CAM emulator using an LUT cascade based on an EVMDD (k)
- Author(s)
  H. Nakahara, T. Sasao, M. Matsuura
- Organizer
  The 44th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2014)
- Place of Presentation
  ブレーメン(ドイツ)
- Year and Date
  2015-05-19 – 2015-05-21
- Data Source
  KAKENHI-PROJECT-24700050
[Presentation] 分割MTMDDs for CFに基づく多値プロセッサに関して
- Author(s)
  中原啓貴, 笹尾勤,松浦宗寛
- Organizer
  2012年電子情報通信学会ソサエティ大会
- Place of Presentation
  富山
- Data Source
  KAKENHI-PROJECT-24700050
[Presentation] Multi-terminal multiple-valued decision diagrams for characteristic function representing cluster decomposition
- Author(s)
  Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
- Organizer
  The 42nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2012)
- Place of Presentation
  カナダ（ビクトリア）
- Data Source
  KAKENHI-PROJECT-24700050
[Presentation] A machine to evaluate decomposed multi-terminal multi-valued decision diagrams for characteristic functions
- Author(s)
  Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
- Organizer
  The 43rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2013)
- Place of Presentation
  富山
- Data Source
  KAKENHI-PROJECT-24700050

1. 佐野健太郎 (00323048)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
2. 佐藤真平 (80782763)

# of Collaborated Projects: 1 results

# of Collaborated Products: 8 results
3. 神宮司明良 (90914242)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
4. 笹尾勤

# of Collaborated Projects: 0 results

# of Collaborated Products: 1 results

Nakahara Hiroki 中原 啓貴

NAKAHARA Hiroki 中原 啓貴

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Development of a Binary Vision Transformer HardwarePrincipal Investigator

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On a noise convolutional neural networkPrincipal Investigator

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Development of Next Generation Spectrometer for Radio TelescopePrincipal Investigator

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A general purpose processor based on a multi-valued decision diagramPrincipal Investigator

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[Journal Article] Remarn: A Reconfigurable Multi-threaded Multi-core Accelerator for Recurrent Neural Networks2023

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[Journal Article] Optimizations of Ternary Generative Adversarial Networks2022

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[Journal Article] Multilayer Perceptron Training Accelerator Using Systolic Array2022

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[Journal Article] Recurrent Neural Networks With Column-Wise Matrix-Vector Multiplication on FPGAs2022

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[Journal Article] Fast Interface with Ensemble Ternary Neural Network2022

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[Journal Article] FPGA-Based Inter-layer Pipelined Accelerators for Filter-Wise Weight-Balanced Sparse Fully Convolutional Networks with Overlapped Tiling2021

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[Journal Article] A Low-Latency Inference of Randomly Wired Convolutional Neural Networks on an FPGA2021

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[Journal Article] Weight Sparseness for a Feature-Map-Split-CNN Toward Low-Cost Embedded FPGAs2021

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[Journal Article] Energy-Efficient ECG Signals Outlier Detection Hardware Using a Sparse Robust Deep Autoencoder2021

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[Journal Article] SENTEI: Filter-Wise Pruning with Distillation towards Efficient Sparse Convolutional Neural Network Accelerators2020

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[Journal Article] GUINNESS: A GUI Based Binarized Deep Neural Network Framework for Software Programmers2019

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Nakahara Hiroki 中原啓貴

NAKAHARA Hiroki 中原啓貴