Ando Hideki 安藤秀樹

… Alternative Names

ANDO Hideki 安藤秀樹

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Researcher Number	40293667
Other IDs
External Links
Affiliation (Current)	2025: 名古屋大学, 情報基盤センター, 招へい教員
Affiliation (based on the past Project Information) *help	2020 – 2023: 名古屋大学, 工学研究科, 教授 2016 – 2018: 名古屋大学, 工学研究科, 教授 2012 – 2015: 名古屋大学, 工学(系)研究科(研究院), 教授 2011 – 2012: 名古屋大学, 工学研究科, 教授 2007 – 2010: Nagoya University, 大学院・工学研究科, 教授 1998 – 2001: 名古屋大学, 工学研究科, 助教授
Review Section/Research Field	Principal Investigator Computer system / Computer system/Network / Basic Section 60040:Computer system-related / 計算機科学 Except Principal Investigator 計算機科学
Keywords	Principal Investigator マイクロプロセッサ / コンピュータ・アーキテクチャ / スーパスカラ方式 / 発行キュー / スーパスカラ・プロセッサ / 計算機アーキテクチャ / 低電力コンピュータ / 高性能コンピュータ / コンピュータアーキテクチャ / メモリ・レベル並列 … More / リオーダ・バッファ / マイクロアーキテクチャ / リオーダバッファ / 分岐先バッファ / ALU / キャッシュ / キャッシュパーティショニング / 最終レベルキャッシュ / thread-level parallelism / instruction-level parallelism / multiprocessor / microprocessor / スレッドレベル並列 / 命令レベル並列 / マルチプロセッサ / 低電力 / プリフェッチ / データ … More Except Principal Investigator value prediction / both-path execution / microprocessor / speculative execution / branch prediction / 高速化 / 値予測 / 両パス実行 / マイクロプロセッサ / 投機的実行 / 分岐予測 Less

Study on microprocessors for high performance and low power consumption after breakdown of Moore's lawPrincipal Investigator
- Principal Investigator
  
  Ando Hideki
- Project Period (FY)
  2020 – 2023
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Nagoya University
Study on computer architcture for high performance and low power consumptionPrincipal Investigator
- Principal Investigator
  
  Ando Hideki
- Project Period (FY)
  2016 – 2018
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system
- Research Institution
  Nagoya University
Computer architecture for high performance and low power consumptionPrincipal Investigator
- Principal Investigator
  
  Ando Hideki
- Project Period (FY)
  2013 – 2015
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system
- Research Institution
  Nagoya University
Study on architecture of high-performance computersPrincipal Investigator
- Principal Investigator
  
  ANDO Hideki
- Project Period (FY)
  2010 – 2012
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system/Network
- Research Institution
  Nagoya University
Study on architectures of high-performance computersPrincipal Investigator
- Principal Investigator
  
  ANDO Hideki
- Project Period (FY)
  2007 – 2009
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system/Network
- Research Institution
  Nagoya University
Research on Branch Prediction and Speculative Execution
- Principal Investigator
  
  SHIMODA Toshio
- Project Period (FY)
  1999 – 2001
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  計算機科学
- Research Institution
  Nagoya University
Research on high-performance microprocessor with distributed instruction-level parallelismPrincipal Investigator
- Principal Investigator
  
  ANDO Hideki
- Project Period (FY)
  1998 – 2000
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  計算機科学
- Research Institution
  Nagoya University

[Journal Article] Reducing Energy Consumption of Wakeup Logic through Double-Stage Tag Comparison2022
- Author(s)
  Y. Matsuda, R. Shioya, and H. Ando
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: E105.D Issue: 2 Pages: 320-332
- DOI
  10.1587/transinf.2021EDP7174
- NAID
  130008149967
- ISSN
  0916-8532, 1745-1361
- Year and Date
  2022-02-01
- Language
  English
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-20K11732
[Journal Article] Performance Improvement Techniques in Tightly Coupled Multicore Architectures for Single-Thread Applications2018
- Author(s)
  K. Doi, R. Shioya, and H. Ando
- Journal Title
  
  IPSJ Journal of Information Processing
  
  Volume: 26 Pages: 445-460
- NAID
  130007397242
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-16K00070
[Journal Article] Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control2016
- Author(s)
  H. Ando and R. Shioya
- Journal Title
  
  IEICE Transactions on Information and Systems
  
  Volume: E99-D Pages: 341-350
- NAID
  130005122012
- Peer Reviewed / Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-25330057
[Journal Article] Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency2016
- Author(s)
  R. Shioya and H. Ando
- Journal Title
  
  IEICE Transactions on Information and Systems
  
  Volume: E99-D Pages: 630-640
- NAID
  130005131824
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-25330057
[Journal Article] FXA: Executing Instructions in Front-End for Energy Efficiency2016
- Author(s)
  R. Shioya, R. Takami, M. Goshima, and H. Ando
- Journal Title
  
  IEICE Transactions on Information and Systems
  
  Volume: E99-D Pages: 1092-1107
- NAID
  130005141379
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-25330057
[Journal Article] MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available Parallelism2014
- Author(s)
  Y. Kora, K. Yamaguchi, and H. Ando
- Journal Title
  
  IEICE Transactions on Information and Systems
  
  Volume: E97-D Pages: 3110-3123
- NAID
  130004841753
- Peer Reviewed / Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-25330057
[Journal Article] Delay Evaluation of issue Queue in Superscalar Processors with Banking Tag RAM and Correct Critical Path Identification2012
- Author(s)
  K. Yamaguchi, Y. Kora, and H. Ando
- Journal Title
  
  IEICE Transactions on Information and Systems
  
  Volume: Vol.E95-D, No.9 Pages: 2235-2246
- NAID
  10031142840
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22500045
[Journal Article] Register File Size Reduction through Instruction Pre-Execution Incorporating Value Prediction2010
- Author(s)
  Y. Tanaka and H. Ando
- Journal Title
  
  IEICE Transactions on Information and Systems
  
  Volume: Vol. E93-D, No.12 Pages: 3294-3305
- NAID
  10027989078
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22500045
[Journal Article] Energy-Efficient Pre-Execution Techniques in Two-Step Physical Register Deallocation2009
- Author(s)
  K.Hyodo, K.Iwamoto, H.Ando
- Journal Title
  
  IEICE Transactions on Information and Systems E92-D
  
  Pages: 2186-2195
- NAID
  10026812073
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19500041
[Journal Article] Energy-Efficient Pre-Execution Techniques in Two-Step Physical Register Deallocation2009
- Author(s)
  K. Hyodo, K. Iwamoto, H. Ando
- Journal Title
  
  IEICE Transactions on Information and Systems Vol.E92-D,No.11
  
  Pages: 2186-2195
- NAID
  10026812073
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19500041
[Journal Article] Two-Step Physical Register Deallocation for Data Prefetching and Address Pre-Calculation2008
- Author(s)
  A. Yamamoto, Y. Tanaka, H. Ando, T. Shimada
- Journal Title
  
  IPSJ Transactions on Advanced Computing Systems Vol.1,No.2
  
  Pages: 34-46
- NAID
  130000022127
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19500041
[Presentation] 選択的レベル2命令キャッシュの追加によるキャッシュの消費電力の削減2023
- Author(s)
  松浦淳, 安藤秀樹
- Organizer
  情報処理学会研究報告
- Data Source
  KAKENHI-PROJECT-20K11732
[Presentation] 整数命令のレイテンシ耐性を利用したALUの消費電力削減手法,2023
- Author(s)
  黒川陸, 安藤秀樹
- Organizer
  情報処理学会研究報告
- Data Source
  KAKENHI-PROJECT-20K11732
[Presentation] TAGE分岐予測器がプロセッサ性能に与える影響の評価2023
- Author(s)
  近藤祐生，安藤秀樹
- Organizer
  情報処理学会研究報告
- Data Source
  KAKENHI-PROJECT-20K11732
[Presentation] Segmenting Age Matrices to Improve Instruction Scheduling without Increasing Delay and Area2022
- Author(s)
  H. Ando
- Organizer
  The 40th IEEE International Conference on Computer Design
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-20K11732
[Presentation] フィルタ・キャッシュにおける低電力化置換ポリシー2022
- Author(s)
  彭南翔, 安藤秀樹
- Organizer
  情報処理学会研究報告
- Data Source
  KAKENHI-PROJECT-20K11732
[Presentation] 発行キューの電力削減のための発行幅制御方式2021
- Author(s)
  後岡瑞希, 安藤秀樹
- Organizer
  情報処理学会研究報告, Vol.2021-ARC-244, No.35
- Data Source
  KAKENHI-PROJECT-20K11732
[Presentation] 容量効率を意識したソース・タグ値に基づくセグメント化による発行キューのエネルギー削減2020
- Author(s)
  森健一郎, 安藤秀樹
- Organizer
  情報処理学会研究報告, Vol.2020-ARC-241, No.3
- Data Source
  KAKENHI-PROJECT-20K11732
[Presentation] SWQUE:優先度を修正するサーキュラー・キューを持ったモード切り替え発行キュー2020
- Author(s)
  安藤秀樹
- Organizer
  IEICE/IPSJ 第19回情報科学技術フォーラム, トップカンファレンス・セッション
- Invited
- Data Source
  KAKENHI-PROJECT-20K11732
[Presentation] キャッシュ・パーティショニングによる性能向上のための MLP を意識した実行サイクル数の推定2019
- Author(s)
  今泉勇斗, 塩谷亮太, 安藤秀樹
- Organizer
  情報処理学会研究報告
- Data Source
  KAKENHI-PROJECT-16K00070
[Presentation] パイプライン構造の動的制御による命令フェッチ・スループットの向上2018
- Author(s)
  松尾玲央馬, 塩谷亮太, 安藤秀樹
- Organizer
  情報処理学会研究報告, Vol.2018-ARC-232, No.
- Data Source
  KAKENHI-PROJECT-16K00070
[Presentation] A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power Mode2018
- Author(s)
  Y. Chidai, K. Izuoka, R. Shioya, M. Goshima, and H. Ando
- Organizer
  Proceedings of the 31st International Conference on Architecture of Computing Systems
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16K00070
[Presentation] SRAMの電力/遅延シミュレータCACTIへのシングルエンド方式の対応2018
- Author(s)
  李虹希, 塩谷亮太, 安藤秀樹
- Organizer
  情報処理学会研究報告, Vol.2018-ARC-232, No.15
- Data Source
  KAKENHI-PROJECT-16K00070
[Presentation] A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power Mode2018
- Author(s)
  Y. Chidai, K. Izuoka, R. Shioya, M. Goshima, and H. Ando
- Organizer
  A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power Mode
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16K00070
[Presentation] グループ化したストリームからのフィードバックを用いたストリーム毎に最適化するストリーム・プリフェチャの高効率化2018
- Author(s)
  劉兆良, 塩谷亮太, 安藤秀樹
- Organizer
  情報処理学会研究報告, Vol.2019-ARC-235, No.21
- Data Source
  KAKENHI-PROJECT-16K00070
[Presentation] Performance Improvement by Prioritizing the Issue of the Instructions in Unconfident Branch Slices2018
- Author(s)
  H. Ando
- Organizer
  Proceedings of the 51st Annual International Symposium on Microarchitecture
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16K00070
[Presentation] Rearranging Random Issue Queue with High IPC and Short Delay2018
- Author(s)
  S. Sakai, T. Suenaga, R. Shioya, and H. Ando
- Organizer
  Proceesings of the 36th IEEE International Conference on Computer Design
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16K00070
[Presentation] 低電力モードを備えるプロセッサとモード切り替えアルゴリズムによる電力効率の向上2017
- Author(s)
  塩谷亮太, 地代康政, 出岡宏二郎, 五島正裕, 安藤秀樹
- Organizer
  情報処理学会研究報告
- Data Source
  KAKENHI-PROJECT-16K00070
[Presentation] フロントエンド実行方式における高エネルギー効率なメモリ・レベル並列性の利用2016
- Author(s)
  出岡宏二郎, 塩谷亮太, 安藤秀樹
- Organizer
  情報処理学会研究報告
- Place of Presentation
  五島市
- Year and Date
  2016-03-24
- Data Source
  KAKENHI-PROJECT-25330057
[Presentation] フロントエンド実行方式におけるエネルギー効率向上のためのインオーダ実行モード切り替えアルゴリズム2016
- Author(s)
  地代康政, 出岡宏二郎, 塩谷亮太, 安藤秀樹
- Organizer
  情報処理学会研究報告
- Place of Presentation
  五島市
- Year and Date
  2016-03-24
- Data Source
  KAKENHI-PROJECT-25330057
[Presentation] 最適な置き換え予測に基づくフィルタ・キャッシュのミス率削減2016
- Author(s)
  古橋陽平, 塩谷亮太, 安藤秀樹
- Organizer
  情報処理学会研究報告
- Place of Presentation
  五島市
- Year and Date
  2016-03-24
- Data Source
  KAKENHI-PROJECT-25330057
[Presentation] フロントエンド実行方式におけるエネルギー効率向上のためのインオーダ実行モード切り替えアルゴリズムの初期検討2015
- Author(s)
  地代康政, 塩谷亮太, 安藤秀樹
- Organizer
  情報処理学会研究報告
- Place of Presentation
  別府市
- Year and Date
  2015-08-04
- Data Source
  KAKENHI-PROJECT-25330057
[Presentation] ランダムバッファの発行キューにより生じる性能低下の抑制2015
- Author(s)
  酒井信二, 塩谷亮太, 安藤秀樹
- Organizer
  情報処理学会研究報告
- Place of Presentation
  別府市
- Year and Date
  2015-08-04
- Data Source
  KAKENHI-PROJECT-25330057
[Presentation] 資源リサイジングとクロック周波数ブーストを適応的に切り替えるデュアルターボブースト2013
- Author(s)
  山口恭平, 塩谷亮太, 安藤秀樹
- Organizer
  2013年先進的計算基盤システムシンポジウム
- Place of Presentation
  仙台
- Data Source
  KAKENHI-PROJECT-25330057
[Presentation] タグの2段階比較による発行キューの消費エネルギー削減2013
- Author(s)
  小林誠弥, 塩谷亮太, 安藤秀樹
- Organizer
  2013年先進的計算基盤システムシンポジウム
- Place of Presentation
  仙台
- Data Source
  KAKENHI-PROJECT-25330057
[Presentation] MLP-Aware Dynamic Instruction Window Resizing for Adaptively Exploiting Both ILP and MLP2013
- Author(s)
  Y. Kora, K. Yamaguchi, and H. Ando
- Organizer
  46th Annual International Symposium on Microarchitecture
- Place of Presentation
  Davis, CA, USA
- Data Source
  KAKENHI-PROJECT-25330057
[Presentation] 資源リサイジングとクロック周波数ブーストを適応的に切り替えるデュアルターボブースト2013
- Author(s)
  山口恭平, 塩谷亮太, 安藤秀樹
- Organizer
  2013 年先進的計算基盤システムシンポジウム SACSIS 2013
- Place of Presentation
  仙台市
- Year and Date
  2013-05-22
- Data Source
  KAKENHI-PROJECT-22500045
[Presentation] 仮想リオーダ・バッファ方式におけるロード/ストア・キューの単純化2012
- Author(s)
  稲垣貴範, 塩谷亮太, 安藤秀樹
- Organizer
  2012 年先進的計算基盤システムシンポジウム SACSIS 2012
- Place of Presentation
  神戸市
- Year and Date
  2012-05-17
- Data Source
  KAKENHI-PROJECT-22500045
[Presentation] 動的な資源のリサイジングを組み合わせたデュアルターボブースト2012
- Author(s)
  山口恭平, 塩谷亮太, 安藤秀樹
- Organizer
  情報処理学会研究報告
- Place of Presentation
  鳥取市
- Year and Date
  2012-08-01
- Data Source
  KAKENHI-PROJECT-22500045
[Presentation] 仮想リオーダ・バッファ方式におけるロード/ストア・キューの単純化2012
- Author(s)
  稲垣貴範, 塩谷亮太, 安藤秀樹
- Organizer
  情報処理学会研究報告
- Place of Presentation
  東京
- Year and Date
  2012-01-20
- Data Source
  KAKENHI-PROJECT-22500045
[Presentation] L1 データ・キャッシュ・ミスに着目した命令発行キューの動的リサイジング2012
- Author(s)
  有松優, 塩谷亮太, 安藤秀樹
- Organizer
  情報処理学会研究報告
- Place of Presentation
  東京
- Year and Date
  2012-01-20
- Data Source
  KAKENHI-PROJECT-22500045
[Presentation] MLP に着目したパイプライン化発行キューの動的サイジング2011
- Author(s)
  甲良祐也, 安藤秀樹
- Organizer
  2011 年先進的計算基盤システムシンポジウム SACSIS 2011
- Place of Presentation
  東京
- Year and Date
  2011-05-25
- Data Source
  KAKENHI-PROJECT-22500045
[Presentation] Evaluation of Issue Queue Delay: Banking Tag RAM and Identifying Correct Critical Path2011
- Author(s)
  K. Yamaguchi, Y. Kora, and H. Ando
- Organizer
  Proceedings of the 29th International Conference on Computer Design
- Place of Presentation
  Amherst, MA, USA
- Year and Date
  2011-10-10
- Data Source
  KAKENHI-PROJECT-22500045
[Presentation] 仮想リオーダ・バッファ方式における選択的先行実行による低消費電力化2011
- Author(s)
  加藤里奈, 安藤秀樹
- Organizer
  情報処理学会研究報告
- Place of Presentation
  鹿児島市
- Year and Date
  2011-07-27
- Data Source
  KAKENHI-PROJECT-22500045
[Presentation] 仮想化により拡大したリオーダ・バッファによる先行実行2011
- Author(s)
  市原敬吾, 田中雄介, 安藤秀樹
- Organizer
  2011 年先進的計算基盤システムシンポジウムSACSIS 2011
- Place of Presentation
  東京
- Year and Date
  2011-05-25
- Data Source
  KAKENHI-PROJECT-22500045
[Presentation] 発行キューのタグ RAM のバンク化と正確なクリティカルパスの遅延時間評価2011
- Author(s)
  山口恭平, 甲良祐也, 安藤秀樹
- Organizer
  情報処理学会研究報告
- Place of Presentation
  鹿児島市
- Year and Date
  2011-07-27
- Data Source
  KAKENHI-PROJECT-22500045
[Presentation] リオーダ・バッファのハードウェア量と消費エネルギーの削減2010
- Author(s)
  岩原佑磨,安藤秀樹
- Organizer
  2010 年先進的計算基盤システムシンポジウム SACSIS 2010
- Place of Presentation
  奈良市
- Year and Date
  2010-05-25
- Data Source
  KAKENHI-PROJECT-22500045
[Presentation] リオーダ・バッファのハードウェア量と消費エネルギーの削減2010
- Author(s)
  岩原佑磨、安藤秀樹
- Organizer
  2010年先進的計算基盤システムシンポジウムSACSIS 2010
- Place of Presentation
  奈良市(採録決定)
- Year and Date
  2010-05-27
- Data Source
  KAKENHI-PROJECT-19500041
[Presentation] リオーダ・バッファの仮想的な拡大による先行実行2010
- Author(s)
  市原敬吾,田中雄介,安藤秀樹
- Organizer
  情報処理学会研究報告
- Place of Presentation
  金沢市
- Year and Date
  2010-08-04
- Data Source
  KAKENHI-PROJECT-22500045
[Presentation] 命令発行キューの遅延時間評価2010
- Author(s)
  甲良祐也、安藤秀樹
- Organizer
  2010年先進的計算基盤システムシンポジウムSACSIS 2010
- Place of Presentation
  奈良市(採録決定)
- Year and Date
  2010-05-27
- Data Source
  KAKENHI-PROJECT-19500041
[Presentation] 命令発行キューの遅延時間評価2010
- Author(s)
  甲良祐也,安藤秀樹
- Organizer
  2010 年先進的計算基盤システムシンポジウム SACSIS 2010
- Place of Presentation
  奈良市
- Year and Date
  2010-05-25
- Data Source
  KAKENHI-PROJECT-22500045
[Presentation] 物理レジスタ2段階解放方式の低消費電力化手法の評価2009
- Author(s)
  岩本健吾, 安藤秀樹
- Organizer
  情報処理学会研究報告
- Place of Presentation
  沖縄市
- Year and Date
  2009-04-24
- Data Source
  KAKENHI-PROJECT-19500041
[Presentation] Reducing Register File Size through Instruction Pre-Execution Enhanced by Value Prediction2009
- Author(s)
  Y. Tanaka, H. Ando
- Organizer
  In Proceedings of the 27th IEEE International Conference on Computer Design
- Place of Presentation
  Olympic Valley, CA, USA
- Year and Date
  2009-10-04
- Data Source
  KAKENHI-PROJECT-19500041
[Presentation] 命令発行キューの深いパイプライン化のための投機発行2009
- Author(s)
  加藤伸幸、安藤秀樹
- Organizer
  2009年先進的計算基盤システムシンポジウムSACSIS 2009
- Place of Presentation
  広島市
- Year and Date
  2009-05-29
- Data Source
  KAKENHI-PROJECT-19500041
[Presentation] 値予測を用いた命令先行実行によるレジスタ・ファイルの縮小2009
- Author(s)
  田中雄介、安藤秀樹
- Organizer
  2009年先進的計算基盤システムシンポジウムSACSIS 2009
- Place of Presentation
  広島市
- Year and Date
  2009-05-29
- Data Source
  KAKENHI-PROJECT-19500041
[Presentation] 選択的先行実行による物理レジスタ2段階解放方式の低消費電力化2008
- Author(s)
  兵藤一永、安藤秀樹
- Organizer
  2008年先進的計算基盤システムシンポジウムSACSIS 2008
- Place of Presentation
  旭川市
- Year and Date
  2008-06-11
- Data Source
  KAKENHI-PROJECT-19500041
[Presentation] 命令発行キューの深いパイプライン化2008
- Author(s)
  加藤伸幸, 安藤秀樹
- Organizer
  情報処理学会研究報告
- Place of Presentation
  佐賀市
- Year and Date
  2008-08-06
- Data Source
  KAKENHI-PROJECT-19500041
[Presentation] 値予測を用いた物理レジスタ2段階開放による命令先行実行方式の性能向上2008
- Author(s)
  田中雄介, 安藤秀樹
- Organizer
  情報処理学会研究報告
- Place of Presentation
  二日市市
- Year and Date
  2008-10-20
- Data Source
  KAKENHI-PROJECT-19500041
[Presentation] 物理レジスタ2段階解放による命令先行実行方式の評価2007
- Author(s)
  田中雄介、安藤秀樹
- Organizer
  情報処理学会研究報告
- Place of Presentation
  旭川市
- Year and Date
  2007-08-14
- Data Source
  KAKENHI-PROJECT-19500041
[Presentation] 物理レジスタ2段階解放による命令先行実行方式の低消費電力化2007
- Author(s)
  兵藤一永、安藤秀樹
- Organizer
  情報処理学会研究報告
- Place of Presentation
  旭川市
- Year and Date
  2007-08-14
- Data Source
  KAKENHI-PROJECT-19500041
[Presentation] Data Prefetching and Address Pre-Calculation through Instruction Pre-Execution with Two-Step Physical Register Deallocation, '' In Proceedings of the Eighth Workshop on Memory Performance: Dealing with Applications2007
- Author(s)
  A. Yamamoto, Y. Tanaka, H. Ando, T. Shimada
- Organizer
  Systems and Architectures
- Place of Presentation
  Brasov, Romania
- Year and Date
  2007-09-14
- Data Source
  KAKENHI-PROJECT-19500041
[Presentation] タグの2段階比較を行う発行キューによる消費エネルギー削減の評価
- Author(s)
  小林誠弥, 塩谷亮太, 安藤秀樹
- Organizer
  情報処理学会研究報告
- Place of Presentation
  小樽市
- Year and Date
  2014-12-09 – 2014-12-10
- Data Source
  KAKENHI-PROJECT-25330057
[Presentation] Energy Efficiency Improvement of Renamed Trace Cache through Reduction of Dependent Path Length
- Author(s)
  R. Shioya and H. Ando
- Organizer
  32nd International Conference on Computer Design
- Place of Presentation
  Seoul, Korea
- Year and Date
  2014-10-20 – 2014-10-22
- Data Source
  KAKENHI-PROJECT-25330057
[Presentation] A Front-end Execution Architecture for High Energy Efficiency
- Author(s)
  R. Shioya, M. Goshima, and H. Ando
- Organizer
  47th Annual International Symposium on Microarchitecture
- Place of Presentation
  Cambridge, UK
- Year and Date
  2014-12-15 – 2014-12-17
- Data Source
  KAKENHI-PROJECT-25330057
[Presentation] 仮想リオーダ・バッファ方式における性能改善技術
- Author(s)
  蘇翰, 塩谷亮太, 安藤秀樹
- Organizer
  情報処理学会研究報告
- Place of Presentation
  別府市
- Year and Date
  2014-10-06 – 2014-10-07
- Data Source
  KAKENHI-PROJECT-25330057

1. SHIMODA Toshio (60252251)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
2. 小林良太郎 (40324454)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results

Ando Hideki 安藤 秀樹

ANDO Hideki 安藤 秀樹

Research Projects

Research Products

Co-Researchers

Study on microprocessors for high performance and low power consumption after breakdown of Moore's lawPrincipal Investigator

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Study on computer architcture for high performance and low power consumptionPrincipal Investigator

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Computer architecture for high performance and low power consumptionPrincipal Investigator

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Study on architecture of high-performance computersPrincipal Investigator

Principal Investigator

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Study on architectures of high-performance computersPrincipal Investigator

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Research on Branch Prediction and Speculative Execution

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Research on high-performance microprocessor with distributed instruction-level parallelismPrincipal Investigator

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[Journal Article] Reducing Energy Consumption of Wakeup Logic through Double-Stage Tag Comparison2022

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[Journal Article] Performance Improvement Techniques in Tightly Coupled Multicore Architectures for Single-Thread Applications2018

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[Journal Article] Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control2016

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[Journal Article] Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency2016

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[Journal Article] FXA: Executing Instructions in Front-End for Energy Efficiency2016

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[Journal Article] MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available Parallelism2014

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Ando Hideki 安藤秀樹

ANDO Hideki 安藤秀樹