Hosokawa Toshinori 細川利典

… Alternative Names

細川利典ホソカワトシノリ

HOSOKAWA Toshinori 細川利典

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Researcher Number	40373005
Other IDs
Affiliation (Current)	2025: 日本大学, 生産工学部, 教授
Affiliation (based on the past Project Information) *help	2019 – 2023: 日本大学, 生産工学部, 教授 2014 – 2016: 日本大学, 生産工学部, 教授
Review Section/Research Field	Principal Investigator Computer system Except Principal Investigator Basic Section 60040:Computer system-related
Keywords	Principal Investigator マルチサイクルキャプチャテスト生成 / 低消費電力指向テスト生成 / テスト容易化機能的時間展開モデル生成 / 階層テスト生成 / コントローラ拡大 / テストポイント挿入 / 低消費電力指向テスト圧縮 / テスト容易化機能的時間展開モデル / テスト容易化スケジューリング / テスト容易化バインディング … More / 高位合成 / 故障診断 / マルチサイクルキャプチャテスト / テスト環境生成 / テスト容易化合成 / トロイ検出 / 低消費電力 / テスト生成 / 動作合成 … More Except Principal Investigator IPコア / トロイ回路 / 論理暗号化 / 電子透かし / 知的財産権保護 / 論理ロック / IPコア流用検知 / 等価性検証 / ハードウェアトロイ回路 / 到達不能状態 / 内部状態 / 入力系列生成 / モンテカルロツリーサーチ / SATソルバー / ホワイトボックス / ブラックボックス Less

Design technology for detecting IP core piracy
- Principal Investigator
  
  吉村正義
- Project Period (FY)
  2021 – 2024
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Kyoto Sangyo University
Research on LSI design methods to identify Trojan circuits in IP cores
- Principal Investigator
  
  Yoshimura Masayoshi
- Project Period (FY)
  2018 – 2022
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Kyoto Sangyo University
Studies on Non-Scan based Synthesis for Testability and Test Generation from High-Level Design for LSIsPrincipal Investigator
- Principal Investigator
  
  HOSOKAWA Toshinori
- Project Period (FY)
  2014 – 2016
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system
- Research Institution
  Nihon University

All 2024 2023 2022 2021 2020 2019 2018 2017 2016 2015 2014 Other

All Journal Article Presentation

[Journal Article] CRLock: A SAT and FALL Attacks Resistant Logic Locking Method for Controller at Register Transfer Level2024
- Author(s)
  YOSHIMURA Masayoshi、TSUJIKAWA Atsuya、HOSOKAWA Toshinori
- Journal Title
  
  IEICE Trans. Fundamentals
  
  Volume: E107.A Issue: 3 Pages: 583-591
- DOI
  10.1587/transfun.2023VLP0018
- ISSN
  0916-8508, 1745-1337
- Year and Date
  2024-03-01
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21K11817
[Journal Article] A Test Register Assignment Method Based on Controller Augmentation to Reduce the Number of Test Patterns2018
- Author(s)
  Toshinori Hosokawa, Hiroshi Yamazaki, Shun Takeda, Masayoshi Yoshimura
- Journal Title
  
  2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)
  
  Volume: 24 Pages: 228-231
- DOI
  10.1109/iolts.2018.8474097
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18K11228
[Journal Article] A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification2018
- Author(s)
  Toshinori Hosokawa, Morito Niseki, Masayoshi Yoshimura, Hiroshi Yamazaki, Masayuki Arai, Hiroyuki Yotsuyanagi, Masaki Hashizume
- Journal Title
  
  2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)
  
  Volume: 24 Pages: 43-46
- DOI
  10.1109/iolts.2018.8474268
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18K11228
[Journal Article] A Capture Safe Static Test Compaction Method Based on Don't Cares2018
- Author(s)
  Sayuri Ochi, Hiroshi Yamazaki, Toshinori Hosokawa, Masayoshi Yoshimura
- Journal Title
  
  2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)
  
  Volume: 24 Pages: 195-200
- DOI
  10.1109/iolts.2018.8474080
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] An Evaluation of a Testability Measure for State Assignment to Estimate Transition Fault Coverage for Controllers2023
- Author(s)
  Toshinori Hosokawa; Kyohei Iizuka; Masayoshi Yoshimura
- Organizer
  2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-21K11817
[Presentation] A Block Partitioning Method for Region Exhaustive Test to Reduce the Number of Test Patterns and Improve Gate Exhaustive Fault Coverage2023
- Author(s)
  Momona Mizota; Toshinori Hosokawa; Masayoshi Yoshimura; Masayuki Arai
- Organizer
  2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-21K11817
[Presentation] An Evaluation of Estimated Field Random Testability for Data Paths at Register Transfer Level Using Status Signal Sequences Based on k-Consecutive State Transitions for Field Testing2023
- Author(s)
  Yudai Toyooka; Haruki Watanabe; Toshinori Hosokawa; Masayoshi Yoshimura
- Organizer
  2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-21K11817
[Presentation] CRLock: A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level2022
- Author(s)
  Masayoshi Yoshimura, Atsuya Tsujikawa, Hiroshi Yamazaki, and Toshinori Hosokawa
- Organizer
  2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] CRLock: A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level2022
- Author(s)
  Masayoshi Yoshimura, Atsuya Tsujikawa, Hiroshi Yamazaki, and Toshinori Hosokawa
- Organizer
  2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-21K11817
[Presentation] 論理故障テスト並列化のための制御信号のドントケア割当て法2022
- Author(s)
  徐　浩豊, 細川利典, 山崎紘史, 新井雅之, 吉村正義
- Organizer
  ETNET2022
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] 無効状態を含んだコントローラの遷移故障検出率向上指向状態割当て法2022
- Author(s)
  飯塚恭平, 細川利典, 山崎紘史, 吉村正義
- Organizer
  ディペンダブルコンピューティング研究会
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] レジスタ転送レベルにおける非スキャンベースフィールドテスタビリティに基づく制御信号のドントケア割当て法2021
- Author(s)
  飯塚恭平・細川利典・山崎紘史・吉村正義
- Organizer
  ディペンダブルコンピューティング研究会
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level2021
- Author(s)
  Atsuya Tsujikawa, Masayoshi Yoshimura and Toshinori Hosokawa
- Organizer
  IEEE The Workshop on RTL and High Level Testing 2021
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-21K11817
[Presentation] An Additional State Transition Insertion Method to Improve Transition Fault Coverage for Controllers2021
- Author(s)
  Kyohei Iizuka, Toshinori Hosokawa, Hiroshi Yamazaki and Masayoshi Yoshimura
- Organizer
  IEEE The Workshop on RTL and High Level Testing 2021
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] 低消費電力指向多重目標故障テスト生成法2021
- Author(s)
  三浦　怜, 細川利典, 山崎紘史, 吉村正義, 新井雅之
- Organizer
  第6回 Winter Workshop on Safety
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] RTLにおけるSFLL-hdに基づいた論理暗号化手法2021
- Author(s)
  野口葉平, 吉村正義, 辻川敦也, 細川利典
- Organizer
  ディペンダブルコンピューティング研究会
- Data Source
  KAKENHI-PROJECT-21K11817
[Presentation] RTLハードウェア要素のテストスケジューリング情報を用いた多重目標故障テスト生成法2021
- Author(s)
  浅見竜輝・細川利典・山崎紘史・吉村正義・新井雅之
- Organizer
  ディペンダブルコンピューティング研究会
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] レジスタ転送レベルにおけるアンチSATに基づく論理暗号化法2021
- Author(s)
  辻川敦也・細川利典・吉村正義
- Organizer
  ETNET2021
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] コントローラの遷移故障検出率向上のためのコントローラ拡大法2021
- Author(s)
  飯塚恭平・細川利典・山崎紘史・吉村正義
- Organizer
  ETNET2021
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] レジスタ転送レベルにおけるSAT攻撃とFALL攻撃に耐性のある論理暗号化手法2021
- Author(s)
  辻川敦也, 細川利典, 吉村正義
- Organizer
  第6回 Winter Workshop on Safety
- Data Source
  KAKENHI-PROJECT-21K11817
[Presentation] A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the Number of Test Patterns Using Partial MaxSAT2020
- Author(s)
  Ryuki Asami, Toshinori Hosokawa, Masayoshi Yoshimura and Masayuki Arai
- Organizer
  2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] A Low Capture Power Oriented X-Identification-Filling Co-Optimization Method2020
- Author(s)
  Toshinori HOSOKAWA, Kenichiro MISAWA, Hiroshi YAMAZAKI, Masayoshi YOSHIMURA, Masayuki ARAI
- Organizer
  2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] テストパターン数削減のためのゲート網羅故障の多重目標故障テスト生成法2020
- Author(s)
  浅見竜輝・細川利典・吉村正義・新井雅之
- Organizer
  SWoPP2020
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] 機能等価な有限状態機械生成に基づく面積削減指向コントローラ拡大法2020
- Author(s)
  辻川敦也・細川利典・吉村正義
- Organizer
  SWoPP2020
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] A State Assignment Method to Improve Transition Fault Coverage for Controllers2019
- Author(s)
  Masayoshi Yoshimura, Yuki Takeuchi, Hiroshi Yamazaki and Toshinori Hosokawa
- Organizer
  2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] A Don't Care Identification-Filling Co-Optimization Method for Low Capture Power Testing Using Partial MaxSAT2019
- Author(s)
  Kenichiro Misawa, Toshinori Hosokawa, Hiroshi Yamazaki, Masayoshi Yoshimura, and Masayuki Arai
- Organizer
  The 20th Workshop on RTL and High-Level Testing (WRTLT’19)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] A Controller Augmentation Method to Improve Transition Fault Coverage for RTL Data-Paths2019
- Author(s)
  Yuki Takeuchi, Toshinori Hosokawa, Hiroshi Yamazaki, and Masayoshi Yoshimura
- Organizer
  2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] A State Assignment Method to Improve Transition Fault Coverage for Controllers2019
- Author(s)
  Toshinori Hosokawa, Hiroshi Yamazaki, Kenichiro Misawa, Masayoshi Yoshimura, Yuki Hirama, and Masavuki Arai
- Organizer
  2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] コントローラの遷移故障検出率向上のための状態割当て手法2018
- Author(s)
  吉村正義・竹内勇希・細川利典・山崎紘史
- Organizer
  ディペンダブルコンピューティング研究会
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] A design for testability method to improve transition fault coverage using controller augmentation at register transfer level2018
- Author(s)
  Yuki Takeuchi, Toshinori Hosokawa, Hiroshi Yamazaki , Masayoshi Yoshimura
- Organizer
  The Nineteenth Workshop on RTL and High Level Testing
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] レジスタ転送レベルにおけるコントローラ拡大を用いた遷移故障検出率向上のためのテスト容易化設計2018
- Author(s)
  竹内勇希、細川利典、山崎紘史、吉村正義
- Organizer
  DAシンポジウム2018
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] キャプチャセーフテストベクトルの故障伝搬経路を模倣した低消費電力指向ドントケア判定法2018
- Author(s)
  三澤健一郎・細川利典・山崎紘史・吉村正義
- Organizer
  ディペンダブルコンピューティング研究会
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] 拡張シフトレジスタを用いた強セキュア回路設計法2017
- Author(s)
  山崎紘史・細川利典・藤原秀雄
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  東京都機械振興会館
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] 到達不能状態を用いたSATベース順序回路のテスト不能故障判定法2017
- Author(s)
  二関森人・細川利典・吉村正義・新井雅之・四柳浩之・橋爪正樹
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  東京都機械振興会館
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] キャプチャセーフテストベクトルを利用した低消費電力指向テスト生成における動的テスト圧縮法2017
- Author(s)
  細川利典・平井淳士・山崎紘史・新井雅之
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  東京都機械振興会館
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] 抵抗性オープン故障のテスト生成法の評価2017
- Author(s)
  錦織誠・山崎紘史・・細川利典・吉村正義・新井雅之・四柳浩之・橋爪正樹
- Organizer
  第76回FTC研究会
- Place of Presentation
  ANAホリディ・インリゾート宮崎
- Year and Date
  2017-01-19
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] A Diagnostic Fault Simulation Method for a Single Universal Logical Fault Model2017
- Author(s)
  Toshinori Hosokawa, Hideyuki Takano, Hiroshi Yamazaki, and Koji Yamazaki
- Organizer
  2017 IEEE 22nd Pacific Rim International Symposium on Dependable Computing
- Place of Presentation
  Christchurch, New Zealand
- Year and Date
  2017-01-22
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] A Hardware Trojan Circuit Detection Method Using Activation Sequence Generations2017
- Author(s)
  Masayoshi YOSHIMURA, Tomohiro BOUYASHIKI, and Toshinori HOSOKAWA
- Organizer
  2017 IEEE 22nd Pacific Rim International Symposium on Dependable Computing
- Place of Presentation
  Christchurch, New Zealand
- Year and Date
  2017-01-22
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] 故障励起条件解析を用いたユニバーサル論理故障診断のための被疑故障ランキング法2016
- Author(s)
  高野秀之・細川利典・山崎紘史・山崎浩二
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  機械振興会館（東京都・港区）
- Year and Date
  2016-02-17
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] テスト容易化機能的時間展開モデル生成のためのバインディング法2016
- Author(s)
  佐藤護・増田哲也・西間木淳・細川利典・藤原秀雄
- Organizer
  第75回FTC研究会
- Place of Presentation
  群馬県伊香保温泉
- Year and Date
  2016-07-14
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] テスト容易化機能的時間展開モデル生成のためのテスト容易化バインディング法2016
- Author(s)
  佐藤護・増田哲也・西間木淳・細川利典・藤原秀雄
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  東京都機械振興会館
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] キャプチャセーフテスト圧縮法2016
- Author(s)
  日下部建斗・平井淳士・細川利典・山崎紘史・新井雅之
- Organizer
  第74回FTC研究会
- Place of Presentation
  国民宿舎みやじま杜の宿（広島県・廿日市）
- Year and Date
  2016-01-21
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] A Scheduling Method for Hierarchical Testability Based on Test Environment Generation Results2016
- Author(s)
  Jun Nishimaki, Toshinori Hosokawa, Hideo Fujiwara
- Organizer
  21st IEEE European Test Symposium
- Place of Presentation
  Amsterdam, The Netherlands
- Year and Date
  2016-05-24
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] コントローラ拡大とテストポイントを用いたテスト圧縮効率向上のためのテスト容易化設計2016
- Author(s)
  武田俊・大崎直也・細川利典・山崎紘史・吉村正義
- Organizer
  DAシンポジウム2016 －システムとLSIの設計技術－
- Place of Presentation
  石川県山代温泉　ゆのくに天祥
- Year and Date
  2016-09-14
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] A scheduling method for hierarchical testability based on test environment generation results2016
- Author(s)
  Jun Nishimaki, Toshinori Hosokawa, and Hideo Fujiwara
- Organizer
  21st IEEE European Test Symposium
- Place of Presentation
  Amsterdam, The Netherlands
- Year and Date
  2016-05-23
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] A Binding Method to Generate Easily Testable Functional Time Expansion Models2016
- Author(s)
  Mamoru Sato, Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa and Hideo Fujiwara
- Organizer
  IEEE the Seventeenth Workshop on RTL and High Level Testing
- Place of Presentation
  Hiroshima, Japan
- Year and Date
  2016-11-24
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] Strongly Secure Scan Design Using Extended Shift Registers2016
- Author(s)
  Hiroshi Yamazaki, Toshinori Hosokawa and Hideo Fujiwara
- Organizer
  IEEE the Seventeenth Workshop on RTL and High Level Testing
- Place of Presentation
  Hiroshima, Japan
- Year and Date
  2016-11-24
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] 低消費電力指向マルチサイクルキャプチャテスト生成における時間展開数の評価2016
- Author(s)
  山崎紘史・西間木淳・細川利典・吉村正義
- Organizer
  第74回FTC研究会
- Place of Presentation
  国民宿舎みやじま杜の宿（広島県・廿日市）
- Year and Date
  2016-01-21
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] A Design for Testability Method at RTL for Concurrent Operational Unit Testing2016
- Author(s)
  Shun Takeda, Toshinori Hosokawa, Hiroshi Yamazaki and Masayoshi Yoshimura
- Organizer
  IEEE the Seventeenth Workshop on RTL and High Level Testing
- Place of Presentation
  Hiroshima, Japan
- Year and Date
  2016-11-24
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] Studies of High Level Design Aware Test Generation at Gate Level2016
- Author(s)
  Toshinori Hosokawa
- Organizer
  IEEE the Seventeenth Workshop on RTL and High Level Testing
- Place of Presentation
  Hiroshima, Japan
- Year and Date
  2016-11-24
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] テストパターン数削減のためのRTLテストポイント挿入法2016
- Author(s)
  大崎直也・細川利典・山崎紘史・吉村正義
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  機械振興会館（東京都・港区）
- Year and Date
  2016-02-17
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] A Sequence Generation Method to Detect Hardware Trojan Circuits2015
- Author(s)
  Masayoshi Yoshimura, Tomohiro Bouyashiki , Toshinori Hosokawa
- Organizer
  16th IEEE Workshop on RTL and High Level Testing 2015
- Place of Presentation
  Mumbai India
- Year and Date
  2015-11-25
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] 階層テスト容易化高位合成におけるスケジューリングの一手法2015
- Author(s)
  西間木淳・細川利典・藤原秀雄
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  東京都
- Year and Date
  2015-02-13
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] A Binding Method for Hierarchical Testability Using Results of Test Environment Generation2015
- Author(s)
  Jun Nishimaki, Toshinori Hosokawa, Hideo Fujiwara
- Organizer
  DUHDe ; 2nd Workshop on Design Automation for Understanding Hardware Designs
- Place of Presentation
  Grenoble, France
- Year and Date
  2015-03-13
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] コントローラ拡大に基づくデータパスのテスト容易化機能的時間展開モデル生成法2015
- Author(s)
  増田哲也・西間木淳・細川利典・藤原秀雄
- Organizer
  第73回FTC研究会
- Place of Presentation
  椿館（青森県・青森市）
- Year and Date
  2015-07-16
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] マルチサイクルキャプチャテスト集合を用いた単一論理故障の故障診断法の評価2015
- Author(s)
  高野秀之・山崎紘史・細川利典・山崎浩二
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  東京都
- Year and Date
  2015-02-13
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] 静的テスト圧縮のための多重目標故障テスト生成を用いたMバイNアルゴリズム2015
- Author(s)
  原　侑也・山崎紘史・細川利典・吉村正義
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  長崎県勤労福祉会館（長崎県・長崎市）
- Year and Date
  2015-12-01
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] スキャンベース攻撃を考慮した暗号LSIのテスト手法2015
- Author(s)
  吉村正義・西間木淳・細川利典
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  東京都
- Year and Date
  2015-02-13
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] BASTにおけるスキャンスライスに基づくテストデータ削減法2015
- Author(s)
  錦織　誠・山崎紘史・細川利典・新井雅之・吉村正義
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  機械振興会館（東京都・港区）
- Year and Date
  2015-06-16
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] マルチサイクルキャプチャテスト集合を用いた単一ユニバーサル論理故障モデルの故障診断法2015
- Author(s)
  高野秀之・山崎紘史・細川利典・山崎浩二
- Organizer
  第73回FTC研究会
- Place of Presentation
  椿館（青森県・青森市）
- Year and Date
  2015-07-16
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] 信号非遷移情報に基づくトロイ回路検出法2015
- Author(s)
  坊屋鋪知拓・細川利典・吉村正義
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  東京都
- Year and Date
  2015-02-13
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] A Fault Diagnosis Method for a Single Universal Logical Fault Model Using Multi Cycle CaptureTest Sets2015
- Author(s)
  Hideyuki Takano, Hiroshi Yamazaki, Toshinori Hosokawa, Koji Yamazaki
- Organizer
  16th IEEE Workshop on RTL and High Level Testing
- Place of Presentation
  Mumbai India
- Year and Date
  2015-11-25
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] A Test Generation Method for Data Paths Using Easily Testable Functional Time Expansion Models and Controller Augmentation2015
- Author(s)
  Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa, Hideo Fujiwara
- Organizer
  24th IEEE ASIAN TEST SYMPOSIUM
- Place of Presentation
  Mumbai India
- Year and Date
  2015-11-23
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] Don’t Care Filling Method to Reduce Capture Power based on Correlation of FF Transitions2015
- Author(s)
  Masayoshi Yoshimura, Yoshiyasu Takahashi, Hiroshi Yamazaki, Toshinori Hosokawa
- Organizer
  24th IEEE ASIAN TEST SYMPOSIUM
- Place of Presentation
  Mumbai India
- Year and Date
  2015-11-23
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] VLSI設計工程時における未遷移信号線情報に基づいたトロイ回路検出法2015
- Author(s)
  坊屋鋪知拓，細川利典，吉村正義
- Organizer
  情報処理学会　DAシンポジウム2015
- Place of Presentation
  ゆのくに天祥（石川県・加賀市）
- Year and Date
  2015-08-26
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] テスト環境生成結果を用いた階層テスト容易化バインディング法2014
- Author(s)
  西間木　淳・細川利典・藤原秀雄
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  東京都
- Year and Date
  2014-06-20
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] 機能的k時間展開モデルのテスト容易性評価2014
- Author(s)
  増田哲也・西間木　淳・細川利典・藤原秀雄
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  東京都
- Year and Date
  2014-06-20
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] 自己組織化マップを用いた低消費電力テストパターンの分類と生成について
- Author(s)
  平井淳士，細川利典，山内ゆかり，新井雅之
- Organizer
  第71回FTC研究会
- Place of Presentation
  東京都
- Year and Date
  2014-07-17 – 2014-07-19
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] A Multi Cycle Capture Test Generation Method for Low Capture Power Dissipation
- Author(s)
  Hiroshi Yamazaki, Jun Nishimaki, Toshinori Hosokawa, Masayoshi Yoshimura
- Organizer
  Designing with Uncertainty
- Place of Presentation
  Grenoble, France
- Year and Date
  2015-03-13 – 2015-03-15
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] テスト環境生成結果を用いた階層テスト容易化スケジューリング法
- Author(s)
  西間木淳，細川利典，藤原秀雄
- Organizer
  第７２回FTC研究会
- Place of Presentation
  熊本県
- Year and Date
  2015-01-22 – 2015-01-24
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] キャプチャ消費電力削減のためのマルチサイクルキャプチャテスト生成法
- Author(s)
  山崎紘史・西間木淳・細川利典・吉村正義
- Organizer
  電子情報通信学会デザインガイア2014
- Place of Presentation
  大分県
- Year and Date
  2014-11-26 – 2014-11-28
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] キャプチャセーフテストベクトルを利用した低消費電力テスト生成法
- Author(s)
  平井淳士・細川利典・山内ゆかり・新井雅之
- Organizer
  電子情報通信学会デザインガイア2014
- Place of Presentation
  大分県
- Year and Date
  2014-11-26 – 2014-11-28
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] A Low Capture Power Test Generation Method Using Capture Safe Test Vectors
- Author(s)
  Atsushi Hirai, Toshinori Hosokawa, Yukari Yamauchi, Masayuki Arai
- Organizer
  20th IEEE European Test Symposium
- Place of Presentation
  Cluj-Napoca, Romania
- Year and Date
  2015-05-25 – 2015-05-29
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] A Scheduling Method for Hierarchical Testability Using Results of Test Environment Generation
- Author(s)
  Jun Nishimaki, Toshinori Hosokawa, Hideo Fujiwara
- Organizer
  The Fifteen Workshop on RTL and High Level Testing
- Place of Presentation
  Hangzhou, Chaina
- Year and Date
  2014-11-19 – 2014-11-20
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] 遷移故障テスト集合を用いた抵抗性ブリッジ故障検出率向上指向テスト生成法
- Author(s)
  北尾隆，山崎紘史，細川利典，吉村正義
- Organizer
  第７２回FTC研究会
- Place of Presentation
  熊本県
- Year and Date
  2015-01-22 – 2015-01-24
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] 順序回路におけるテスト不可能故障判定法の評価
- Author(s)
  秋山正碩，山崎紘史，細川利典，吉村正義
- Organizer
  第７２回FTC研究会
- Place of Presentation
  熊本県
- Year and Date
  2015-01-22 – 2015-01-24
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] キャプチャ消費電力削減のためのテストポイント挿入法
- Author(s)
  髙橋慶安・山崎紘史・細川利典・吉村正義
- Organizer
  電子情報通信学会デザインガイア2014
- Place of Presentation
  大分県
- Year and Date
  2014-11-26 – 2014-11-28
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] マルチサイクルキャプチャテストの消費電力評価
- Author(s)
  山崎紘史，西間木淳，細川利典，吉村正義，山崎浩二
- Organizer
  第71回FTC研究会
- Place of Presentation
  東京都
- Year and Date
  2014-07-17 – 2014-07-19
- Data Source
  KAKENHI-PROJECT-26330071
[Presentation] A Simulation Based Low Capture Power Test Generation Method Using Capture Safe Test Vectors
- Author(s)
  Atsushi Hirai, Toshinori Hosokawa, Yukari Yamauchi, Masayuki Arai
- Organizer
  The Fifteen Workshop on RTL and High Level Testing
- Place of Presentation
  Hangzhou, Chaina
- Year and Date
  2014-11-19 – 2014-11-20
- Data Source
  KAKENHI-PROJECT-26330071

1. Yoshimura Masayoshi (90452820)

# of Collaborated Projects: 3 results

# of Collaborated Products: 51 results
2. FUJIWARA Hideo

# of Collaborated Projects: 1 results

# of Collaborated Products: 15 results
3. MIYASE Kohei

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
4. YAMAZAKI Hiroshi

# of Collaborated Projects: 1 results

# of Collaborated Products: 23 results
5. MATSUNAGA Yusuke

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
6. YOTSUYANAGI Hiroyuki

# of Collaborated Projects: 1 results

# of Collaborated Products: 2 results

Hosokawa Toshinori 細川 利典

細川 利典 ホソカワ トシノリ

HOSOKAWA Toshinori 細川 利典

Research Projects

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Co-Researchers

Design technology for detecting IP core piracy

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Research on LSI design methods to identify Trojan circuits in IP cores

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Studies on Non-Scan based Synthesis for Testability and Test Generation from High-Level Design for LSIsPrincipal Investigator

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[Journal Article] CRLock: A SAT and FALL Attacks Resistant Logic Locking Method for Controller at Register Transfer Level2024

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[Journal Article] A Test Register Assignment Method Based on Controller Augmentation to Reduce the Number of Test Patterns2018

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[Journal Article] A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification2018

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[Journal Article] A Capture Safe Static Test Compaction Method Based on Don't Cares2018

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[Presentation] An Evaluation of a Testability Measure for State Assignment to Estimate Transition Fault Coverage for Controllers2023

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[Presentation] A Block Partitioning Method for Region Exhaustive Test to Reduce the Number of Test Patterns and Improve Gate Exhaustive Fault Coverage2023

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[Presentation] An Evaluation of Estimated Field Random Testability for Data Paths at Register Transfer Level Using Status Signal Sequences Based on k-Consecutive State Transitions for Field Testing2023

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[Presentation] CRLock: A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level2022

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[Presentation] CRLock: A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level2022

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[Presentation] 論理故障テスト並列化のための制御信号のドントケア割当て法2022

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[Presentation] 無効状態を含んだコントローラの遷移故障検出率向上指向状態割当て法2022

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[Presentation] レジスタ転送レベルにおける非スキャンベースフィールドテスタビリティに基づく制御信号のドントケア割当て法2021

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[Presentation] A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level2021

Hosokawa Toshinori 細川利典

細川利典ホソカワトシノリ

HOSOKAWA Toshinori 細川利典