MATSUMOTO Takeshi 松本剛史

Researcher Number	40536140
Other IDs
Affiliation (Current)	2025: 石川工業高等専門学校, 電子情報工学科, 准教授
Affiliation (based on the past Project Information) *help	2018 – 2023: 石川工業高等専門学校, 電子情報工学科, 准教授 2015 – 2017: 石川工業高等専門学校, その他部局等, 准教授 2011 – 2014: 東京大学, 大規模集積システム設計教育研究センター, 助教
Review Section/Research Field	Principal Investigator Computer system / Basic Section 09070:Educational technology-related / Computer system/Network Except Principal Investigator Computer system/Network
Keywords	Principal Investigator 回路検証 / 回路デバッグ / 形式的検証 / 工学教育 / 回路実験 / 検証カバレッジ / 機能検証 / プロパティ検証 / FPGA / 回路検証・デバッグ … More / デバッグ支援 / 論理修正 / FPGA設計 / 高位設計 / システムレベル設計 / 等価性検証 … More Except Principal Investigator デバッグ支援技術 / ストリーム処理化 / ハイパフォーマンスコンピューティング / 自動設計修復 / メモリベース計算 / 多重表引 / 高性能計算 / 設計自動修復 / ストリーム処理 / 組み込みシステム / 検証・デバッグ / 組込みシステム / プログラム解析 / 論理関数解析 / 差異抽出 / 設計デバッグ / 設計自動合成 / 形式的解析 Less

回路分野の学生実験における検証・デバッグ技術の活用による高度化・効率化Principal Investigator
- Principal Investigator
  
  松本剛史
- Project Period (FY)
  2020 – 2024
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 09070:Educational technology-related
- Research Institution
  Ishikawa National College of Technology
Development of Coverage Metric for Formal Property VerificationPrincipal Investigator
- Principal Investigator
  
  Matsumoto Takeshi
- Project Period (FY)
  2017 – 2020
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system
- Research Institution
  Ishikawa National College of Technology
Efficient FPGA Circuit Modification for Specification Change and Design DebugPrincipal Investigator
- Principal Investigator
  
  Matsumoto Takeshi
- Project Period (FY)
  2015 – 2017
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Computer system
- Research Institution
  Ishikawa National College of Technology
Logic verification and synthesis based on difference analysis
- Principal Investigator
  
  FUJITA Masahiro
- Project Period (FY)
  2012 – 2014
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  The University of Tokyo
Automatic correction of hardware systems based on stream processing
- Principal Investigator
  
  FUJITA Masahiro
- Project Period (FY)
  2012 – 2013
- Research Category
  
  Grant-in-Aid for Challenging Exploratory Research
- Research Field
  
  Computer system/Network
- Research Institution
  The University of Tokyo
Equivalence Checking for System-Level Designs Having Different Input-Output TimingsPrincipal Investigator
- Principal Investigator
  
  MATSUMOTO Takeshi
- Project Period (FY)
  2011 – 2012
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Computer system/Network
- Research Institution
  The University of Tokyo

All 2021 2020 2019 2018 2017 2016 2014 2013 2012 2011

All Journal Article Presentation

[Journal Article] CPU作成実験における効率的な回路デバッグ環境の構築2021
- Author(s)
  尾山敬典, 西村美紀子, 松本剛史
- Journal Title
  
  石川工業高等専門学校紀要
  
  Volume: 53 Pages: 17-22
- NAID
  130008095746
- Open Access
- Data Source
  KAKENHI-PROJECT-20K03114
[Journal Article] SAT-based automatic rectification and debugging of combinational circuits with LUT insertions2014
- Author(s)
  S. Jo, T. Matsumoto, and M. Fujita
- Journal Title
  
  IPSJ Transactions on System LSI Design Methodology
  
  Volume: Vol.7, February Issue Pages: 46-55
- NAID
  130003394413
- Data Source
  KAKENHI-PROJECT-24650019
[Journal Article] SAT-based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions2014
- Author(s)
  S. Jo, T. Matsumoto, M. Fujita
- Journal Title
  
  IPSJ Transactions on System LSI Design Methodology
  
  Volume: 7 Issue: 0 Pages: 46-55
- DOI
  10.2197/ipsjtsldm.7.46
- NAID
  130003394413
- ISSN
  1882-6687
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23700051, KAKENHI-PROJECT-24300015, KAKENHI-PROJECT-24650019
[Presentation] ブレッドボード回路の設計・作成支援ツールの開発2021
- Author(s)
  尾山敬典, 松本剛史
- Organizer
  令和3年度電気・情報関係学会北陸支部連合大会
- Data Source
  KAKENHI-PROJECT-20K03114
[Presentation] プロパティ検証における検証カバレッジの定義と評価2020
- Author(s)
  河上悠輝, 松本剛史
- Organizer
  令和元年度北陸地区学生による研究発表会
- Data Source
  KAKENHI-PROJECT-17K00089
[Presentation] 学生実験用CPU回路のデバッグ支援に関する研究2019
- Author(s)
  道畑萌絵, 松本剛史
- Organizer
  平成30年度北陸地区学生による研究発表会
- Data Source
  KAKENHI-PROJECT-17K00089
[Presentation] FPGAが搭載されたSoC上での画像処理の実装と評価2018
- Author(s)
  山元美奈, 松本剛史
- Organizer
  平成29年度北陸地区学生による研究発表会
- Data Source
  KAKENHI-PROJECT-17K00089
[Presentation] SAT問題への定式化によるブレッドボード回路の自動配線2018
- Author(s)
  山本巧, 松本剛史
- Organizer
  平成29年度北陸地区学生による研究発表会
- Data Source
  KAKENHI-PROJECT-17K00089
[Presentation] SATソルバーを用いた論理回路における設計誤りの特定と修正2018
- Author(s)
  内井明日香, 松本剛史
- Organizer
  平成29年度北陸地区学生による研究発表会
- Data Source
  KAKENHI-PROJECT-15K15963
[Presentation] 論理関数推定に基づく回路内依存関係の解析2017
- Author(s)
  桶作雄輝, 松本剛史
- Organizer
  平成28年度北陸地区学生による研究発表会
- Place of Presentation
  福井工業高等専門学校（福井県鯖江市）
- Data Source
  KAKENHI-PROJECT-15K15963
[Presentation] 高位設計に対する検証・デバッグ技術2016
- Author(s)
  松本剛史
- Organizer
  電子情報通信学会リコンフィギャラブルシステム研究会
- Place of Presentation
  富山大学（富山県富山市）
- Invited
- Data Source
  KAKENHI-PROJECT-15K15963
[Presentation] 高位合成されたFPGA回路において設計変更がもたらす差分の評価2016
- Author(s)
  石田光洋, 松本剛史
- Organizer
  平成27年度北陸地区学生による研究発表会
- Place of Presentation
  石川工業高等専門学校（石川県河北郡）
- Year and Date
  2016-03-08
- Data Source
  KAKENHI-PROJECT-15K15963
[Presentation] 配置配線を必要としないFPGA再合成手法2016
- Author(s)
  土井瑛平, 松本剛史
- Organizer
  平成27年度北陸地区学生による研究発表会
- Place of Presentation
  石川工業高等専門学校（石川県河北郡）
- Year and Date
  2016-03-08
- Data Source
  KAKENHI-PROJECT-15K15963
[Presentation] プログラム可能データパスとSMT ソルバーを利用した高位設計デバッグ手法2014
- Author(s)
  松本剛史, 城怜史, 藤田昌宏
- Organizer
  組込み技術とネットワークに関するワークショップETNET2014
- Place of Presentation
  石垣, 沖縄
- Year and Date
  2014-03-15
- Data Source
  KAKENHI-PROJECT-23700051
[Presentation] アサーション自動生成とそのシミュレーションによる完全検証2014
- Author(s)
  藤田昌宏, 城怜史, 松本剛史
- Organizer
  組込技術とネットワークに関するワークショップ(ETNET2014)
- Data Source
  KAKENHI-PROJECT-24650019
[Presentation] アサーション自動生成とそのシミュレーションによる完全検証2014
- Author(s)
  藤田昌宏, 城怜史, 松本剛史
- Organizer
  組込み技術とネットワークに関するワークショップ ETNET2014
- Place of Presentation
  ICT文化センター, 沖縄
- Data Source
  KAKENHI-PROJECT-24650019
[Presentation] プログラム可能データパスとSMTソルバーを利用した高位設計デバッグ手法2014
- Author(s)
  松本剛史, 城怜史, 藤田昌宏
- Organizer
  組込み技術とネットワークに関するワークショップ ETNET2014
- Place of Presentation
  ICT文化ホール, 沖縄
- Data Source
  KAKENHI-PROJECT-23700051
[Presentation] プログラム可能データパスとSMTソルバーを利用した高位設計デバッグ手法2014
- Author(s)
  松本剛史, 城怜史, 藤田昌宏
- Organizer
  組込技術とネットワークに関するワークショップ(ETNET2014)
- Data Source
  KAKENHI-PROJECT-24650019
[Presentation] A Debugging Method for Gate Level Circuit Designs by Introducing Programmability2013
- Author(s)
  K. Oshima, T. Matsumoto, and M. Fujita
- Organizer
  Proc. of 21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'13)
- Data Source
  KAKENHI-PROJECT-24650019
[Presentation] Debugging Processors with Advanced Features by Reprogramming LUTs on FPGA2013
- Author(s)
  Satoshi Jo, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita
- Organizer
  International Conference on Field-Programmable Technology
- Place of Presentation
  京都リサーチパーク, 京都
- Data Source
  KAKENHI-PROJECT-23700051
[Presentation] Hardware Implementation of BLTL Property Checkers for Acceleration of Statistical Model Checking2013
- Author(s)
  K. Oshima, T. Matsumoto, and M. Fujita
- Organizer
  Proc. of the International Conference on Computer-Aided Design (ICCAD'13)
- Data Source
  KAKENHI-PROJECT-24650019
[Presentation] Debugging Processors with Advanced Features by Reprogramming LUTs on FPGA2013
- Author(s)
  S. Jo, A.M. Gharehbaghi, T. Matsumoto, and M. Fujita
- Organizer
  Proc. of the International Conference on Field-Programmable Technology (ICFPT)
- Data Source
  KAKENHI-PROJECT-24650019
[Presentation] Partial synthesis through sampling with and without specification2013
- Author(s)
  M. Fujita, S. Jo, S. Ono, and T. Matsumoto
- Organizer
  Proc. of the International Conference on Computer-Aided Design (ICCAD'13)
- Data Source
  KAKENHI-PROJECT-24650019
[Presentation] FOF: Functionally Observable Fault and its ATPG Techniques2013
- Author(s)
  Masahiro Fujita, Takeshi Matsumoto, Satoshi Jo
- Organizer
  21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC '13)
- Place of Presentation
  Istanbul, Turkey
- Data Source
  KAKENHI-PROJECT-24650019
[Presentation] Partial synthesis through sampling with and without specification2013
- Author(s)
  Masahiro Fujita, Satoshi Jo, Shohei Ono, Takeshi Matsumoto
- Organizer
  International Conference on Computer-Aided Design (ICCAD '13)
- Place of Presentation
  San Jose, USA
- Data Source
  KAKENHI-PROJECT-24650019
[Presentation] FOF: Functionally Observable Fault and its ATPG Techniques2013
- Author(s)
  Masahiro Fujita, Takeshi Matsumoto, Satoshi Jo
- Organizer
  21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC '13)
- Place of Presentation
  Istanbul, Turkey
- Data Source
  KAKENHI-PROJECT-24300015
[Presentation] A Debugging Method for Gate Level Circuit Designs by Introducing Programmability2013
- Author(s)
  Kousuke Oshima, Takeshi Matsumoto, Masahiro Fujita
- Organizer
  21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC '13)
- Place of Presentation
  Istanbul, Turkey
- Data Source
  KAKENHI-PROJECT-24300015
[Presentation] A debugging method for gate level circuit designs by introducing programmability2013
- Author(s)
  K. Oshima, T. Matsumoto, M. Fujita
- Organizer
  IFIP/IEEE 21st International Confer- ence on Very Large Scale Integration and System-on-Chip
- Place of Presentation
  Istanbul, Turkey
- Data Source
  KAKENHI-PROJECT-23700051
[Presentation] Hardware Implementation of BLTL Property Checkers for Acceleration of Statistical Model Checking2013
- Author(s)
  Kousuke Oshima, Takeshi Matsumoto, Masahiro Fujita
- Organizer
  International Conference on Computer-Aided Design (ICCAD '13)
- Place of Presentation
  San Jose, USA
- Data Source
  KAKENHI-PROJECT-24650019
[Presentation] Partial synthesis through sampling with and without specification2013
- Author(s)
  Masahiro Fujita, Satoshi Jo, Shohei Ono, Takeshi Matsumoto
- Organizer
  International Conference on Computer-Aided Design (ICCAD '13)
- Place of Presentation
  San Jose, USA
- Data Source
  KAKENHI-PROJECT-24300015
[Presentation] A Debugging Method for Gate Level Circuit Designs by Introducing Programmability2013
- Author(s)
  Kousuke Oshima, Takeshi Matsumoto, Masahiro Fujita
- Organizer
  21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC '13)
- Place of Presentation
  Istanbul, Turkey
- Data Source
  KAKENHI-PROJECT-24650019
[Presentation] FOF : Functionally Observable Fault and its ATPG techniques2013
- Author(s)
  M. Fujita, T. Matsumoto, S. Jo
- Organizer
  IFIP/IEEE 21st International Conference on Very Large Scale Integration and System-on-Chip
- Place of Presentation
  Istanbul, Turkey
- Data Source
  KAKENHI-PROJECT-23700051
[Presentation] Automatic Assertion Extraction in Gate-Level Simulation Using GPGPUs2012
- Author(s)
  Shohei Ono, Takeshi Matsumoto, Masahiro Fujita
- Organizer
  IEEE 30th International Conference on Computer Design
- Place of Presentation
  Montreal, Canada
- Data Source
  KAKENHI-PROJECT-24650019
[Presentation] 論理関数の充足不可能性に注目した論理回路デバッグ手法の検討2012
- Author(s)
  李在城, 松本剛史, 藤田昌宏
- Organizer
  組込み技術とネットワークに関するワークショップETNET2012
- Place of Presentation
  松島, 宮城
- Year and Date
  2012-03-02
- Data Source
  KAKENHI-PROJECT-23700051
[Presentation] An Efficient Method to Localize and Correct Bugs in High-Level Designs Using Counterexamples and Potential Dependence2012
- Author(s)
  Takeshi Matsumoto, Shohei Ono, Masahiro Fujita
- Organizer
  IEEE/IFIP 20th International Symposium on Very Large Scale Integration
- Place of Presentation
  Santa Cruz, USA
- Data Source
  KAKENHI-PROJECT-23700051
[Presentation] Automatic Assertion Extraction in Gate-Level Simulation Using GPGPUs2012
- Author(s)
  S. Ono, T. Matsumoto, and M. Fujita
- Organizer
  Proc. of IEEE 30th International Conference on Computer Design
- Data Source
  KAKENHI-PROJECT-24650019
[Presentation] An Efficient Method to Localize Correct Bugs in High-Level Designs Using Counterexamples and Potential Dependence2012
- Author(s)
  T. Matsumoto, S. Ono, M. Fujita
- Organizer
  IEEE/IFIP 20th International Symposium on Very Large Scale Integration
- Place of Presentation
  Santa Cruz, USA
- Data Source
  KAKENHI-PROJECT-23700051
[Presentation] SAT-based automatic rectification and debugging of combinational circuits with LUT insertions2012
- Author(s)
  Satoshi Jo, Takeshi Matsumoto, Masahiro Fujita
- Organizer
  IEEE 21st Asia Test Symposium
- Place of Presentation
  朱鷺メッセ, 新潟
- Data Source
  KAKENHI-PROJECT-24300015
[Presentation] SAT-based automatic rectification and debugging of combinational circuits with LUT insertions2012
- Author(s)
  Satoshi Jo, Takeshi Matsumoto, Masahiro Fujita
- Organizer
  IEEE 21st Asia Test Symposium
- Place of Presentation
  新潟県朱鷺メッセ新潟コンベンションセンター
- Data Source
  KAKENHI-PROJECT-24650019
[Presentation] 論理関数の充足不可能性に注目した論理回路デバッグ手法の検討2012
- Author(s)
  李在城, 松本剛史, 藤田昌宏
- Organizer
  組込み技術とネットワークに関するワークショップ ETNET2012
- Place of Presentation
  松島
- Data Source
  KAKENHI-PROJECT-23700051
[Presentation] SAT-based automatic rectification and debugging of combinational circuits with LUT insertions2012
- Author(s)
  S. Jo, T. Matsumoto, and M. Fujita
- Organizer
  Proc. of IEEE 21st Asia Test Symposium
- Data Source
  KAKENHI-PROJECT-24650019
[Presentation] Automatic Assertion Extraction in Gate-Level Simulation Using GPGPUs2012
- Author(s)
  S. Ono, T. Matsumoto, M. Fujita
- Organizer
  IEEE 30th International Conference on Computer Design
- Place of Presentation
  Montreal, Canada
- Data Source
  KAKENHI-PROJECT-23700051
[Presentation] 反例と設計分割に基づく高位設計に対する効率的な設計修正支援手法2011
- Author(s)
  原田裕基, 松本剛史, 藤田昌宏
- Organizer
  第150回システムLSI設計技術研究会
- Place of Presentation
  北九州
- Data Source
  KAKENHI-PROJECT-23700051

1. FUJITA Masahiro (70323524)

# of Collaborated Projects: 2 results

# of Collaborated Products: 20 results

MATSUMOTO Takeshi 松本 剛史

Research Projects

Research Products

Co-Researchers

回路分野の学生実験における検証・デバッグ技術の活用による高度化・効率化Principal Investigator

Principal Investigator

Project Period (FY)

Research Category

Review Section

Research Institution

Development of Coverage Metric for Formal Property VerificationPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Efficient FPGA Circuit Modification for Specification Change and Design DebugPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Logic verification and synthesis based on difference analysis

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Automatic correction of hardware systems based on stream processing

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Equivalence Checking for System-Level Designs Having Different Input-Output TimingsPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

[Journal Article] CPU作成実験における効率的な回路デバッグ環境の構築2021

Author(s)

Journal Title

NAID

Data Source

[Journal Article] SAT-based automatic rectification and debugging of combinational circuits with LUT insertions2014

Author(s)

Journal Title

NAID

Data Source

[Journal Article] SAT-based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions2014

Author(s)

Journal Title

DOI

NAID

ISSN

Language

Data Source

[Presentation] ブレッドボード回路の設計・作成支援ツールの開発2021

Author(s)

Organizer

Data Source

[Presentation] プロパティ検証における検証カバレッジの定義と評価2020

Author(s)

Organizer

Data Source

[Presentation] 学生実験用CPU回路のデバッグ支援に関する研究2019

Author(s)

Organizer

Data Source

[Presentation] FPGAが搭載されたSoC上での画像処理の実装と評価2018

Author(s)

Organizer

Data Source

[Presentation] SAT問題への定式化によるブレッドボード回路の自動配線2018

Author(s)

Organizer

Data Source

[Presentation] SATソルバーを用いた論理回路における設計誤りの特定と修正2018

Author(s)

MATSUMOTO Takeshi 松本剛史