Holst Stefan ＨｏｌｓｔＳｔｅｆａｎ

… Alternative Names

HOLST Stefan ホルストシュテファン

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Researcher Number	40710322
Other IDs
Affiliation (Current)	2025: 九州工業大学, 大学院情報工学研究院, 准教授
Affiliation (based on the past Project Information) *help	2021 – 2024: 九州工業大学, 大学院情報工学研究院, 准教授 2013 – 2020: 九州工業大学, 大学院情報工学研究院, 助教
Review Section/Research Field	Principal Investigator Basic Section 60040:Computer system-related Except Principal Investigator Computer system / Basic Section 60040:Computer system-related
Keywords	Principal Investigator Failure Analysis / GPU Computing / Soft-Error Tolerance / Process Variations / Response Compression / IR-Drop / Small-Delay Defects / Logic Diagnosis / VLSI Except Principal Investigator IR-Drop … More / シフトエラー / シフト電力 / LSI回路 / 誤テスト / テスト電力 / スキャンテスト / LSIテスト / 欠陥検出設計 / 欠陥影響最小化設計 / 欠陥影響定量化 / 欠陥 / 耐ソフトエラー記憶素子 / ディペンダブル・コンピュー / ディペンダブル・コンピュータ / グルーピング / テストクロック / シフトタイミング / ディペンダブル・コンピューティング / 電子デバイス・機器 / 計算機システム / クロックパス / パス遅延 / 信号値遷移 / 誤テスト回避 / テスト電力制御 / クロック / マスク回路 / 入力遷移 / テスト電力安全性 / テスト生成 / 低電力テスト / テストデータ変更 / クロックストレッチ / IR-Dop / キャプチャ電力 Less

Research on Defect-Aware Soft-Error Mitigation for Reliable LSIs
- Principal Investigator
  
  温暁青
- Project Period (FY)
  2021 – 2024
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Kyushu Institute of Technology
Interactive Logic Diagnosis of Unpredicted Defects in Logic CircuitsPrincipal Investigator
- Principal Investigator
  
  Holst Stefan
- Project Period (FY)
  2018 – 2019
- Research Category
  
  Grant-in-Aid for Early-Career Scientists
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Kyushu Institute of Technology
Shift-Power-Safe Scan Test Methodology for High-Quality Low-Power LSI Circuits
- Principal Investigator
  
  Wen Xiaoqing
- Project Period (FY)
  2017 – 2020
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system
- Research Institution
  Kyushu Institute of Technology
Research on High-Quality Test Method for Avoiding False Testing of Next-Generation Low-Power LSIs
- Principal Investigator
  
  Wen Xiaoqing
- Project Period (FY)
  2015 – 2017
- Research Category
  
  Grant-in-Aid for Challenging Exploratory Research
- Research Field
  
  Computer system
- Research Institution
  Kyushu Institute of Technology
Research on Extra-Low-Power Self-Test for LSI Circuits in Implantable Medical Devices
- Principal Investigator
  
  WEN XIAOQING
- Project Period (FY)
  2013 – 2017
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system
- Research Institution
  Kyushu Institute of Technology

All 2023 2022 2021 2020 2019 2018 2017 2016 2015 Other

All Journal Article Presentation

[Journal Article] GPU-Accelerated Estimation and Targeted Reduction of Peak IR-Drop during Scan Chain Shifting2023
- Author(s)
  S. Shi, S. Holst, and X. Wen
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: E106.D Issue: 10 Pages: 1694-1704
- DOI
  10.1587/transinf.2023EDP7011
- ISSN
  0916-8532, 1745-1361
- Year and Date
  2023-10-01
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23K21653
[Journal Article] Evaluation and Test of Production Defects in Hardened Latches2022
- Author(s)
  R. Ma, S. Holst, X. Wen, A. Yan, and H. Xu
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: E105.D Issue: 5 Pages: 996-1009
- DOI
  10.1587/transinf.2021EDP7216
- ISSN
  0916-8532, 1745-1361
- Year and Date
  2022-05-01
- Language
  English
- Peer Reviewed / Open Access / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21653
[Journal Article] Probability of Switching activity to Locate Hotspots in Logic Circuits2021
- Author(s)
  Y. Zhang, S. Holst, X. Wen, K. Miyase, S. Kajihara, J. Qian
- Journal Title
  
  IEICE Trans. on Inf. & Syst.
  
  Volume: E104-D
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Journal Article] Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation2016
- Author(s)
  F. Li, X. Wen, K. Miyase, S. Holst, S. Kajihara
- Journal Title
  
  IEICE Trans. Fundamentals
  
  Volume: E99.A Issue: 12 Pages: 2310-2319
- DOI
  10.1587/transfun.E99.A.2310
- NAID
  130005170516
- ISSN
  0916-8508, 1745-1337
- Language
  English
- Peer Reviewed / Acknowledgement Compliant / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280016, KAKENHI-PROJECT-15K12003, KAKENHI-PROJECT-15K12004
[Presentation] Mitigating Test-Induced Yield-Loss by IR-Drop-Aware X-Filling2023
- Author(s)
  S. Shi, S. Holst, and X. Wen
- Organizer
  The 16th IEEE Int`l Symp. on Embedded Milticore/Many-core Systems-on-Chip
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21653
[Presentation] BiSTAHL: A Built-In Self-Testable Soft-Error-Hardened Scan-Cell2023
- Author(s)
  S. Holst, R. Ma, X. Wen, A. Yan, and H. Xu
- Organizer
  IEEE European Test Symp.
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21653
[Presentation] Estimation and Reduction of Peak IR-Drop in Scan Shift2022
- Author(s)
  S. Shi, S. Holst, and X. Wen
- Organizer
  the 10th Int'l Symp. on Applied Engineering and Sciences
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21653
[Presentation] Functional Safety of AI Accelerators with Hardware Defects2022
- Author(s)
  B. Lim, S. Holst, X. Wen
- Organizer
  第13回LSIテストセミナー
- Data Source
  KAKENHI-PROJECT-23K21653
[Presentation] Functional Safety of AI Accelerators with Hardware Defects2021
- Author(s)
  S. Holst, B. Lim, X. Wen
- Organizer
  The 9th Int'l Symp. on Applied Engineering and Sciences
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21653
[Presentation] GPU-Accelerated Timing Simulation of Systolic Array Based AI Accelerators2021
- Author(s)
  S. Holst, B. Lim, X. Wen
- Organizer
  IEEE Asian Test Symp.
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21653
[Presentation] STAHL: A Novel Scan-Test-Aware Hardened Latch2021
- Author(s)
  R. Ma, S. Holst, X. Wen
- Organizer
  The 9th Int'l Symp. on Applied Engineering and Sciences
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21653
[Presentation] A Novel High Performance Scan-Test-Aware Hardened Latch Design2020
- Author(s)
  R. Ma, S. Holst, X. Wen, A. Yan, H. Xu,
- Organizer
  電子情報通信学会技術研究報告, DC2020-71
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] Diagnosing Hidden Delay Defects from Faster-Than-At-Speed Test Responses2020
- Author(s)
  Stefan Holst
- Organizer
  South European Test Seminar 2020, Obergurgl, Austria
- Data Source
  KAKENHI-PROJECT-18K18026
[Presentation] Logic Fault Diagnosis of Hidden Delay Defects2020
- Author(s)
  . Holst, M. Kampmann, A. Sprenger, J. D. Reimer, S. Hellebrand, H.-J. Wunderlich, X. Wen
- Organizer
  Int'l Test Conf.
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] Diagnosing Hidden Delay Defects from Faster-Than-At-Speed Test Responses2020
- Author(s)
  Stefan Holst
- Organizer
  FTC Workshop Jan. 2020, Yurihama, Tottori-ken, Japan
- Data Source
  KAKENHI-PROJECT-18K18026
[Presentation] Accelerated Timing Simulation and Its Applications2019
- Author(s)
  Stefan Holst
- Organizer
  Dagstuhl Workshop "Intelligent Methods for Test and Reliability" Sep. 2019, Dagstuhl, Germany
- Invited
- Data Source
  KAKENHI-PROJECT-18K18026
[Presentation] Variation-Aware Small Delay Fault Diagnosis on Compacted Failure Data2019
- Author(s)
  S. Holst, E. Schneider, M. A. Kochte, X. Wen, H.-J. Wunderlich
- Organizer
  Int'l Test Conf.
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] Small Delay Fault Diagnosis with Compacted Responses2019
- Author(s)
  Stefan Holst
- Organizer
  FTC Workshop Jan. 2019, Kitakyushu-shi, Fukuoka-ken, Japan
- Data Source
  KAKENHI-PROJECT-18K18026
[Presentation] Logic Fault Diagnosis of Hidden Delay Defects2019
- Author(s)
  Stefan Holst
- Organizer
  FTC Workshop Jul. 2019, Daigo-machi, Kuji-gun, Ibaraki-ken, Japan
- Data Source
  KAKENHI-PROJECT-18K18026
[Presentation] Small Delay Fault Diagnosis with Compacted Responses2019
- Author(s)
  Stefan Holst
- Organizer
  South European Test Seminar 2019, St. Leonhard, Pitztal, Austria
- Data Source
  KAKENHI-PROJECT-18K18026
[Presentation] Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption2019
- Author(s)
  Y. Zhang, S. Holst, X. Wen, K. Miyase, S. Kajihara, J. Qian
- Organizer
  第11回LSIテストセミナー
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] Small Delay Fault Diagnosis with Compacted Responses2019
- Author(s)
  Stefan Holst
- Organizer
  56th Design Automation Conference (DAC) 2019 Work-In-Progress Poster
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K18026
[Presentation] Small Delay Fault Diagnosis on Compacted Responses2019
- Author(s)
  S. Holst, E. Schneider, M. A. Kochte, X. Wen, H.-J. Wunderlich
- Organizer
  第80回 FTC 研究会
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] Targeted Partial-Shift For Mitigating Shift Switching Activity Hot-Spots During Scan Test2019
- Author(s)
  S. Holst, S. Shi, and X. Wen
- Organizer
  IEEE Pacific Rim Int'l Symp. on Dependable Computing
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] Variation-Aware Small Delay Fault Diagnosis on Compressed Test Responses2019
- Author(s)
  Stefan Holst
- Organizer
  IEEE International Test Conference, Nov. 2019, Washington DC, USA
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K18026
[Presentation] Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing2018
- Author(s)
  Y. Zhang, X. Wen, S. Holst, K. Miyase, S. Kajihara, H.-J. Wunderlich, J. Qian
- Organizer
  IEEE Asian Test Symposium
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] Interactive Logic Diagnosis of Unpredicted Defects in Logic Circuits2018
- Author(s)
  Stefan Holst
- Organizer
  FTC Workshop Jul. 2018, Sakura-shi, Tochigi-ken, Japan
- Data Source
  KAKENHI-PROJECT-18K18026
[Presentation] The Impact of Production Defects on the Soft-Error Tolerance of Hardened Latches2018
- Author(s)
  S. Holst, R. Ma, X. Wen
- Organizer
  第17 回情報科学技術フォーラム
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] The Impact of Production Defects on the Soft-Error Tolerance of Hardened Latches2018
- Author(s)
  S. Holst, R. Ma, X. Wen
- Organizer
  IEEE European Test Symposium
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption2018
- Author(s)
  Y. Zhang, S. Holst, X. Wen, K. Miyase, S. Kajihara, J. Qian
- Organizer
  第17 回情報科学技術フォーラム
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption2017
- Author(s)
  Y. Zhang, S. Holst, X. Wen, K. Miyase, S. Kajihara, J. Qia
- Organizer
  IEEE Asian Test Symp.
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K12003
[Presentation] Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors2017
- Author(s)
  S. Holst, E. Schneiderz, H. Kawagoe, M. A. Kochtez, K. Miyase, H.-J. Wunderlichz, S. Kajihara, X. Wen
- Organizer
  Proc. of IEEE Int'l Test Conf.
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] 高品質実速度スキャンテスト生成に関する研究2017
- Author(s)
  宮崎俊紀、温暁青、ホルストシュテファン、宮瀬紘平、梶原誠司
- Organizer
  第9回LSIテストセミナー
- Place of Presentation
  福岡市
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] On Avoiding Test Data Corruption by Optimal Scan Chain Grouping2017
- Author(s)
  Y. Zhang, S. Holst, X. Wen, K. Miyase, S. Kajihara, J. Qian
- Organizer
  第181回SLDM・第46回EMB合同研究発表会
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption2017
- Author(s)
  Y. Zhang, S. Holst, X. Wen, K. Miyase, S. Kajihara, J. Qian
- Organizer
  Proc. of IEEE Asian Test Symp.
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors2017
- Author(s)
  S. Holst, E. Schneider, H. Kawagoe, M. A. Kochtez, K. Miyase, H.-J. Wunderlichz, S. Kajihara, X. Wen
- Organizer
  IEEE Int'l Test Conf.
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K12003
[Presentation] Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test2016
- Author(s)
  S. Holst, E. Schneider, X. Wen, S. Kajihara, Y. Yamato, H.-J. Wunderlich, M. A. Kochte
- Organizer
  IEEE Asian Test Symp.
- Place of Presentation
  Hiroshima, Japan
- Year and Date
  2016-11-24
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K12003
[Presentation] Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation2016
- Author(s)
  F. Li, X. Wen, S. Holst, K. Miyase, S. Kajihara
- Organizer
  Int'l Symp. on Applied Engineering and Sciences
- Place of Presentation
  Kitakyushu, Japan
- Year and Date
  2016-12-17
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K12003
[Presentation] Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test2016
- Author(s)
  S. Eggersgluess, S. Holst, D. Tillex, K. Miyase, X. Wen
- Organizer
  IEEE Asian Test Symp.
- Place of Presentation
  Hiroshima, Japan
- Year and Date
  2016-11-21
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At- Speed Scan Test2016
- Author(s)
  S. Holst, E. Schneider, X. Wen, S. Kajihara, Y. Yamato, H.-J. Wunderlich, M. A. Kochte
- Organizer
  IEEE Asian Test Symp.
- Place of Presentation
  Hiroshima, Japan
- Year and Date
  2016-11-21
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation2016
- Author(s)
  F. Li, X. Wen, S. Holst, K. Miyase, S. Kajihara
- Organizer
  Int'l Symp. on Applied Engineering and Sciences
- Place of Presentation
  Kitakyushu, Japan
- Year and Date
  2016-12-17
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test2016
- Author(s)
  S. Eggersgluess, S. Holst, D. Tillex, K. Miyase, X. Wen
- Organizer
  IEEE Asian Test Symp.
- Place of Presentation
  Hiroshima, Japan
- Year and Date
  2016-11-24
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K12003
[Presentation] Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch2015
- Author(s)
  K. Asada, X. Wen, S. Holst, K. Miyase, S. Kajihara, M. A. Kochte, E. Schneider, H.-J. Wunderlich, J. Qian
- Organizer
  IEEE Asian Test Symp.
- Place of Presentation
  Bombay, India
- Year and Date
  2015-11-24
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] A Soft-Error Tolerant TCAM Using Partial Don’t-Care Keys2015
- Author(s)
  I. Syafalni, T. Sasao, X. Wen, S. Holst, K. Miyase
- Organizer
  IEEE European Test Symp.
- Place of Presentation
  Cluj-Napoca, Romania
- Year and Date
  2015-11-05
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] Data-Parallel Switch-Level Simulation for Fast and Accurate Timing Validation of CMOS Circuits
- Author(s)
  E. Schneider, S. Holst, X. Wen, H.-J. Wunderlich
- Organizer
  IEEE International Conference on Computer-Aided Design
- Place of Presentation
  San Jose, USA
- Year and Date
  2014-11-03 – 2014-11-06
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] Data-Parallel Switch-Level Simulation for Fast and Accurate Timing Validation of CMOS Circuits
- Author(s)
  E. Schneider, S. Holst, X. Wen, H.-J. Wunderlich
- Organizer
  Design Automation Conference
- Place of Presentation
  San Francisco, USA
- Year and Date
  2014-06-01 – 2014-06-05
- Data Source
  KAKENHI-PROJECT-25280016

1. WEN XIAOQING (20250897)

# of Collaborated Projects: 4 results

# of Collaborated Products: 34 results
2. 宮瀬紘平 (30452824)

# of Collaborated Projects: 4 results

# of Collaborated Products: 16 results
3. 梶原誠司 (80252592)

# of Collaborated Projects: 4 results

# of Collaborated Products: 15 results
4. Tehranipoor M.

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
5. Girard P.

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
6. KINOSHITA Kozo

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
7. AIKYO Takashi

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
8. TAKAGI Noriaki

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
9. HAMADA Shuji

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
10. HADATE Koji

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
11. Saluja K. K.

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
12. Keller B.

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
13. Varma P.

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
14. Chakravarty K.

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
15. Wunderlich H.-J.

# of Collaborated Projects: 1 results

# of Collaborated Products: 2 results
16. Wang L.-T.

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
17. Jan M. E.

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results

Holst Stefan Ｈｏｌｓｔ Ｓｔｅｆａｎ

HOLST Stefan ホルスト シュテファン

Research Projects

Research Products

Co-Researchers

Research on Defect-Aware Soft-Error Mitigation for Reliable LSIs

Principal Investigator

Project Period (FY)

Research Category

Review Section

Research Institution

Interactive Logic Diagnosis of Unpredicted Defects in Logic CircuitsPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Review Section

Research Institution

Shift-Power-Safe Scan Test Methodology for High-Quality Low-Power LSI Circuits

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Research on High-Quality Test Method for Avoiding False Testing of Next-Generation Low-Power LSIs

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Research on Extra-Low-Power Self-Test for LSI Circuits in Implantable Medical Devices

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

[Journal Article] GPU-Accelerated Estimation and Targeted Reduction of Peak IR-Drop during Scan Chain Shifting2023

Author(s)

Journal Title

DOI

ISSN

Year and Date

Language

Data Source

[Journal Article] Evaluation and Test of Production Defects in Hardened Latches2022

Author(s)

Journal Title

DOI

ISSN

Year and Date

Language

Data Source

[Journal Article] Probability of Switching activity to Locate Hotspots in Logic Circuits2021

Author(s)

Journal Title

Data Source

[Journal Article] Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation2016

Author(s)

Journal Title

DOI

NAID

ISSN

Language

Data Source

[Presentation] Mitigating Test-Induced Yield-Loss by IR-Drop-Aware X-Filling2023

Author(s)

Organizer

Data Source

[Presentation] BiSTAHL: A Built-In Self-Testable Soft-Error-Hardened Scan-Cell2023

Author(s)

Organizer

Data Source

[Presentation] Estimation and Reduction of Peak IR-Drop in Scan Shift2022

Author(s)

Organizer

Data Source

[Presentation] Functional Safety of AI Accelerators with Hardware Defects2022

Author(s)

Organizer

Data Source

[Presentation] Functional Safety of AI Accelerators with Hardware Defects2021

Holst Stefan ＨｏｌｓｔＳｔｅｆａｎ

HOLST Stefan ホルストシュテファン