AMAGASAKI MOTOKI 尼崎太樹

… Alternative Names

AMAGASAKI Motoki 尼崎太樹

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Researcher Number	50467974
Other IDs
Affiliation (Current)	2025: 熊本大学, 大学院先端科学研究部(工), 教授
Affiliation (based on the past Project Information) *help	2022 – 2024: 熊本大学, 大学院先端科学研究部(工), 教授 2018 – 2019: 熊本大学, 大学院先端科学研究部(工), 准教授 2016 – 2017: 熊本大学, 大学院先端科学研究部(工), 助教 2011 – 2015: 熊本大学, 自然科学研究科, 助教 2009 – 2011: Kumamoto University, 大学院・自然科学研究科, 助教
Review Section/Research Field	Principal Investigator Computer system / Basic Section 60040:Computer system-related / Computer system/Network Except Principal Investigator Computer system/Network / Basic Section 60040:Computer system-related
Keywords	Principal Investigator 深層学習 / ニューラルネットワーク / 高速シリアル通信 / リコンフィギャラブルシステム / コンパイラ / 集積回路 / 深層学習週 / エッジAI / NVAR Mixer / DNNコンパイラ … More / ニューラルネットワークチップ / ディープラーニング / 重み2のべき乗化 / リコンフィギャラブル / エッジ端末 / DNNアクセラレータ / AIチップ / 3D FPGA / 3次元FPGA / TSV / face-up / face-down / 3D-FPGA / 自己組織化マップ / アルゴリズム … More Except Principal Investigator リコンフィギャラブルシステム / FPGA / ディペンダブルシステム / MLIR / 自動生成 / 高位合成 / アクセラレータ / ニューラルネットワーク / LSIテスト / ハードエラー回避 / ハードエラー検出 / ディペンダブル・コンピューティング / ハードエラー検出．回避 / 電子デバイス・機器 / ディペンダブル・コンピューティング / LSI試作 / SEU / ソフトエラー / ＦＰＧＡ Less

高位合成を用いた融合型ニューラルネットワークアクセラレータの自動生成
- Principal Investigator
  
  瀬戸謙修
- Project Period (FY)
  2024 – 2026
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Kumamoto University
エッジAIシステム向け設計基盤技術に関する研究Principal Investigator
- Principal Investigator
  
  尼崎太樹
- Project Period (FY)
  2022 – 2024
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Kumamoto University
Neural network LSI for deep learningPrincipal Investigator
- Principal Investigator
  
  Amagasaki Motoki
- Project Period (FY)
  2017 – 2019
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system
- Research Institution
  Kumamoto University
Three dimensional FPGA architecture and its design methodPrincipal Investigator
- Principal Investigator
  
  Amagasaki Motoki
- Project Period (FY)
  2014 – 2016
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Computer system
- Research Institution
  Kumamoto University
A Study of High Dependability Reconfigurable Logic Architecture
- Principal Investigator
  
  IIDA Masahiro
- Project Period (FY)
  2011 – 2013
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Kumamoto University
Development of Self-Repair Dependable system on FPGA
- Principal Investigator
  
  SUEYOSHI Toshinori
- Project Period (FY)
  2010 – 2012
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Kumamoto University
FPGA design method based on self-organization maps.Principal Investigator
- Principal Investigator
  
  AMAGASAKI Motoki
- Project Period (FY)
  2009 – 2011
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Kumamoto University

All 2023 2022 2020 2019 2018 2017 2016 2015 2014 2013 2012 2011 2010 Other

All Journal Article Presentation Patent

[Journal Article] A Lightweight Deep Neural Network Using a Mixer-Type Nonlinear Vector Autoregression2023
- Author(s)
  Diana Mery、Amin Ridhwan、Amagasaki Motoki、Kiyama Masato
- Journal Title
  
  IEEE Access
  
  Volume: 11 Pages: 103544-103553
- DOI
  10.1109/access.2023.3318873
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-22K11956
[Journal Article] `A Deep Neural Network Translator for Edge Site Implementation2023
- Author(s)
  Mery Diana, Masato Kiyama, Motoki Amagasaki, Masayoshi Ito and Yuki Morishita
- Journal Title
  
  Proc. of CANDARW
  
  Volume: CSA93
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22K11956
[Journal Article] A Posit Based Multiply-accumulate Unit with Small Quire Size for Deep Neural Networks2022
- Author(s)
  Yasuhiro Nakahara, Yuta Masuda, Masato Kiyama, Motoki Amagasaki and Masahiro Iida
- Journal Title
  
  IPSJ Transactions on System LSI Design Methodology
  
  Volume: 15 Issue: 0 Pages: 16-19
- DOI
  10.2197/ipsjtsldm.15.16
- ISSN
  1882-6687
- Language
  English
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-22K11956
[Journal Article] EVALUATION OF ROUTING AREA REDUCTION FOR FINE-GRAINED OVERLAY VIRTUAL FPGA2020
- Author(s)
  Theingi Myint, Ito Takanori, Motoki Amagasaki, Qian Zhao, Masahiro Iida
- Journal Title
  
  International Journal of Innovative Computing, Information and Control
  
  Volume: 16 Pages: 0-0
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-17K00083
[Journal Article] A SLM-based Overlay Architecture for Fine-grained Virtual FPGA2020
- Author(s)
  Theingi Myint, Motoki Amagasaki, Qian Zhao, Masahiro Iida
- Journal Title
  
  IEICE Electronics Express (ELEX)
  
  Volume: 16 Pages: 0-0
- NAID
  130007772826
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-17K00083
[Journal Article] SLM: A Scalable Logic Module Architecture with Less Configuration Memory2016
- Author(s)
  M.Amagasaki, R.Araki, M.Iida and T.Sueyoshi
- Journal Title
  
  IEICE Transactions Fundamentals of Electronics, Communications and Computer Sciences
  
  Volume: E99-A Pages: 2500-2506
- NAID
  130005170458
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-26730028
[Journal Article] A 3D FPGA Architecture to Realize Simple Die Stacking2015
- Author(s)
  M.Amagasaki, Q.Zhao, M.Iida, M.Kuga and T.Sueyoshi
- Journal Title
  
  IPSJ Transactions on System LSI Design Methodology
  
  Volume: 8 Pages: 116-122
- NAID
  130005091216
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-26730028
[Journal Article] FPGA PLACEMENT BASED ON SELF-ORGANIZING MAP2015
- Author(s)
  M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi
- Journal Title
  
  International Journal of Innovative Computing, Information and Control
  
  Volume: 11 Pages: 2001-2012
- NAID
  110008899692
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-26730028
[Journal Article] システムLSI搭載FPGA-IPコア向け物理故障検出及び回避手法2013
- Author(s)
  尼崎太樹, 西谷祐樹, 井上万輝, 飯田全広, 久我守弘, 末吉敏則
- Journal Title
  
  信学論D
  
  Volume: Vol.J96-D, No.12 Pages: 3019-3029
- NAID
  40019900178
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23300017
[Journal Article] システムLSI搭載FPGA-IPコア向け物理故障検出及び回避手法2013
- Author(s)
  尼崎太樹，西谷祐樹，井上万輝，飯田全広，久我守弘，末吉敏則
- Journal Title
  
  信学論D
  
  Volume: Vol.J96-D，No.12 Pages: 3019-3029
- NAID
  40019900178
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23300017
[Journal Article] FPGA Design Framework Combined with Commercial VLSI CAD2013
- Author(s)
  Q.Zhao, K.Inoue, M.Amagasaki, M.Iida, M.Kuga, T.Sueyoshi
- Journal Title
  
  IEICE Transactions on Information and Systems
  
  Volume: Vol.E96-D, No.8 Pages: 1602-1612
- NAID
  130003370942
- Data Source
  KAKENHI-PROJECT-23300017
[Journal Article] Fault Recovery Technique for TMRSoftcore Processor System using PartialReconfiguration2012
- Author(s)
  M.Fujino, H.Tanaka, Y.Ichinomiya,M.Kuga, M.Iida, M.Amagasaki andT.Sueyoshi
- Journal Title
  
  Proc. of 12th International Conference onAlgorithms and Architectures for ParallelProcessing (ICA3PP-12), Lecture Notes in ComputerScience(LNCS)7439,Springer-VerlagBerlinHeidelberg
  
  Pages: 392-404
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22300018
[Journal Article] Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration2012
- Author(s)
  Y.Ichinomiya, T.Kimura, M.Amagasaki, M.Kuga, M.Iida and T.Sueyoshi
- Journal Title
  
  IEICE Transactions on Fundamentals of Electronics
  
  Volume: Vol.E95-A, No.12 Pages: 2347-2356
- NAID
  10031161369
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23300017
[Journal Article] Accelerated evaluation of SEUfailure-in-time using frame-based partialreconfiguration ,''Proc2012
- Author(s)
  Y.Ichinomiya, K.Takano, M.Amagasaki,M.Kuga, M.Iida and T.Sueyosh
- Journal Title
  
  Proc. InternationalConference on Field ProgrammableTechnology(ICFPT2012)
  
  Pages: 220-223
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22300018
[Journal Article] A bitstream relocation technique toimprove flexibility of partialreconfiguration2012
- Author(s)
  Y.Ichinomiya, M.Amagasaki, M.Iida,M.Kuga and T.Sueyoshi
- Journal Title
  
  Proc. of 12th International Conference onAlgorithms and Architectures for ParallelProcessing (ICA3PP-12), Lecture Notes inComputer Science (LNCS) 7439,Springer-Verlag Berlin Heidelber
  
  Pages: 139-152
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22300018
[Journal Article] Fault-Injection Analysis to Estimate SEUFailure in Time by Using Frame-BasedPartial Reconfiguration2012
- Author(s)
  Y.Ichinomiya, T.Kimura, M.Amagasaki,M.Kuga, M.Iida and T.Sueyoshi
- Journal Title
  
  IEICETransactions on Fundamentals ofElectronics, , Communications andComputer Sciences
  
  Volume: Vol.E95-A,No.12 Pages: 2347-2356
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22300018
[Journal Article] Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration2012
- Author(s)
  Y.Ichinomiya, T.Kimura, M.Amagasaki, M.Kuga, M.Iida and T.Sueyoshi
- Journal Title
  
  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
  
  Volume: Vol.E95-A, No.12 Pages: 2347-2356
- NAID
  10031161369
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22300018
[Journal Article] COGRE : A Novel Compact Logic Cell Architecture for Area Minimization2012
- Author(s)
  M.Iida, M.Amagasaki, Y.Okamoto, Q.Zhao and T.Sueyoshi
- Journal Title
  
  IEICE Transactions on Information and Systems
  
  Volume: Vol.E95-D, No.2 Pages: 294-302
- NAID
  10030610468
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23300017
[Journal Article] Fault Recovery Technique for TMR Softcore Processor System using Partial Reconfiguration2012
- Author(s)
  M.Fujino, H.Tanaka, Y.Ichinomiya, M.Kuga, M.Iida, M.Amagasaki and T.Sueyoshi
- Journal Title
  
  Lecture Notes in Computer Science, Springer-Verlag Berlin Heidelberg
  
  Volume: 7439 Pages: 392-404
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23300017
[Journal Article] A Self-Organization Maps Approach to FPGA Placement2012
- Author(s)
  M.Amagasaki, Y.Tomonari, M.Iida, M.Kuga, T.Sueyosh
- Journal Title
  
  Proc.The 17th Workshop on Synthesis And System Integration of Mixed Information Technologies
  
  Pages: 468-469
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21700061
[Journal Article] COGRE: A Novel Compact Logic Cell Architecture for Area Minimization2012
- Author(s)
  M.Iida, M.Amagasaki, Y.Okamoto, Q.Zhao, T.Sueyoshi
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: E95-D Issue: 2 Pages: 294-302
- DOI
  10.1587/transinf.E95.D.294
- NAID
  10030610468
- ISSN
  0916-8532, 1745-1361
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23300017
[Journal Article] An Easily Testable Routing Architecture and Prototype Chip2012
- Author(s)
  K.Inoue, M.Amagasaki, M.Iida, T.Sueyoshi
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: E95-D Issue: 2 Pages: 303-313
- DOI
  10.1587/transinf.E95.D.303
- NAID
  10030610493
- ISSN
  0916-8532, 1745-1361
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23300017
[Journal Article] A bitstream relocation technique to improve flexibility of partial reconfiguration2012
- Author(s)
  Y.Ichinomiya, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi
- Journal Title
  
  Lecture Notes in Computer Science, Springer-Verlag Berlin Heidelberg
  
  Volume: 7439 Pages: 139-152
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23300017
[Journal Article] Designing flexible reconfigurableregions to relocate partial bitstreams2012
- Author(s)
  Y.Ichinomiya, S.Usagawa, M.Amagasaki,M.Iida, M.Kuga and T.Sueyoshi
- Journal Title
  
  Proc. the 20th Annual International IEEESymposium on Field-Programmable CustomComputing Machines (FCCM2012)
  
  Pages: 241-241
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22300018
[Journal Article] An Easily Testable Routing Architecture and Prototype Chip2012
- Author(s)
  K.Inoue, M.Koga, M.Amagasaki, M.Iida, Y.Ichida, M.Saji, J.Iida and T.Sueyoshi
- Journal Title
  
  IEICE Transactions on Information and Systems
  
  Volume: Vol.E95-D, No.2 Pages: 303-313
- NAID
  10030610493
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23300017
[Journal Article] Improving the Soft-error Tolerability of a Soft-core Processor on an FPGA using Triple Modular Redundancy and Partial Reconfiguration2011
- Author(s)
  Y.Ichinomiya, M.Amagasaki, M.Iida, M.Kuga, T.Sueyoshi
- Journal Title
  
  Journal of Next Generation Information Technology
  
  Volume: 2 Pages: 35-48
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22300018
[Journal Article] Reliable Softcore Processor System using TMR and Dynamic Reconguration2011
- Author(s)
  M.Fujino, Y.Ichinomiya, M.Amagasaki, M.Kuga, M.Iida, T.Sueyoshi
- Journal Title
  
  Proc.2011 Joint Conference of Electrical and Electronics Engineers in Kyushu
- Data Source
  KAKENHI-PROJECT-22300018
[Journal Article] A Case Study of Dependability Estimation for SRAM-based FPGA Circuits2011
- Author(s)
  T.Kimura, Y.Ichinomiya, M.Koga, M.Amagasaki, M.Kuga, T.Sueyoshi
- Journal Title
  
  Proc.the 6th International Student Conference on Advanced Science and Technology
  
  Pages: 107-108
- Data Source
  KAKENHI-PROJECT-22300018
[Journal Article] Improving the Soft-error Tolerability ofa Soft-core Processor on an FPGA usingTriple Modular Redundancy and PartialReconfiguration2011
- Author(s)
  Y.Ichinomiya, M.Amagasaki, M.Iida,M.Kuga and T.Sueyoshi
- Journal Title
  
  Journal of Next Generation InformationTechnology
  
  Volume: Vol.2, No.3 Pages: 35-48
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22300018
[Journal Article] A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems2011
- Author(s)
  Q.Zhao, Y.Ichinomiya, M.Amagasaki, M.Iida and T.Sueyoshi
- Journal Title
  
  IEEE Embedded Systems Letters
  
  Volume: Vol.3, Issue3 Pages: 89-92
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23300017
[Journal Article] A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems2011
- Author(s)
  Qian Zhao, Yoahihiro Ichinomiya, et al
- Journal Title
  
  IEEE Embedded Systems Letters
  
  Volume: 3 Issue: 3 Pages: 89-92
- DOI
  10.1109/les.2011.2167213
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-11J07446, KAKENHI-PROJECT-22300018, KAKENHI-PROJECT-23300017
[Journal Article] A Case Study of Evaluation Technique for soft error Tolerance on SRAM-based FPGAs2010
- Author(s)
  T.Kimura, N.Kai, M.Amagasaki, M.Iida, M.Kuga, T.Sueyoshi
- Journal Title
  
  Proc.2010 Joint Conference of Electrical and Electronics Engineers in Kyushu
- NAID
  110007999814
- Data Source
  KAKENHI-PROJECT-22300018
[Journal Article] Improving the Robustness of a Softcore Processor against SEUs by using TMR and Partial Reconfiguration2010
- Author(s)
  Y.Ichinomiya, S.Tanoue, M.Amagasaki, M.Iida, M.Kuga, T.Sueyoshi
- Journal Title
  
  Proc.the 18th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines
  
  Pages: 47-54
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22300018
[Journal Article] A Case Study of Evaluation Technique forSoft error Tolerance on SRAM-based FPGAs2010
- Author(s)
  T.Kimura, N.Kai, M.Amagasaki, M.Kugaand T.Sueyoshi
- Journal Title
  
  Proc. of IEEE Region 10 InternationalTechnical Conference (TENCON2010)
  
  Volume: T6-2.5
- NAID
  110007999814
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22300018
[Journal Article] A Less Configuration Memory Reconfigurable Logic Device with Error Detect and Correct Circuit2010
- Author(s)
  Q.Zhao, Y.Ichinomiya, Y.Okamoto, M.Amagasaki, M.Iida, T.Sueyoshi
- Journal Title
  
  Proc.of IEEE Region 10 International Technical Conference
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22300018
[Journal Article] Improving the Reliability of FPGA system by using TMR and Partial Rconfiguration2010
- Author(s)
  Y.Ichinomiya, M.Amagasaki, M.Iida, M.Kuga, T.Sueyoshi
- Journal Title
  
  Proc.International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies
  
  Pages: 107-112
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22300018
[Journal Article] An Error Detect and Correct Circuit Based Fault-tolerant Reconfigurable Logic Device2010
- Author(s)
  Q.Zhao, Y.Ichinomiya, Y.Okamoto, M.Amagasaki, M.Iida, T.Sueyoshi
- Journal Title
  
  Proc.of International Conference on Field-Programmable Technology
  
  Pages: 85-90
- NAID
  110008106758
- Data Source
  KAKENHI-PROJECT-22300018
[Journal Article] Soft-error Tolerability Analysis for Triplicated Circuit on an FPGA2010
- Author(s)
  Y.Ichinomiya, Motoki Amagasaki, M.Kuga, Toshinori Sueyoshi
- Journal Title
  
  Proc.16th Workshop on Synthesis And System Integration of Mixed Information Technologies
  
  Pages: 448-453
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22300018
[Journal Article] Improving the Robustness ofs a SoftcoreProcessor against SEUs by using TMR andPartial Reconfiguration2010
- Author(s)
  Y.Ichinomiya, S.Tanoue, M.Amagasaki,M.Iida, M.Kuga and T.Sueyoshi
- Journal Title
  
  Proc. the 18th Annual International IEEESymposium on Field-Programmable CustomComputing Machines (FCCM2010)
  
  Pages: 47-54
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22300018
[Journal Article] SRAM型FPGA上の実装回路におけるソフトエラー耐性評価手法の一検討2010
- Author(s)
  木村剛士, 甲斐統貴, 堤喜章, 尼崎太樹, 久我守弘, 末吉敏則
- Journal Title
  
  電子情報通信学会技術研究報告書RECONF20-10-7
  
  Pages: 37-42
- NAID
  110007999814
- Data Source
  KAKENHI-PROJECT-22300018
[Journal Article] Soft-error Tolerability Analysis forTriplicated Circuit on an FPGA2010
- Author(s)
  Y.Ichinomiya, M.Amagasaki, M.Kuga andT.Sueyoshi
- Journal Title
  
  Proc. the 16th Workshop on Synthesis AndSystem Integration of Mixed InformationTechnologies (SASIMI2010)
  
  Pages: 448-453
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22300018
[Journal Article] A Case Study of Soft Error Emulation for SRAM-based FPGA Circuits2010
- Author(s)
  T.Kimura, N.Kai, M.Amagasaki, M.Iida, M.Kuga, T.Sueyoshi
- Journal Title
  
  Proc.2010 Joint Conference of Electrical and Electronics Engineers in Kyushu
- NAID
  130005033448
- Data Source
  KAKENHI-PROJECT-22300018
[Journal Article] A Robust Reconfigurable Logic Device Based on Less Configuration Memory Logic Cell2010
- Author(s)
  Q.Zhao, Y.Ichinomiya, Y.Okamoto, M.Amagasaki, M.Iida, T.Sueyoshi
- Journal Title
  
  Proc.of International Conference on Field-Programmable Technology
  
  Pages: 162-169
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22300018
[Patent] ニューラルネットワークの回路及びニューラルネットワーク演算方法2019
- Inventor(s)
  尼崎太樹; 飯田全広; 中原康宏; 千竈純太郎
- Industrial Property Rights Holder
  尼崎太樹; 飯田全広; 中原康宏; 千竈純太郎
- Industrial Property Rights Type
  特許
- Industrial Property Number
  2019-196326
- Filing Date
  2019
- Data Source
  KAKENHI-PROJECT-17K00083
[Presentation] 高速シリアル光通信を用いたCNN分割実装の検討2018
- Author(s)
  千竈純太郎・中原康宏・尼崎太樹・久我守弘・飯田全広・末吉敏則
- Organizer
  電子情報通信学会
- Data Source
  KAKENHI-PROJECT-17K00083
[Presentation] 2のべき乗近似とプルーニングを用いたCNN向けFPGAアクセラレータ2018
- Author(s)
  宇都宮誉博，尼崎太樹，飯田全広，久我守弘，末吉敏則
- Organizer
  電子情報通信学会
- Data Source
  KAKENHI-PROJECT-17K00083
[Presentation] CNN implementation using High Speed Optical Serial Links2018
- Author(s)
  千竈純太郎・中原康宏・尼崎太樹・飯田全広・久我守弘・末吉敏則
- Organizer
  電気・情報関係学会九州支部連合大会
- Data Source
  KAKENHI-PROJECT-17K00083
[Presentation] CNN accerarator using power-of-two weight and pruning2018
- Author(s)
  中原康宏・千竈純太郎・尼崎太樹・飯田全広・久我守弘・末吉敏則
- Organizer
  電気・情報関係学会九州支部連合大会
- Data Source
  KAKENHI-PROJECT-17K00083
[Presentation] Resources Utilization of Fine-grained Overlay Architecture2018
- Author(s)
  Theingi Myint（Kumamoto）・Qian Zhao（Kyutech）・Motoki Amagasaki・Masahiro Iida・Toshinori Sueyoshi
- Organizer
  電子情報通信学会
- Data Source
  KAKENHI-PROJECT-17K00083
[Presentation] 重みの2のべき乗近似を用いたCNNのFPGA実装に関する一検討2017
- Author(s)
  宇都宮誉博，尼崎太樹，飯田全広，久我守弘，末吉敏則
- Organizer
  電子情報通信学会
- Data Source
  KAKENHI-PROJECT-17K00083
[Presentation] Simple Wafer Stacking 3D-FPGA Architecture2015
- Author(s)
  M.Amagasaki
- Organizer
  IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)
- Place of Presentation
  ブリュッセル（ベルギー）
- Year and Date
  2015-06-03
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26730028
[Presentation] A CONFIGURATION MEMORY REDUCED PROGRAMMABLE LOGIC CELL2015
- Author(s)
  M.Amagasaki
- Organizer
  IEEE Symposium on COOL Chips XVIII
- Place of Presentation
  横浜
- Year and Date
  2015-04-14
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26730028
[Presentation] Architecture Exploration of 3D FPGA to minimize internal layer connection2015
- Author(s)
  M.Amagasaki
- Organizer
  IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
- Place of Presentation
  テジョン（韓国）
- Year and Date
  2015-10-06
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26730028
[Presentation] レイヤ間接続を削減した3次元FPGAアーキテクチャの検討2015
- Author(s)
  趙　謙，尼崎太樹，飯田全広，久我守弘，末吉敏則
- Organizer
  電子情報通信学会RECONF研究会
- Place of Presentation
  慶応大学
- Year and Date
  2015-01-29
- Data Source
  KAKENHI-PROJECT-26730028
[Presentation] 高速シリアル通信を用いた3次元FPGAの検討2014
- Author(s)
  梶原拓也，尼崎太樹，飯田全広，久我守弘，末吉敏則
- Organizer
  電子情報通信学会RECONF研究会
- Place of Presentation
  東北大学
- Year and Date
  2014-06-12
- Data Source
  KAKENHI-PROJECT-26730028
[Presentation] A Novel FPGA Design Framework with VLSI Post-routing erformance Analysis2013
- Author(s)
  Q.Zhao, K.Inoue, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi
- Organizer
  Proc. 21st ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA2013)
- Place of Presentation
  Monterey, California
- Year and Date
  2013-02-12
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] An FPGA design and implementation framework combined with commercial VLSI CADs2013
- Author(s)
  Qian Zhao, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi
- Organizer
  International Workshop on Reconfigurable Communication-centric Systems-on-Chip(ReCoSoC2013)
- Place of Presentation
  Darmstadt, Germany
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] DEFECT-ROBUST FPGA ARCHITECTURES FOR INTELLECTUAL PROPERTY CORES IN SYSTEM LSI2013
- Author(s)
  M.Amagasaki, Kazuki Inoue, Qian Zhao, M.Iida, M.Kuga and T.Sueyoshi
- Organizer
  23th International Conference on Field Programmable Logic and Applications (FPL2013)
- Place of Presentation
  Porto, Porutugal
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] An Automatic Design and Implementation Framework for Reconfigurable Logic IP Core2013
- Author(s)
  Qian Zhao, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi
- Organizer
  Proc. International Conference on ENGINEERING OF RECONFIGURABLE SYSTEMS AND ALGORITHMS (ERSA2013)
- Place of Presentation
  Las Vegas, Nevada, USA
- Year and Date
  2013-07-22
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] AN FPGA DESIGN AND IMPLEMENTATION FRAMEWORK COMBINED WITH COMMERCIAL VLSI CADS2013
- Author(s)
  Qian Zhao, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi
- Organizer
  Proc. 8th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC2013)
- Place of Presentation
  Darmstadt, Germany
- Year and Date
  2013-07-11
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] DEFECT-ROBUST FPGA ARCHITECTURES FOR INTELLECTUAL PROPERTY CORES IN SYSTEM LSI2013
- Author(s)
  M.Amagasaki, Kazuki Inoue, Qian Zhao, M.Iida, M.Kuga and T.Sueyoshi
- Organizer
  Proc. of 23th International Conference on Field Programmable Logic and Applications (FPL2013)
- Place of Presentation
  Porto, Portugal
- Year and Date
  2013-09-02
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] An Automatic Design and Implementation Framework for Reconfigurable Logic IP Core2013
- Author(s)
  Q.Zhao, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi
- Organizer
  Proc. of 23th International Conference on Field Programmable Logic and Applications (FPL2013)
- Place of Presentation
  Porto, Portugal
- Year and Date
  2013-09-04
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] An Automatic Design and Implementation Framework for Reconfigurable Logic IP Core2013
- Author(s)
  Q.Zhao, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi
- Organizer
  23th International Conference on Field Programmable Logic and Applications (FPL2013)
- Place of Presentation
  Porto, Porutugal
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] An Automatic Design and Implementation Framework for Reconfigurable Logic IP Core2013
- Author(s)
  Qian Zhao, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi
- Organizer
  International Conference on ENGINEERING OF RECONFIGURABLE SYSTEMS AND ALGORITHMS(ERSA2013)
- Place of Presentation
  Las Vegas, Nevada, USA
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] Evaluation of fault tolerant technique based on homogeneous FPGA architecture2012
- Author(s)
  Y.Nishitani, K.Inoue, Motoki Amagasaki, M.Iida, M.Kuga and T.Sueyoshi
- Organizer
  Proc. the 20th IFIP International Conference on Very Large Scale Integration (VLSI-SoC2012)
- Place of Presentation
  Santa Cruz, USA
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] Accelerated evaluation of SEU failure-in-time using frame-based partial reconfiguration2012
- Author(s)
  Y.Ichinomiya, K.Takano, M.Amagasaki, M.Kuga, M.Iida and T.Sueyoshi
- Organizer
  Proc. International Conference on Field Programmable Technology(ICFPT2012)
- Place of Presentation
  Seoul, Korea
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] Designing flexible reconfigurable regions to relocate partial bitstreams2012
- Author(s)
  Y.Ichinomiya, S.Usagawa, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi,
- Organizer
  Proc. the 20th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM2012)
- Place of Presentation
  Toronto, Canada
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] Accelerated evaluation of SEUfailure-in-time using frame-based partialreconfiguration2012
- Author(s)
  Y.Ichinomiya, K.Takano, M.Amagasaki,M.Kuga, M.Iida and T.Sueyoshi
- Organizer
  Proc. InternationalConference on Field ProgrammableTechnology(ICFPT2012)
- Place of Presentation
  Seoul(Korea)
- Year and Date
  2012-12-11
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] A Novel Physical Defects Recovery Technique for FPGA-IP cores2012
- Author(s)
  Y.Nishitani, K.Inoue, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi
- Organizer
  Proc. International Conference on Reconfigurable Computing and FPGAs (ReConFig2012)
- Place of Presentation
  Cancun, Mexico
- Year and Date
  2012-12-06
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] A Self-Organization Maps Approach to FPGA Placement2012
- Author(s)
  Motoki Amagasaki, Yasuaki Tomonari, Masahiro Iida, Morihiro Kuga and Toshinori Sueyoshi
- Organizer
  The 17th Workshop on Synthesis And System Integration of Mixed Information Technologies(SASIMI2012)
- Place of Presentation
  Beppu, Japan, B-CONPLAZA(別府市)
- Year and Date
  2012-03-09
- Data Source
  KAKENHI-PROJECT-21700061
[Presentation] 単一 FPGA 内における三重冗長モジュールの動的再配置によるハードエラー回避手法2012
- Author(s)
  田中宏樹,一ノ宮佳裕,宇佐川貞幹,尼崎太樹,飯田全広,久我守弘,末吉敏則
- Organizer
  信学技報 RECONF2012-11
- Place of Presentation
  沖縄県男女共同参画センター(那覇)
- Year and Date
  2012-05-29
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] Fault Detection and Avoidance of FPGA in Various Granularities2012
- Author(s)
  K.Inoue, Y.Nishitani, M.Amagasaki, M.Iida and T.Sueyoshi
- Organizer
  Proc. 22th International Conference on Field Programmable Logic and Applications (FPL2012)
- Place of Presentation
  Oslo, Norway
- Year and Date
  2012-08-29
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] A bitstream relocation technique toimprove flexibility of partialreconfiguration2012
- Author(s)
  Y.Ichinomiya, M.Amagasaki, M.Iida,M.Kuga and T.Sueyoshi
- Organizer
  Proc. of 12th International Conference onAlgorithms and Architectures for ParallelProcessing(ICA3PP-12)
- Place of Presentation
  九州産業大学(福岡)
- Year and Date
  2012-09-07
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] FPGA システムのソフトエラー耐性評価におけるブートストラップ法による高速化2012
- Author(s)
  高野光平,一ノ宮佳裕,尼崎太樹,久我守弘,飯田全広,末吉敏則
- Organizer
  信学技報 RECONF2012-45
- Place of Presentation
  立命館大学(草津)
- Year and Date
  2012-09-19
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] システムの高信頼化に向けた SupervisorProcessor の一検討2012
- Author(s)
  藤野誠,一ノ宮佳裕,久我守弘,尼崎太樹,飯田全広,末吉敏則
- Organizer
  学技報 CPSY2011-92
- Place of Presentation
  ホテル松島大観荘(仙台)
- Year and Date
  2012-03-03
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] A Self-Organization Maps Approach to FPGA Placement2012
- Author(s)
  M.Amagasaki, Y.Tomonari, M.Iida, M.Kuga, T.Sueyoshi
- Organizer
  Workshop on Synthesis And System Integration of Mixed Information Technologies
- Place of Presentation
  別府国際コンベンションセンター(大分県)
- Year and Date
  2012-03-09
- Data Source
  KAKENHI-PROJECT-21700061
[Presentation] Designing flexible reconfigurableregions to relocate partial bitstreams2012
- Author(s)
  Y.Ichinomiya, S.Usagawa, M.Amagasaki,M.Iida, M.Kuga and T.Sueyoshi
- Organizer
  Proc. the 20th Annual International IEEESymposium on Field-Programmable Custom Computing Machines (FCCM2012)
- Place of Presentation
  Toronto, Canada(USA)
- Year and Date
  2012-05-01
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] 動的部分再構成を用いたソフトエラー耐性評価手法2012
- Author(s)
  高野光平,木村剛士,一ノ宮佳裕,尼崎太樹,久我守弘,飯田全広,末吉敏則
- Organizer
  LSI とシステムのワークショップ 2012 予稿集
- Place of Presentation
  北九州国際会議場(北九州)
- Year and Date
  2012-05-29
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] システムの高信頼化に向けたSupervisor Processorの一検討2012
- Author(s)
  藤野誠, 一ノ宮佳裕, 久我守弘, 尼崎太樹, 飯田全広, 末吉敏則
- Organizer
  電子情報通信学会CPSY研究会
- Place of Presentation
  ホテル松島大観荘(宮城県)
- Year and Date
  2012-03-03
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] Fault Detection and Avoidance of FPGA inVarious Granularities2012
- Author(s)
  M.Fujino, H.Tanaka, Y.Ichinomiya,M.Kuga, M.Iida, M.Amagasaki andT.Sueyoshi
- Organizer
  Proc. of 12th International Conference onAlgorithms and Architectures for ParallelProcessing(ICA3PP-12)
- Place of Presentation
  九州産業大学(福岡)
- Year and Date
  2012-09-07
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] Evaluation of fault tolerant technique based on homogeneous FPGA architecture2012
- Author(s)
  Y.Nishitani, K.Inoue, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi
- Organizer
  Proc. the 20th IFIP International Conference on Very Large Scale Integration
- Place of Presentation
  Santa Cruz, CA, USA
- Year and Date
  2012-10-10
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] Self-repair Technique using SpareResource in TMR Softcore ProcessorSystem2012
- Author(s)
  H.Tanaka, Y.Ichinomiya, M.Amagasaki,M.Kuga, M.Iida and T.Sueyoshi
- Organizer
  Proc. 2012 Joint Conference ofElectrical and Electronics Engineers inKyusyu
- Place of Presentation
  長崎大学(長崎)
- Year and Date
  2012-09-24
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] コホーネンネットワークを用いたFPGA配置アルゴリズム2011
- Author(s)
  友成恭章, 尼崎太樹, 飯田全広, 久我守弘, 末吉敏則
- Organizer
  情報処理学会九州支部若手の会セミナー
- Place of Presentation
  パレスイン鹿児島(鹿児島県)
- Year and Date
  2011-09-16
- Data Source
  KAKENHI-PROJECT-21700061
[Presentation] ソフトコアプロセッサシステムの高信頼化に向けたコンテキスト同期手法2011
- Author(s)
  藤野誠,甲斐統貴,一ノ宮佳裕,尼崎太樹,久我守弘,末吉敏則
- Organizer
  信学技報 RECONF2011-5
- Place of Presentation
  北海道大学(札幌)
- Year and Date
  2011-05-12
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] Reliable Softcore Processor System using TMR and Dynamic Reconguration2011
- Author(s)
  M.Fujino, Y.Ichinomiya, M.Amagasaki, M.Kuga, M.Iida, T.Sueyoshi
- Organizer
  Joint Conference of Electrical and Electronics Engineers in Kyushu
- Place of Presentation
  佐賀大学(佐賀県)
- Year and Date
  2011-09-26
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] FPGA における二重冗長ソフトコアプロセッサの高信頼化手法2011
- Author(s)
  山本千重子,白石恭平,一ノ宮佳裕,尼崎太樹,久我守弘,末吉敏則
- Organizer
  若手の会セミナー2011 講演論文集, 情報処理学会九州支部
- Place of Presentation
  パレスインホテル鹿児島(鹿児島)
- Year and Date
  2011-09-17
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] 動的再構成システムに向けた部分再構成データの再配置に関する一検討2011
- Author(s)
  宇佐川貞幹, 一ノ宮佳裕, 尼崎太樹, 飯田全広, 久我守弘, 末吉敏則
- Organizer
  電子情報通信学会RECONF研究会
- Place of Presentation
  名古屋大学(愛知県)
- Year and Date
  2011-09-26
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] コホーネンネットワークを用いたFPGA配置アルゴリズム2011
- Author(s)
  友成恭章, 尼崎太樹, 飯田全広, 久我守弘, 末吉敏則
- Organizer
  情報処理学会九州支部
- Place of Presentation
  パレスイン鹿児島(鹿児島市)
- Year and Date
  2011-09-16
- Data Source
  KAKENHI-PROJECT-21700061
[Presentation] ソフトコアプロセッサシステムの高信頼化に向けたコンテキスト同期手法2011
- Author(s)
  藤野誠, 甲斐統貴, 一ノ宮佳裕, 尼崎太樹, 久我守弘, 末吉敏則
- Organizer
  電子情報通信学会RECONF研究会
- Place of Presentation
  北海道大学(北海道)
- Year and Date
  2011-05-12
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] Reliable Softcore Procesor System usingTMR and Dynamic Reconguration2011
- Author(s)
  M.Fujino, Y.Ichinomiya, M.Amagasaki,M.Kuga, M.Iida and T.Sueyoshi
- Organizer
  Proc. 2011 Joint Conference of Electricaland Electronics Engineers in Kyusyu
- Place of Presentation
  佐賀大学(佐賀)
- Year and Date
  2011-09-26
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] LUT間の入力共有に基づく小面積論理クラスク構造の一提案2011
- Author(s)
  高橋知也, 井上万輝, 尼崎太樹, 飯田全広, 久我守弘, 末吉敏則
- Organizer
  IEICEリコンフィギャラブルシステム研究会
- Place of Presentation
  名古屋大学
- Year and Date
  2011-09-26
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] AN EASILY TESTABLE ROUTING ARCHITECTURE AND EFFICIENT TEST TECHNIQUE2011
- Author(s)
  K.Inoue, H.Yosho, M.Amagasaki, M.Iida and T.Sueyoshi
- Organizer
  Proc. 21th International Conference on Field Programmable Logic and Applications (FPL2011)
- Place of Presentation
  Chania, Greece
- Year and Date
  2011-09-06
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] 自己組織化マップを用いたFPGA配置手法の提案2011
- Author(s)
  友成恭章, 尼崎太樹, 飯田全広, 久我守弘, 末吉敏則
- Organizer
  電子情報通信学会RECONF研究会
- Place of Presentation
  名古屋大学(愛知県)
- Year and Date
  2011-09-26
- Data Source
  KAKENHI-PROJECT-21700061
[Presentation] A Case Study of Dependability Estimation for SRAM-based FPGA Circuits2011
- Author(s)
  T.Kimura, Y.Ichinomiya, M.Koga, M.Amagasaki, M.Kuga, T.Sueyoshi
- Organizer
  International Student Conference on Advanced Science and Technology
- Place of Presentation
  山東大学(中国)
- Year and Date
  2011-09-23
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] \AN EASILY TESTABLE ROUTING ARCHITECTURE AND EFFICIENT TEST TECHNIQUE2011
- Author(s)
  K.Inoue, H.Yosho, M.Amagasaki, M.Iida, T.Sueyoshi
- Organizer
  21th International Conference on Field Programmable Logic and Applications (FPL2011)
- Place of Presentation
  Chania, Greece
- Year and Date
  2011-09-06
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] 自己組織化マップを用いたFPGA配置手法の提案2011
- Author(s)
  友成恭章, 尼崎太樹, 飯田全広, 久我守弘, 末吉敏則
- Organizer
  信学技報RECONF2011-26
- Place of Presentation
  名古屋大学(名古屋市)
- Year and Date
  2011-09-26
- Data Source
  KAKENHI-PROJECT-21700061
[Presentation] ホモジニアスな配線構造によるFPGA設計の容易化2011
- Author(s)
  井上万輝, 尼崎太樹, 飯田全広
- Organizer
  IEICEリコンフィギャラブルシステム研究会
- Place of Presentation
  北海道大学
- Year and Date
  2011-05-13
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] 二重冗長ソフトコアプロセッサにおけるソフトエラーの高速復旧技術2011
- Author(s)
  一ノ宮佳裕,藤野誠,尼崎太樹,久我守弘,飯田全広,末吉敏則
- Organizer
  信学技報 RECONF2011-42
- Place of Presentation
  ニューウェルシティ宮崎(宮崎)
- Year and Date
  2011-11-28
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] A Case Study of Dependability Estimationfor SRAM-based FPGA Circuits2011
- Author(s)
  T.Kimura, Y.Ichinomiya, M.Koga,M.Amagasaki, M.Kuga and T.Sueyoshi
- Organizer
  Proc. the6th International Student Conference onAdvanced Science and Technology(ICAST)
- Place of Presentation
  Jinan(China)
- Year and Date
  2011-09-23
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] An Easily Testable Routing Architecture of FPGA2011
- Author(s)
  M.Iida, K.Inoue, M.Amagasaki and T.Sueyoshi
- Organizer
  Proc. the 19th IFIP International Conference on Very Large Scale Integration (VLSI-SoC2011)
- Place of Presentation
  Hong Cong, China
- Year and Date
  2011-10-03
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] 動的再構成システムに向けた部分再構成データの再配置に関する一検討2011
- Author(s)
  宇佐川貞幹,一ノ宮佳裕,尼崎太樹,飯田全広,久我守弘,末吉敏則
- Organizer
  信学技報 RECONF2011-30
- Place of Presentation
  名古屋大学(名古屋)
- Year and Date
  2011-09-26
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] FPGAにおける二重冗長ソフトコアプロセッサの高信頼化手法2011
- Author(s)
  山本千重子, 白石恭平, 一ノ宮佳裕, 尼崎太樹, 久我守弘, 末吉敏則
- Organizer
  情報処理学会九州支部若手の会セミナー
- Place of Presentation
  パレスイン鹿児島(鹿児島県)
- Year and Date
  2011-09-17
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] 二重冗長ソフトコアプロセッサにおけるソフトエラーの高速復旧技術2011
- Author(s)
  一ノ宮佳裕, 藤野誠, 尼崎太樹, 久我守弘, 飯田全広, 末吉敏則
- Organizer
  電子情報通信学会RECONF研究会
- Place of Presentation
  ニューウェルシティ宮崎(宮崎県)
- Year and Date
  2011-11-28
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] An Easily Testable Routing Architecture of FPGA2011
- Author(s)
  M.Iida, K.Inoue, M.Amagasaki, T.Sueyoshi
- Organizer
  19th IFIP International Conference on Very Large Scale Integration (VLSI-SoC2011)
- Place of Presentation
  Hong Cong, Chaina
- Year and Date
  2011-10-03
- Data Source
  KAKENHI-PROJECT-23300017
[Presentation] Improving the Robustness of a Softcore Processor against SEUs by using TMR and Partial Reconfiguration2010
- Author(s)
  Y.Ichinomiya, S.Tanoue, M.Amagasaki, M.Iida, M.Kuga, T.Sueyoshi
- Organizer
  Proc.the 18th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines
- Place of Presentation
  Hilton Charlotte University Place(USA)
- Year and Date
  2010-05-03
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] SRAM型FPGA上の実装回路におけるソフトエラー耐性評価手法の一検討2010
- Author(s)
  木村剛士, 甲斐統貴, 堤喜章, 尼崎太樹, 久我守弘, 末吉敏則
- Organizer
  電子情報通信学会技術研究報告書RECONF2010-7
- Place of Presentation
  やすらぎ伊王島(長崎市)
- Year and Date
  2010-05-13
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] A Robust Reconfigurable Logic Device Based on Less Configuration Memory Logic Cell2010
- Author(s)
  Q.Zhao, Y.Ichinomiya, Y.Okamoto, M.Amagasaki, M.Iida, T.Sueyoshi
- Organizer
  Proc.of International Conference on Field-Programmable Technology
- Place of Presentation
  清華大学(中国)
- Year and Date
  2010-12-09
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] A Case Study of Soft Error Emulation for SRAM-based FPGA Circuits2010
- Author(s)
  T.Kimura, N.Kai, M.Amagasaki, M.Iida, M.Kuga, T.Sueyoshi
- Organizer
  Proc.2010 Joint Conference of Electrical and Electronics Engineers in Kyushu
- Place of Presentation
  九州産業大学
- Year and Date
  2010-09-25
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] Improving the Reliability of FPGA system by using TMR and Partial Rconfiguration2010
- Author(s)
  Y.Ichinomiya, M.Amagasaki, M.Iida, M.Kuga, T.Sueyoshi
- Organizer
  Proc.International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies
- Place of Presentation
  つくば国際会議場(つくば市)
- Year and Date
  2010-06-01
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] Soft-error Tolerability Analysis forTriplicated Circuit on an FPGA2010
- Author(s)
  Y.Ichinomiya, M.Amagasaki, M.Kuga andT.Sueyoshi
- Organizer
  Proc. the16th Workshop on Synthesis And SystemIntegration of Mixed InformationTechnologies (SASIMI2010)
- Place of Presentation
  Taipei(Taiwan)
- Year and Date
  2010-10-19
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] A Less Configuration Memory Reconfigurable Logic Device with Error Detect and Correct Circuit2010
- Author(s)
  Q.Zhao, Y.Ichinomiya, Y.Okamoto, M.Amagasaki, M.Iida, T.Sueyoshi
- Organizer
  Proc.of IEEE Region 10 International Technical Conference
- Place of Presentation
  福岡国際会議場(福岡市)
- Year and Date
  2010-11-22
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] A Case Study of Evaluation Technique for soft error Tolerance on SRAM-based FPGAs2010
- Author(s)
  T.Kimura, N.Kai, M.Amagasaki, M.Iida, M.Kuga, T.Sueyoshi
- Organizer
  Proc.of IEEE Region 10 International Technical Conference
- Place of Presentation
  福岡国際会議場(福岡市)
- Year and Date
  2010-11-22
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] SRAM 型 FPGA 上の実装回路におけるソフトエラー耐性評価手法の一検討2010
- Author(s)
  木村剛士,甲斐統貴,堤喜章,尼崎太樹,久我守弘,末吉敏則
- Organizer
  信学技報 RECONF2010-7
- Place of Presentation
  やすらぎ伊王島(長崎)
- Year and Date
  2010-05-13
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] An Error Detect and Correct Circuit Based Fault-tolerant Reconfigurable Logic Device2010
- Author(s)
  Q.Zhao, Y.Ichinomiya, Y.Okamoto, M.Amagasaki, M.Iida, T.Sueyoshi
- Organizer
  電子情報通信学会技術研究報告書RECONF2010-32
- Place of Presentation
  静岡大学
- Year and Date
  2010-09-17
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] Improving the Robustness ofs a SoftcoreProcessor against SEUs by using TMR andPartial Reconfiguration2010
- Author(s)
  Y.Ichinomiya, S.Tanoue, M.Amagasaki,M.Iida, M.Kuga and T.Sueyoshi
- Organizer
  Proc. the 18thAnnual International IEEE Symposium onField-Programmable Custom ComputingMachines (FCCM2010)
- Place of Presentation
  Charlotte, North Carolina(USA)
- Year and Date
  2010-05-03
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] A Case Study of Evaluation Technique forSoft error Tolerance on SRAM-based FPGAs2010
- Author(s)
  T.Kimura, N.Kai, M.Amagasaki, M.Kugaand T.Sueyoshi
- Organizer
  Proc. of IEEE Region 10 InternationalTechnical Conference (TENCON2010)
- Place of Presentation
  福岡国際会議場(福岡)
- Year and Date
  2010-11-22
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] Soft-error Tolerability Analysis for Triplicated Circuit on an FPGA2010
- Author(s)
  Y.Ichinomiya, Motoki Amagasaki, M.Kuga, Toshinori Sueyoshi
- Organizer
  Proc.16th Workshop on Synthesis And System Integration of Mixed Information Technologies
- Place of Presentation
  Grand Formosa Regent Taipei(台湾)
- Year and Date
  2010-10-19
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] A Logic Cell Architecture Exploiting the Shannon Expansion for the Reduction of Configuration Memory
- Author(s)
  Q.Zhao, K.Yanagida, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi
- Organizer
  24th International Conference on Field Programmable Logic and Applications (FPL2014)
- Place of Presentation
  Munich, Germany
- Year and Date
  2014-09-01 – 2014-09-03
- Data Source
  KAKENHI-PROJECT-26730028
[Presentation] Fault Detection and Avoidance of FPGA in Various Granularities
- Author(s)
  M.Fujino, H.Tanaka, Y.Ichinomiya, M.Kuga, M.Iida, M.Amagasaki and T.Sueyoshi
- Organizer
  Proc. of 12th International Conference on Algorithms and Architectures for Parallel Processing(ICA3PP-12)
- Place of Presentation
  Kyushu Sangyo University, Fukuoka, Japan
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] Self-repair Technique using Spare Resource in TMR Softcore Processor System
- Author(s)
  H.Tanaka, Y.Ichinomiya, M.Amagasaki, M.Kuga, M.Iida and T.Sueyoshi
- Organizer
  Proc. 2012 Joint Conference of Electrical and Electronics Engineers in Kyusyu
- Place of Presentation
  Nagasaki University, Nagasaki, Japan
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] Designing flexible reconfigurable regions to relocate partial bitstreams
- Author(s)
  Y.Ichinomiya, S.Usagawa, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi,
- Organizer
  Proc. the 20th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM2012)
- Place of Presentation
  Toronto, Canada
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] 単一FPGA内における三重冗長モジュールの動的再配置によるハードエラー回避手法
- Author(s)
  田中宏樹，一ノ宮佳裕，宇佐川貞幹，尼崎太樹，飯田全広，久我守弘，末吉敏則
- Organizer
  信学技報 RECONF2012-11
- Place of Presentation
  沖縄県男女共同参画センター，那覇，沖縄
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] A Novel Three-dimensional FPGA Architecture with High-speed Serial Communication Links
- Author(s)
  T.Kajiwara, Q.Zhao, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi
- Organizer
  International Conference on Field Programmable Technology(ICFPT2014)
- Place of Presentation
  shanghai, China
- Year and Date
  2014-12-10 – 2014-12-12
- Data Source
  KAKENHI-PROJECT-26730028
[Presentation] FPGAシステムのソフトエラー耐性評価におけるブートストラップ法による高速化
- Author(s)
  高野光平，一ノ宮佳裕，尼崎太樹，久我守弘，飯田全広，末吉敏則
- Organizer
  信学技報 RECONF2012-45
- Place of Presentation
  立命館大，草津市，滋賀
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] A bitstream relocation technique to improve flexibility of partial reconfiguration
- Author(s)
  Y.Ichinomiya, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi
- Organizer
  Proc. of 12th International Conference on Algorithms and Architectures for Parallel Processing(ICA3PP-12)
- Place of Presentation
  Kyushu Sangyo University, Fukuoka, Japan
- Data Source
  KAKENHI-PROJECT-22300018
[Presentation] Accelerated evaluation of SEU failure-in-time using frame-based partial reconfiguration
- Author(s)
  Y.Ichinomiya, K.Takano, M.Amagasaki, M.Kuga, M.Iida and T.Sueyoshi
- Organizer
  Proc. International Conference on Field Programmable Technology(ICFPT2012)
- Place of Presentation
  Seoul, Korea
- Data Source
  KAKENHI-PROJECT-22300018

1. SUEYOSHI Toshinori (00117136)

# of Collaborated Projects: 2 results

# of Collaborated Products: 92 results
2. 木山真人 (30363534)

# of Collaborated Projects: 2 results

# of Collaborated Products: 2 results
3. KUGA Morihiro (80243989)

# of Collaborated Projects: 1 results

# of Collaborated Products: 58 results
4. IIDA Masahiro (70363512)

# of Collaborated Projects: 1 results

# of Collaborated Products: 30 results
5. 瀬戸謙修 (10420241)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results

AMAGASAKI MOTOKI 尼崎 太樹

AMAGASAKI Motoki 尼崎 太樹

Research Projects

Research Products

Co-Researchers

高位合成を用いた融合型ニューラルネットワークアクセラレータの自動生成

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エッジAIシステム向け設計基盤技術に関する研究Principal Investigator

Principal Investigator

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Neural network LSI for deep learningPrincipal Investigator

Principal Investigator

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Three dimensional FPGA architecture and its design methodPrincipal Investigator

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A Study of High Dependability Reconfigurable Logic Architecture

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Development of Self-Repair Dependable system on FPGA

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FPGA design method based on self-organization maps.Principal Investigator

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[Journal Article] A Lightweight Deep Neural Network Using a Mixer-Type Nonlinear Vector Autoregression2023

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[Journal Article] `A Deep Neural Network Translator for Edge Site Implementation2023

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[Journal Article] A Posit Based Multiply-accumulate Unit with Small Quire Size for Deep Neural Networks2022

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[Journal Article] EVALUATION OF ROUTING AREA REDUCTION FOR FINE-GRAINED OVERLAY VIRTUAL FPGA2020

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[Journal Article] A SLM-based Overlay Architecture for Fine-grained Virtual FPGA2020

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NAID

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[Journal Article] SLM: A Scalable Logic Module Architecture with Less Configuration Memory2016

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NAID

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[Journal Article] A 3D FPGA Architecture to Realize Simple Die Stacking2015

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AMAGASAKI MOTOKI 尼崎太樹

AMAGASAKI Motoki 尼崎太樹