Xu Zule 徐祖楽

Researcher Number	50778925
Other IDs
Affiliation (based on the past Project Information) *help	2019 – 2021: 東京大学, 大学院工学系研究科(工学部), 特任講師 2018: 東京大学, 大規模集積システム設計教育研究センター, 特任講師 2017: 東京理科大学, 工学部電気工学科, 助教
Review Section/Research Field	Principal Investigator Basic Section 21060:Electron device and electronic equipment-related / Communication/Network engineering
Keywords	Principal Investigator アナログ集積回路設計自動化 / アナログ集積回路の設計自動化 / 自動配置配線可能なアナログ回路 / 電子デバイス・機器 / 位相同期回路 / 極低消費電力PLL / IoT / 無線機 / 周波数シンセサイザ

Research Projects
(2 results)
Research Products
(14 results)

Synthesizable Mixed-Signal Integrated Circuits for Agile Development of Analog AI Sensor NodesPrincipal Investigator
- Principal Investigator
  
  Xu Zule
- Project Period (FY)
  2020 – 2021
- Research Category
  
  Grant-in-Aid for Early-Career Scientists
- Review Section
  
  Basic Section 21060:Electron device and electronic equipment-related
- Research Institution
  The University of Tokyo
Research on Ultra-Low Power Ring-Oscillator Based Frequency Synthesizer for Wireless Sensor NodesPrincipal Investigator
- Principal Investigator
  
  Xu Zule
- Project Period (FY)
  2017 – 2019
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Communication/Network engineering
- Research Institution
  The University of Tokyo
  Tokyo University of Science

All 2022 2021 2019 2017

All Journal Article Presentation

[Journal Article] A fractional-N MASH2-k FDC phase-locked loop architecture enabling higher-order quantisation noise shaping2022
- Author(s)
  R. Iwashita, Z.Xu, M. Osada, and T. Iizuka
- Journal Title
  
  IET Electronics Letters
  
  Volume: 58 Issue: 7 Pages: 274-276
- DOI
  10.1049/ell2.12436
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-20K14786, KAKENHI-PROJECT-22KJ0659, KAKENHI-PROJECT-21H03406
[Journal Article] Analysis of strong-arm comparator with auxiliary pair for offset calibration2022
- Author(s)
  S. Li, Z. Xu, and T. Iizuka
- Journal Title
  
  Springer Journal of Analog Integrated Circuits and Signal Processing
  
  Volume: 110 Issue: 3 Pages: 535-546
- DOI
  10.1007/s10470-022-01992-6
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-20K14786, KAKENHI-PROJECT-21H03406
[Journal Article] Analysis and simulation of MOSFET-based gate-voltage-independent capacitor2022
- Author(s)
  S. Li, N. Ojima, Z. Xu, and T. Iizuka
- Journal Title
  
  Japanese Journal of Applied Physics (JJAP)
  
  Volume: 1 Issue: 6 Pages: 1-13
- DOI
  10.35848/1347-4065/ac6406
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-20K14786, KAKENHI-PROJECT-21H03406
[Journal Article] An All-Standard-Cell-Based Synthesizable SAR ADC with Nonlinearity-Compensated RDAC2021
- Author(s)
  Z. Xu, N. Ojima, S. Li, and T. Iizuka
- Journal Title
  
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  
  Volume: 29 Issue: 12 Pages: 2153-2162
- DOI
  10.1109/tvlsi.2021.3122027
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-20K14786, KAKENHI-PROJECT-21H03406
[Journal Article] Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector2019
- Author(s)
  Zule Xu, Anugerah Firdauzi, Masaya Miyahara, Kenichi Okada, and Akira Matsuzawa
- Journal Title
  
  IEICE Transactions on Electronics
  
  Volume: E102-C
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17K14684
[Journal Article] A Saturating-Integrator-Based Behavioral Model of Ring Oscillator Facilitating PLL Design2017
- Author(s)
  XU Zule、KAWAHARA Takayuki
- Journal Title
  
  IEICE Trans. Electron.
  
  Volume: E100.C Issue: 4 Pages: 370-372
- DOI
  10.1587/transele.E100.C.370
- NAID
  130005529923
- ISSN
  0916-8524, 1745-1353
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17K14684
[Presentation] An All-Standard-Cell-Based Synthesizable SAR ADC with Nonlinearity-Compensated RDAC2022
- Author(s)
  Z. Xu, N. Ojima, S. Li, and T. Iizuka
- Organizer
  IEEE International Symposium on Circuits and Systems
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-20K14786
[Presentation] A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter2022
- Author(s)
  Z. Yang, Z. Xu, M. Osada, and T. Iizuka
- Organizer
  IEEE VLSI Symposium on Technology and Circuits
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-20K14786
[Presentation] A Charge-Redistribution Multi-Bit Stochastic-Resonance ADC Enhancing SNDR for Weak Input Signal2022
- Author(s)
  R. Shibata, Z. Xu, Y. Hotta, H. Tabata, and T. Iizuka
- Organizer
  IEEE International Symposium on Circuits and Systems
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-20K14786
[Presentation] A 0.79-1.16-GHz Synthesizable Fractional-N PLL Using DTC-Based Multi-Stage Injection with Dithering-Assisted Local Skew Calibration Achieving －232.8-dB FoMref2021
- Author(s)
  Z. Xu
- Organizer
  IEEE Asian Conference on Solid-State Circuits
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-20K14786
[Presentation] Low-Power and Low-Noise Clock Generation: A Fractional-N Hybrid CDAC-Embedded Sampling PLL and a Class-C Complementary Colpitts Crystal Oscillator2021
- Author(s)
  Z. Xu
- Organizer
  IEEE International Workshop on Electromagnetics: Applications and Student Innovation Competition
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-20K14786
[Presentation] A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with －80-dBc Reference Spur2021
- Author(s)
  Zule Xu, Masaru Osada, and Tetsuya Iizuka
- Organizer
  IEEE Symposium on VLSI Circuits
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-20K14786
[Presentation] A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with －80-dBc Reference Spur2021
- Author(s)
  Z. Xu, M. Osada, T. Iizuka
- Organizer
  IEEE SSCS Kansai Chapter Symposium on VLSI Technology and Circuits 2021報告会
- Invited
- Data Source
  KAKENHI-PROJECT-20K14786
[Presentation] A 0.0053-mm 2 6-bit Fully-Standard-Cell-Based Synthesizable SAR ADC in 65 nm CMOS2019
- Author(s)
  Naoki Ojima, Zule Xu, and Tetsuya Iizuka
- Organizer
  IEEE NEWCAS 2019
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17K14684

Xu Zule 徐 祖楽

Research Projects

Research Products

Synthesizable Mixed-Signal Integrated Circuits for Agile Development of Analog AI Sensor NodesPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Review Section

Research Institution

Research on Ultra-Low Power Ring-Oscillator Based Frequency Synthesizer for Wireless Sensor NodesPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

[Journal Article] A fractional-N MASH2-k FDC phase-locked loop architecture enabling higher-order quantisation noise shaping2022

Author(s)

Journal Title

DOI

Data Source

[Journal Article] Analysis of strong-arm comparator with auxiliary pair for offset calibration2022

Author(s)

Journal Title

DOI

Data Source

[Journal Article] Analysis and simulation of MOSFET-based gate-voltage-independent capacitor2022

Author(s)

Journal Title

DOI

Data Source

[Journal Article] An All-Standard-Cell-Based Synthesizable SAR ADC with Nonlinearity-Compensated RDAC2021

Author(s)

Journal Title

DOI

Data Source

[Journal Article] Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector2019

Author(s)

Journal Title

Data Source

[Journal Article] A Saturating-Integrator-Based Behavioral Model of Ring Oscillator Facilitating PLL Design2017

Author(s)

Journal Title

DOI

NAID

ISSN

Language

Data Source

[Presentation] An All-Standard-Cell-Based Synthesizable SAR ADC with Nonlinearity-Compensated RDAC2022

Author(s)

Organizer

Data Source

[Presentation] A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter2022

Author(s)

Organizer

Data Source

[Presentation] A Charge-Redistribution Multi-Bit Stochastic-Resonance ADC Enhancing SNDR for Weak Input Signal2022

Author(s)

Organizer

Data Source

[Presentation] A 0.79-1.16-GHz Synthesizable Fractional-N PLL Using DTC-Based Multi-Stage Injection with Dithering-Assisted Local Skew Calibration Achieving －232.8-dB FoMref2021

Author(s)

Organizer

Data Source

[Presentation] Low-Power and Low-Noise Clock Generation: A Fractional-N Hybrid CDAC-Embedded Sampling PLL and a Class-C Complementary Colpitts Crystal Oscillator2021

Author(s)

Organizer

Data Source

[Presentation] A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with －80-dBc Reference Spur2021

Author(s)

Organizer

Data Source

[Presentation] A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with －80-dBc Reference Spur2021

Author(s)

Organizer

Data Source

[Presentation] A 0.0053-mm 2 6-bit Fully-Standard-Cell-Based Synthesizable SAR ADC in 65 nm CMOS2019

Author(s)

Organizer

Data Source

Xu Zule 徐祖楽