Nakamura Kazuyuki 中村和之

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NAKAMURA Kazuyuki 中村和之

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Researcher Number	60336097
Other IDs
External Links
Affiliation (Current)	2025: 九州工業大学, マイクロ化総合技術センター, 教授
Affiliation (based on the past Project Information) *help	2008 – 2024: Kyushu Institute of Technology, マイクロ化総合技術センター, 教授 2007: Kyushu Institute of Technology, マイクロ化総合技術センタ一, 教授 2002 – 2005: 九州工業大学, マイクロ化総合技術センター, 助教授
Review Section/Research Field	Principal Investigator Electron device/Electronic equipment / Basic Section 21060:Electron device and electronic equipment-related / 電子デバイス・機器工学 / Science and Engineering
Keywords	Principal Investigator SRAM / 素子ばらつき / CMOS / 連想メモリ / TCAM / レシオレス / 不揮発メモリ / インターフェース / システムLSI / LUTカスケード … More / 人工知能 / ニューラルネットワーク / Interface / 低電圧 / LSI / 経年劣化 / 動作マージン / ばらつき / 素子劣化 / アナログ回路 / PLL / 画像処理 / 高速通信 / SoC / Cascade / AI / 脳型LSI / ニューラルネット / 推論 / 超低電圧 / ハードウエアエンジン / 検索 / 低消費電力 / CAM / Multi-value logic / Device fluctuation / Band-width / Coding / Serial Communication / System in a Package / インターフェイス / コーディング / バンド幅 / O / I / 多値伝送 / シリアル通信 / non-volatile memory / image Processing / device variataion / Communication / System-LSI / System-on-A-Chip / スタティックノイズマージン / スタティックノイズマージ / SNM / ノイズマージン / メモリ / マージン / 環境変動 / 環境変化 / 最適化 / インターフェース回路 / ワーストケース / リファレンス回路 / マナログ回路 / レギュレータ / 製造後補正 / トリミング / 集積回路 Less

メモリカスケード型ニューロモルフィックLSIのフリーEDA環境による設計と実証Principal Investigator
- Principal Investigator
  
  中村和之
- Project Period (FY)
  2024 – 2026
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 21060:Electron device and electronic equipment-related
- Research Institution
  Kyushu Institute of Technology
メモリカスケード構成による記憶駆動型人工知能LSIの実現に関する研究Principal Investigator
- Principal Investigator
  
  中村和之
- Project Period (FY)
  2021 – 2024
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 21060:Electron device and electronic equipment-related
- Research Institution
  Kyushu Institute of Technology
Study on Realization of Brain-like Hardware by Sequential Driving of Ratio-less Tri-level Associative MemoryPrincipal Investigator
- Principal Investigator
  
  Nakamura Kazuyuki
- Project Period (FY)
  2018 – 2022
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 21060:Electron device and electronic equipment-related
- Research Institution
  Kyushu Institute of Technology
Study on fully digital ternary content addressable memory for high-speed processing of the big data.Principal Investigator
- Principal Investigator
  
  NAKAMURA KAZUYUKI
- Project Period (FY)
  2015 – 2017
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  Kyushu Institute of Technology
Study on fully digital ratio-less SRAM design for avoiding the variability and aging effects of device characteristicsPrincipal Investigator
- Principal Investigator
  
  NAKAMURA KAZUYUKI
- Project Period (FY)
  2012 – 2014
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  Kyushu Institute of Technology
Study on automatic operating margin maximization for analog VLSI circuits with the endurance for device characteristic variation and aging degradation.Principal Investigator
- Principal Investigator
  
  NAKAMURA Kazuyuki
- Project Period (FY)
  2009 – 2011
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  Kyushu Institute of Technology
Study on novel analog design method using post-fabrication trimming with CMOS non-volatile memoriesPrincipal Investigator
- Principal Investigator
  
  NAKAMURA Kazuyuki
- Project Period (FY)
  2007 – 2008
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  Kyushu Institute of Technology
Study on Ultra High-bandwidth Interconnect Circuits for System-in-a-packagePrincipal Investigator
- Principal Investigator
  
  NAKAMURA Kazuyuki
- Project Period (FY)
  2004 – 2005
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  KYUSHU INSTITUTE OF TECHNOLOGY
耐ばらつき超高バンド幅SoCマクロ間インターコネクト回路技術の研究Principal Investigator
- Principal Investigator
  
  中村和之
- Project Period (FY)
  2002 – 2003
- Research Category
  
  Grant-in-Aid for Scientific Research on Priority Areas
- Review Section
  
  Science and Engineering
- Research Institution
  Kyushu Institute of Technology
Study on Ultra High-bandwidth Interconnect Circuits for System-on-a-chipPrincipal Investigator
- Principal Investigator
  
  NAKAMURA Kazuyuki
- Project Period (FY)
  2002 – 2003
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  電子デバイス・機器工学
- Research Institution
  KYUSHU INSTITUTE OF TECHNOLOGY

[Journal Article] Design and measurement of fully digital ternary content addressable memory using ratioless static random access memory cells and hierarchical-AND matching comparator2018
- Author(s)
  D. Nishikata, M. A. Bin Mohd Ali, K. Hosoda, H.Matsumoto, K. Nakamura
- Journal Title
  
  Japanese Journal of Applied Physics
  
  Volume: 57 Issue: 4S Pages: 04FF11-04FF11
- DOI
  10.7567/jjap.57.04ff11
- NAID
  120006778228
- Peer Reviewed / Open Access / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K06021, KAKENHI-PROJECT-18K04266
[Journal Article] Self-stabilization techniques for intermediate power level in stacked-Vdd integrated circuits using DC-balanced coding methods2016
- Author(s)
  Yusuke Kohara, Naoya Kubo, Tomofumi Nishiyama, Taiki Koizuka, Mohammad Alimudin, Amirul Rahmat, Hitoshi Okamura, Tomoyuki Yamanokuchi, Kazuyuki Nakamura
- Journal Title
  
  Japanese Journal of Applied Physics
  
  Volume: 55 Issue: 4S Pages: 04EF06-04EF06
- DOI
  10.7567/jjap.55.04ef06
- NAID
  210000146329
- Peer Reviewed / Acknowledgement Compliant / Open Access
- Data Source
  KAKENHI-PROJECT-15K06021
[Journal Article] Ratioless full-complementary 12-transistor static random access memory for ultra low supply voltage operation2015
- Author(s)
  Takahiro Kondo, Hiromasa Yamamoto, Satoko Hoketsu, Hitoshi Imi, Hitoshi Okamura, Kazuyuki Nakamura
- Journal Title
  
  Japanese Journal of Applied Physics
  
  Volume: ５４ Issue: 4S Pages: 04DD11-04DD11
- DOI
  10.7567/jjap.54.04dd11
- NAID
  120006782185
- Peer Reviewed / Acknowledgement Compliant / Open Access
- Data Source
  KAKENHI-PROJECT-24560408
[Journal Article] Complementary Metal Oxide Semiconductor Operational Amplifier Offset Calibration Technique Using Closed Loop Offset Amplifier and Folded-Alternated Resistor String Digital-to-Analog Converter2012
- Author(s)
  Hiroyuki Morimoto, Hiroaki Goto, Hajime Fujiwara, Kazuyuki Nakamura
- Journal Title
  
  Japanese Journal of Applied Physics
  
  Volume: Vol.51 No.2 Issue: 2S Pages: 02BE10-02BE10
- DOI
  10.1143/jjap.51.02be10
- NAID
  120006782184
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21560356
[Journal Article] An Electrically Adjustable 3-Terminal Regulator for Post-Fabrication Level-Trimming with a Reliable 1-Wire Serial I/O2011
- Author(s)
  H. Morimoto, H. Koike, K. Nakamura
- Journal Title
  
  IEICE Trans. Electron.
  
  Volume: E94-C Issue: 6 Pages: 945-952
- DOI
  10.1587/transele.E94.C.945
- NAID
  10029804120
- ISSN
  0916-8524, 1745-1353
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21560356
[Journal Article] An Optimal Design Method for Complementary Metal Oxide Semiconductor Even-Stage Ring Oscillators Containing Latches2010
- Author(s)
  Y. Kohara, M. Asano, Y. Kawakami, Y. Uchida, H. Koike, K. Nakamura
- Journal Title
  
  Japanese Journal of Applied Physics
  
  Volume: Vol. 49, Issue 4
- NAID
  120006782186
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21560356
[Journal Article] An Optimal Design Method for Complementary Metal Oxide Semiconductor Even-Stage Ring Oscillators Containing Latches2010
- Author(s)
  Yusuke Kohara, Masaharu Asano, Yoshihiro Kawakami, Yasuhisa Uchida, Hiroki Koike, Kazuyuki Nakamura
- Journal Title
  
  Japanese Journal of Applied Physics
  
  Volume: Volume 49, Issue 4
- NAID
  120006782186
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21560356
[Journal Article] LSI間高速通信用4値I/0回路の設計2004
- Author(s)
  白木良典, 中村和之
- Journal Title
  
  電子情報通信学会2004年ソサイエティ大会発表論文概要集
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560302
[Journal Article] Design of the 4-level I/O circuit for high-speed interconnection for LSIs2004
- Author(s)
  Yoshinori Shiraki, Kazuyuki Nakamura
- Journal Title
  
  2004 Digest of IEICE Society Conference
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-16560302
[Journal Article] LSI間高速通信用4値I/O回路の設計2004
- Author(s)
  白木良典, 中村和之
- Journal Title
  
  電子情報通信学会2004年ソサイエティ大会発表論文概要集
- Data Source
  KAKENHI-PROJECT-16560302
[Journal Article] LSI間高速通信用4値I/O回路の設計2004
- Author(s)
  白木良典, 中村和之
- Journal Title
  
  電子情報通信学会2004年ソサイエティ大会発表論文概要集
- Data Source
  KAKENHI-PROJECT-16560302
[Journal Article] Long-Term Data Retention Test Method for Ferroelectric RAM2003
- Author(s)
  Hiroki Koike, Kazuyuki Nakamura et al.
- Journal Title
  
  IEICE Transactions on Electronics VOL.J86-C, No.8
  
  Pages: 902-912
- NAID
  110003202110
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-14550325
[Journal Article] 強誘電体メモリ(FeRAM)の長期データ保持特性テスト法2003
- Author(s)
  小池洋紀, 中村和之他
- Journal Title
  
  電子情報通信学会論文誌 J86-C, No.8
  
  Pages: 902-912
- NAID
  110003202110
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14550325
[Journal Article] Super-Parallel Link technology for Tbps Inter-chip communication2002
- Author(s)
  Kazuyuki, Nakamura
- Journal Title
  
  2002 Workshop for Circuits and System in Karuizawa
  
  Pages: 221-226
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-14550325
[Journal Article] Analog bit-map analysis using image processing technique for large scale non-volatile memories.2002
- Author(s)
  Kazuyuki Nakamura
- Journal Title
  
  2002 IEICE Society Conference
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-14550325
[Journal Article] LSI間のTbps通信を目指すスーパーパラレルリンク技術の概要2002
- Author(s)
  中村和之
- Journal Title
  
  2002年回路とシステム(軽井沢)ワークショップ論文集
  
  Pages: 221-226
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14550325
[Journal Article] 大規模不揮発メモリLSIのアナログビットマップ解析と画像処理の適用2002
- Author(s)
  中村和之
- Journal Title
  
  2002年電子情報通信学会ソサエティ大会講演論文集
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14550325
[Journal Article] Analog bit-map analysis for large scale non-volatile memories2002
- Author(s)
  Tomomi Yano, Hiroki Koike, Kazuyuki Nakamura
- Journal Title
  
  2002 IEICE System LSI Workshop in Biwako
  
  Pages: 283-286
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-14550325
[Journal Article] 大規模不揮発メモリLSIのアナログビットマップ解析システム2002
- Author(s)
  矢野智美, 小池洋紀, 中村和之
- Journal Title
  
  第6回システムLSI(琵琶湖)ワークショップ論文集(ポスターセッション
  
  Pages: 283-286
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14550325
[Patent] 半導体装置及びニューラルネットワークの構成方法2019
- Inventor(s)
  中村和之
- Industrial Property Rights Holder
  九州工業大学
- Industrial Property Rights Type
  特許
- Industrial Property Number
  2019-069485
- Filing Date
  2019
- Data Source
  KAKENHI-PROJECT-18K04266
[Patent] 符号変換回路及び並列信号変換送受信システム2016
- Inventor(s)
  小原祐輔、久保直也、中村和之
- Industrial Property Rights Holder
  小原祐輔、久保直也、中村和之
- Industrial Property Rights Type
  特許
- Industrial Property Number
  2016-053531
- Filing Date
  2016-03-17
- Data Source
  KAKENHI-PROJECT-15K06021
[Patent] 半導体記憶装置2013
- Inventor(s)
  中村和之、齊藤貴彦、岡村均
- Industrial Property Rights Holder
  中村和之、齊藤貴彦、岡村均
- Industrial Property Rights Type
  特許
- Filing Date
  2013-03-22
- Overseas
- Data Source
  KAKENHI-PROJECT-24560408
[Patent] 半導体記憶装置2012
- Inventor(s)
  中村和之、齋藤貴彦、岡村均
- Industrial Property Rights Holder
  九州工業大学
- Industrial Property Number
  2012-076414
- Filing Date
  2012-03-29
- Data Source
  KAKENHI-PROJECT-21560356
[Patent] 半導体記憶装置2011
- Inventor(s)
  中村和之、齋藤貴彦
- Industrial Property Rights Holder
  九州工業大学
- Industrial Property Number
  2011-035109
- Filing Date
  2011-02-21
- Data Source
  KAKENHI-PROJECT-21560356
[Patent] 電子デバイス2008
- Inventor(s)
  森本浩之, 中村和之
- Industrial Property Rights Holder
  九州工業大学
- Filing Date
  2008-01-29
- Data Source
  KAKENHI-PROJECT-19560347
[Presentation] Vth-Shiftable SRAM Cell TEGs for Direct Measurement for the immunity of the Threshold Voltage Variability2017
- Author(s)
  S. Yamaguchi, H. Imi, S. Tokumaru, T Kondo, H. Yamamoto, K. Nakamura
- Organizer
  IEEE International Conference on Microelectronic Test Structures (ICMTS) 2017
- Place of Presentation
  Grenoble, FRANCE
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K06021
[Presentation] Fully Digital Ternary Content Addressable Memory using Ratio-less SRAM Cells and Hierarchical-AND Matching Comparator for Ultra-low-voltage Operation2017
- Author(s)
  D. Nishikata, M. A. Bin Mohd Ali, K. Hosoda, H.Matsumoto, K. Nakamura
- Organizer
  2017 International Conference on Solid State Devices and Materials
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K06021
[Presentation] Vth-Shiftable SRAM Cell TEGs for Direct Measurement for the immunity of the Threshold Voltage Variability2016
- Author(s)
  S. Yamaguchi, H. Imi, S. Tokumaru, K. Nakamura
- Organizer
  IEEE/ACM Workshop on Variability Modeling and Characterization
- Place of Presentation
  Austin,TX,USA
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K06021
[Presentation] A Measurement of Ratio-less 12-transistor SRAM cell Operation at Ultra-low Supply-voltage2014
- Author(s)
  T. Kondo, H. Yamamoto, H. Imi, H. Okamura, K. Nakamura
- Organizer
  International Conference on Solid State Devices and Materials(SSDM)
- Place of Presentation
  Tsukuba, Japan
- Year and Date
  2014-09-10
- Data Source
  KAKENHI-PROJECT-24560408
[Presentation] ＣＭＯＳＳＲＡＭセルのしきい値電圧ばらつき耐性評価用ＴＥＧの設計及び評価2014
- Author(s)
  伊見　仁，徳丸　翔吾，岡村　均，中村　和之
- Organizer
  LSIとシステムのワークショップ2014
- Place of Presentation
  北九州国際会議場
- Year and Date
  2014-05-26
- Data Source
  KAKENHI-PROJECT-24560408
[Presentation] A Ratio-Less 10-Transistor Cell and Static Column Retention Loop Structure for Fully Digital SRAM Design2013
- Author(s)
  Saito, T. ; Okamura, H. ; Yamamoto, H. ; Nakamura, K.
- Organizer
  2012 4th IEEE International Memory Workshop (IMW)
- Place of Presentation
  Milan, Italy
- Data Source
  KAKENHI-PROJECT-24560408
[Presentation] Mosaic SRAM Cell TEGs with Intentionally-added Device Variability for Confirming the Ratio-less SRAM Operation2013
- Author(s)
  Hitoshi Okamura, Takahiko Saito, Hiroaki Goto, Masahiro Yamamoto and Kazuyuki Nakamura
- Organizer
  IEEE International Conference on Microelectronic Test Structures (ICMTS 2013)
- Place of Presentation
  Osaka, Japan
- Data Source
  KAKENHI-PROJECT-24560408
[Presentation] A Ratio-Less 10-Transistor Cell and Static Column Retention Loop Structure for Fully Digital SRAM2012
- Author(s)
  T. Saito, H. Okamura, M. Yamamoto, K. Nakamura
- Organizer
  2012 4th IEEE International Memory Workshop (IMW)
- Place of Presentation
  Milano Italy
- Year and Date
  2012-05-29
- Data Source
  KAKENHI-PROJECT-21560356
[Presentation] A Universal Test Structure for the Direct Measurement of the Design Margin of Even-Stage Ring Oscillators with CMOS Latch2012
- Author(s)
  Y. Hirakawa, A. Motomura,K. Ota,N. Mimura, K. Nakamura
- Organizer
  IEEE International Conference on Microelectronic Test Structures (ICMTS) 2012
- Place of Presentation
  San Diego USA
- Year and Date
  2012-03-20
- Data Source
  KAKENHI-PROJECT-21560356
[Presentation] A Universal Test Structure for the Direct Measurement of the Design Margin of Even-Stage Ring Oscillators with CMOS Latch2012
- Author(s)
  Y.Hirakawa, A. Motomura,K. Ota,N. Mimura, K. Nakamura
- Organizer
  IEEE International Conference on Microelectronic Test Structures (ICMTS) 2012
- Place of Presentation
  San Diego, USA
- Data Source
  KAKENHI-PROJECT-21560356
[Presentation] An Experimental Verification of the Design Margin Analysis Method for Even-Stage Ring Oscillators with CMOS Latch2011
- Author(s)
  Y. Hirakawa, N. Mimura, A. Motomura, K. Nakamura
- Organizer
  International Conference on Solid State Devices and Materials(SSDM)
- Place of Presentation
  Nagoya, Japan
- Data Source
  KAKENHI-PROJECT-21560356
[Presentation] 省面積抵抗ストリング DAC と閉ループ・オフセット検出を用いた CMOS オペアンプのオフセット校正2011
- Author(s)
  森本浩之、後藤弘明、藤原宗、中村
- Organizer
  デザインガイア 2011
- Place of Presentation
  宮崎市
- Year and Date
  2011-11-28
- Data Source
  KAKENHI-PROJECT-21560356
[Presentation] CMOS偶数段リング発振回路の設計マージンの測定2011
- Author(s)
  平川、本村、三村、中村
- Organizer
  電子情報通信学会 2011 総合大会
- Place of Presentation
  東京
- Year and Date
  2011-03-15
- Data Source
  KAKENHI-PROJECT-21560356
[Presentation] 電源遷移時間を考慮した偶数段リング発振回路発振領域の検討2011
- Author(s)
  三村法寛・平川豊・中村和之
- Organizer
  電子情報通信学会 2011総合大会
- Place of Presentation
  東京都市大学
- Year and Date
  2011-03-15
- Data Source
  KAKENHI-PROJECT-21560356
[Presentation] An Experimental Verification of the Design Margin Analysis Method for Even-Stage Ring Oscillators with CMOS Latch2011
- Author(s)
  Y. Hirakawa, N. Mimura, A. Motomura, K. Nakamura
- Organizer
  2011 International Conference on Solid State Devices and Materials(SSDM)
- Place of Presentation
  Nagoya Japan
- Year and Date
  2011-09-29
- Data Source
  KAKENHI-PROJECT-21560356
[Presentation] CMOS Op-amp Offset Calibration Technique Using a Closed Loop Offset Amplifier and Compact Resistor String DAC2011
- Author(s)
  H. Morimoto, H. Koike, K. Nakamura
- Organizer
  2011 International Conference on Solid State Devices and Materials(SSDM)
- Place of Presentation
  Nagoya, Japan
- Data Source
  KAKENHI-PROJECT-21560356
[Presentation] CMOS Op-amp Offset Calibration Technique Using a Closed Loop Offset Amplifier and Compact Resistor String DAC2011
- Author(s)
  H. Morimoto, H. Goto, H. Fujiwara, K. Nakamura
- Organizer
  2011 International Conference on Solid State Devices and Materials(SSDM)
- Place of Presentation
  Nagoya Japan
- Year and Date
  2011-09-29
- Data Source
  KAKENHI-PROJECT-21560356
[Presentation] CMOS偶数段リング発振回路の設計マージンの測定2011
- Author(s)
  平川豊・本村綾美・三村法寛・中村和之
- Organizer
  電子情報通信学会 2011総合大会
- Place of Presentation
  東京都市大学
- Year and Date
  2011-03-16
- Data Source
  KAKENHI-PROJECT-21560356
[Presentation] 電源遷移時間を考慮した偶数段リング発振回路発振領域の検討2011
- Author(s)
  三村、平川、中村
- Organizer
  電子情報通信学会 2011 総合大会
- Place of Presentation
  東京
- Year and Date
  2011-03-15
- Data Source
  KAKENHI-PROJECT-21560356
[Presentation] An Electrically Adjustable 3-Terminal Regulator with Post-Fabrication Level-Trimming Function2010
- Author(s)
  Hiroyuki Morimoto, Hiroki Koike, Kazuyuki Nakamura
- Organizer
  15th Asia and South Pacific Design Automation Conference (ASP-DAC 2010)
- Place of Presentation
  採択済み
- Data Source
  KAKENHI-PROJECT-19560347
[Presentation] 複数個のラッチを有する CMOS 偶数段リング発振回路の最適設計2010
- Author(s)
  平川、小原、川上、中村
- Organizer
  LSI とシステムのワークショップ 2010
- Place of Presentation
  北九州市
- Year and Date
  2010-05-18
- Data Source
  KAKENHI-PROJECT-21560356
[Presentation] 複数個のラッチを有するCMOS偶数段リング発振回路の最適設計2010
- Author(s)
  平川豊, 小原祐輔, 川上義弘, 中村和之
- Organizer
  LSIとシステムのワークショップ2010
- Place of Presentation
  北九州国際会議場
- Year and Date
  2010-05-18
- Data Source
  KAKENHI-PROJECT-21560356
[Presentation] 片チャネルラッチ構成の偶数段リング発振回路の検討2010
- Author(s)
  小原、平川、中村
- Organizer
  電子情報通信学会 2010 総合大会
- Place of Presentation
  仙台市
- Year and Date
  2010-03-16
- Data Source
  KAKENHI-PROJECT-21560356
[Presentation] 片チャネルラッチ構成の偶数段リング発振回路の検討2010
- Author(s)
  小原祐輔、平川豊、中村和之
- Organizer
  電子情報通信学会2010総合大会
- Place of Presentation
  東北大学
- Year and Date
  2010-03-16
- Data Source
  KAKENHI-PROJECT-21560356
[Presentation] ユニバーサルSRAM TEGによるSRAM動作マージンの評価2009
- Author(s)
  野田和徳, 齋藤慶顕, 中村和之
- Organizer
  電子情報通信学会全国大会
- Place of Presentation
  愛媛大学
- Year and Date
  2009-03-17
- Data Source
  KAKENHI-PROJECT-19560347
[Presentation] CMOS不揮発メモリとその設計法に関する研究開発及び事業化2008
- Author(s)
  中村和之
- Organizer
  電子情報通信学会全国大会
- Place of Presentation
  北九州学術研究都市
- Year and Date
  2008-03-21
- Data Source
  KAKENHI-PROJECT-19560347
[Presentation] Ratio-less 10Tr-SRAMセルとColumn Retention Loop構造による完全デジタルSRAMの設計及び評価
- Author(s)
  山本裕允、齋藤貴彦、岡村均、中村和之
- Organizer
  LSIとシステムのワークショップ 2013
- Place of Presentation
  北九州国際会議場
- Data Source
  KAKENHI-PROJECT-24560408

1. YOSHIDA Mika (50336096)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
2. MORIMOTO Hiroyuki

# of Collaborated Projects: 1 results

# of Collaborated Products: 1 results

Nakamura Kazuyuki 中村 和之

NAKAMURA Kazuyuki 中村 和之

Research Projects

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Co-Researchers

メモリカスケード型ニューロモルフィックLSIのフリーEDA環境による設計と実証Principal Investigator

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メモリカスケード構成による記憶駆動型人工知能LSIの実現に関する研究Principal Investigator

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Study on Realization of Brain-like Hardware by Sequential Driving of Ratio-less Tri-level Associative MemoryPrincipal Investigator

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Study on fully digital ternary content addressable memory for high-speed processing of the big data.Principal Investigator

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Study on fully digital ratio-less SRAM design for avoiding the variability and aging effects of device characteristicsPrincipal Investigator

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Study on automatic operating margin maximization for analog VLSI circuits with the endurance for device characteristic variation and aging degradation.Principal Investigator

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Study on novel analog design method using post-fabrication trimming with CMOS non-volatile memoriesPrincipal Investigator

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Study on Ultra High-bandwidth Interconnect Circuits for System-in-a-packagePrincipal Investigator

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耐ばらつき超高バンド幅SoCマクロ間インターコネクト回路技術の研究Principal Investigator

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Study on Ultra High-bandwidth Interconnect Circuits for System-on-a-chipPrincipal Investigator

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[Journal Article] Design and measurement of fully digital ternary content addressable memory using ratioless static random access memory cells and hierarchical-AND matching comparator2018

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NAID

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[Journal Article] Self-stabilization techniques for intermediate power level in stacked-Vdd integrated circuits using DC-balanced coding methods2016

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DOI

NAID

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[Journal Article] Ratioless full-complementary 12-transistor static random access memory for ultra low supply voltage operation2015

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Nakamura Kazuyuki 中村和之

NAKAMURA Kazuyuki 中村和之