Namba Kazuteru 難波一輝

… Alternative Names

Kazuteru NAMBA 難波一輝

NAMBA Kazuteru 難波一輝

Less

Researcher Number	60359594
Other IDs
External Links
Affiliation (Current)	2025: 千葉大学, 大学院情報学研究院, 准教授
Affiliation (based on the past Project Information) *help	2025: 千葉大学, 大学院情報学研究院, 准教授 2022 – 2023: 千葉大学, 大学院情報学研究院, 准教授 2019 – 2022: 千葉大学, 大学院工学研究院, 准教授 2017: 千葉大学, 大学院工学研究院, 准教授 2016: 千葉大学, 大学院融合科学研究科, 准教授 … More 2015: 千葉大学, 融合科学研究科(研究院), 准教授 2007 – 2010: 千葉大学, 大学院・融合科学研究科, 助教 2003: Chiba University, Faculty of Engineering, Assistance, 工学部, 助手 Less
Review Section/Research Field	Principal Investigator Basic Section 60040:Computer system-related / Computer system / Computer system/Network Except Principal Investigator Medium-sized Section 21:Electrical and electronic engineering and related fields / Basic Section 21060:Electron device and electronic equipment-related / Medium-sized Section 63:Environmental analyses and evaluation and related fields / 電子デバイス・機器工学 / Electron device/Electronic equipment
Keywords	Principal Investigator メモリシステム / 計算機システム / 相変化メモリ / 高信頼化 / 低電力化 / ニューラルネット / 誤差許容計算 / 回路とシステム / 書き込み時間削減 / 符号 … More / PCM / ディペンダブル・コンピューティング / システムオンチップ / ディペンダブルコンピューティング … More Except Principal Investigator FPGA / 相変化 / 脳型システム / 原子移動 / 人工知能素子 / 超格子 / 超高速 / 高速 / 人工シナプス / 高速化 / 人工知能 / 相変化材料 / シナプス素子 / 画像 / 高解像度 / リモートセンシング / 多ビーム / マイクロストリップアンテナ / アレーアンテナ / SAR画像信号処理 / マルチビーム / マイクロ波リモートセンシング / 合成開口レーダ / Error Recovery / Reconfiguration / Fault Detection / Defect Tolerance / Defect / Programmable Chip / カバリッジ / SOC / マルチコンテキスト / 誤り回復 / 再構成 / 故障検出 / 欠陥救済 / 欠陥 / プログラマブルチップ / スキャンFF / 2線式論理 / シグナルインテグリティ / テスト容易化 / 遅延故障 / テスト容易化設計 / スキャン設計 / ラッチ / VLSI / ソフトエラー / CAD / 回路設計 Less

Ultra-High-Performance, Innovative Neuromorphic Information Processing Devices
- Principal Investigator
  
  インユウ
- Project Period (FY)
  2025 – 2028
- Research Category
  
  Grant-in-Aid for Scientific Research (A)
- Review Section
  
  Medium-sized Section 21:Electrical and electronic engineering and related fields
- Research Institution
  Gunma University
Ultrafast Superlattice Phase-change Artificial Synapse
- Principal Investigator
  
  Yin You
- Project Period (FY)
  2021 – 2023
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Review Section
  
  Basic Section 21060:Electron device and electronic equipment-related
- Research Institution
  Gunma University
Write latency reduction on PCM for approximate computingPrincipal Investigator
- Principal Investigator
  
  Kazuteru NAMBA
- Project Period (FY)
  2020 – 2022
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Chiba University
Improvement on High Resolution of Environmental Remote Sensed Imagery using Multi Beam Synthetic Aperture Radar
- Principal Investigator
  
  Josaphat Tetuko Sri Sumantyo
- Project Period (FY)
  2019 – 2021
- Research Category
  
  Grant-in-Aid for Challenging Research (Exploratory)
- Review Section
  
  Medium-sized Section 63:Environmental analyses and evaluation and related fields
- Research Institution
  Chiba University
Write time reduction code for PRAMPrincipal Investigator
- Principal Investigator
  
  Namba Kazuteru
- Project Period (FY)
  2015 – 2017
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system
- Research Institution
  Chiba University
Proposal of test data reduction method for scan design facilitating delay fault testingPrincipal Investigator
- Principal Investigator
  
  NAMBA Kazuteru
- Project Period (FY)
  2009 – 2010
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Chiba University
VLSI CIRCUIT DESIGNS with SOFT ERROR TOLERANCE
- Principal Investigator
  
  ITO Hideo
- Project Period (FY)
  2007 – 2009
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  Chiba University
Design for Fault-Tolerant Programmable Chips
- Principal Investigator
  
  ITO Hideo
- Project Period (FY)
  2001 – 2003
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  電子デバイス・機器工学
- Research Institution
  Chiba University

All 2023 2022 2021 2020 2018 2017 2016 2010 2009 2008 2007 Other

All Journal Article Presentation Patent

[Journal Article] Low Power Neural Network by Reducing SRAM Operating Voltage2022
- Author(s)
  Kozu Keisuke、Tanabe Yuya、Kitakami Masato、Namba Kazuteru
- Journal Title
  
  IEEE Access
  
  Volume: 10 Pages: 116982-116986
- DOI
  10.1109/access.2022.3219208
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-20K11728
[Journal Article] On coding for endurance enhancement and error control of phase change memories (PCMs) with write latency reduction2018
- Author(s)
  Kazuteru Namba and Fabrizio Lombardi
- Journal Title
  
  IEEE Trans. Very Large Scale Integr. Syst.
  
  Volume: 26 Issue: 2 Pages: 230-238
- DOI
  10.1109/tvlsi.2017.2766362
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K00069
[Journal Article] A Coding Scheme for Write Time Improvement of Phase Change Memory (PCM) Systems2016
- Author(s)
  Kazuteru Namba and Fabrizio Lombardi
- Journal Title
  
  IEEE Trans. Multi-Scale Comput. Syst.
  
  Volume: Vol.2, No.4 Issue: 4 Pages: 291-296
- DOI
  10.1109/tmscs.2016.2605098
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K00069
[Journal Article] A Calibration Technique for DVMC with Delay Time Controllable Inverter2016
- Author(s)
  Ri Cui and Kazuteru Namba
- Journal Title
  
  IPSJ Transactions on System LSI Design Methodology
  
  Volume: 9 Issue: 0 Pages: 30-36
- DOI
  10.2197/ipsjtsldm.9.30
- NAID
  130005126053
- ISSN
  1882-6687
- Language
  English
- Peer Reviewed / Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-15K00069
[Journal Article] Chiba Scan Delay Fault Testing with Short Test Application Time2010
- Author(s)
  K.Namba, H.Ito
- Journal Title
  
  J.Electronic Test. : Theory & Appl. Vol.26, No.
  
  Pages: 6667-677
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21700053
[Journal Article] Chiba Scan Delay Fault Testing with Short Test Application Time2010
- Author(s)
  難波一輝, 伊藤秀男
- Journal Title
  
  Journal of Electronic Testing : Theory and Applications
  
  Volume: 26 Pages: 667-677
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21700053
[Journal Article] Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Path2009
- Author(s)
  Kentaroh Katoh, Kazuteru Namba, Hideo Ito
- Journal Title
  
  IEICE Trans. Inf. & Syst. E92-D
  
  Pages: 433-442
- NAID
  10026807952
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19560335
[Journal Article] Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability2009
- Author(s)
  Shuagyu Ruan, Kazuteru Namba, Hideo Ito
- Journal Title
  
  IEICE Trans.Inf. & Syst. E92-D
  
  Pages: 1534-1541
- NAID
  10026810480
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19560335
[Journal Article] Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability2009
- Author(s)
  Shuagyu Ruan, Kazuteru Namba, Hideo Ito
- Journal Title
  
  IEICE Trans.Inf.&Syst. Vol.E92-D, No.8
  
  Pages: 1534-1541
- NAID
  10026810480
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19560335
[Journal Article] Design for Delay Fault Testability of 2-Rail Logic Circuits2009
- Author(s)
  Kentaroh Katoh, Kazuteru Namba, Hideo Ito
- Journal Title
  
  IEICE Trans. Inf. & Syst. E92-D
  
  Pages: 336-341
- NAID
  10026807731
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19560335
[Journal Article] Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger2008
- Author(s)
  Yoichi Sasaki, Kazuteru Namba, Hideo Ito
- Journal Title
  
  J.Electronic Test.:Theory & Appl. Vol.24, No.1-3
  
  Pages: 11-19
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19560335
[Journal Article] Scan FF Reordering for Test Volume Reduction in Chiba-Scan Architecture
- Author(s)
  K.Matsumoto, K.Namba, H.Ito
- Journal Title
  
  IPSJ Trans.Syst.LSI Des.Method 掲載予定
- NAID
  110009598054
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21700053
[Patent] 遅延故障テスト容易化耐ソフトエラーラッチ2007
- Inventor(s)
  池田卓史, 難波一輝, 伊藤秀男
- Industrial Property Rights Holder
  千葉大学
- Industrial Property Number
  2007-111043
- Filing Date
  2007-04-19
- Data Source
  KAKENHI-PROJECT-19560335
[Patent] 半導体集積回路2007
- Inventor(s)
  加藤健太郎, 難波一輝, 伊藤秀男
- Industrial Property Rights Holder
  国立大学法人千葉大学
- Industrial Property Number
  2007-233388
- Filing Date
  2007-09-07
- Data Source
  KAKENHI-PROJECT-19560335
[Patent] 半導体集積回路及び半導体集積回路の検査方法2007
- Inventor(s)
  加藤健太郎, 難波一輝, 伊藤秀男
- Industrial Property Rights Holder
  国立大学法人千葉大学
- Industrial Property Number
  2007-233346
- Filing Date
  2007-09-07
- Data Source
  KAKENHI-PROJECT-19560335
[Patent] 半導体集積回路2007
- Inventor(s)
  池田卓史, 難波一輝, 伊藤秀男
- Industrial Property Rights Holder
  国立大学法人千葉大学
- Industrial Property Number
  2007-111043
- Filing Date
  2007-04-19
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] Stuck-at Fault Tolerance in DNN Using Outliers and Sampling2023
- Author(s)
  Tomohiro Ishii, Donghyun Kwon and Kazuteru Namba
- Organizer
  Japan-Korea Joint Workshop on Complex Communication Sciences
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-20K11728
[Presentation] 外れ値を用いたDNNの縮退故障に対するエラー耐性の向上2023
- Author(s)
  石井智大, 難波一輝
- Organizer
  IEICE FIIS
- Data Source
  KAKENHI-PROJECT-20K11728
[Presentation] 外れ値と標本化を用いたDNNの縮退故障に対するエラー耐性の向上2022
- Author(s)
  石井智大, 難波一輝
- Organizer
  IEICE DC
- Data Source
  KAKENHI-PROJECT-20K11728
[Presentation] Stuck-at fault tolerance in DNN using statistical data2022
- Author(s)
  Tomohiro Ishii and Kazuteru Namba
- Organizer
  IEEE Pacific Rim International Symposium on Dependable Computing
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-20K11728
[Presentation] Low power quantized neural network by reducing the operating voltage of SRAM2022
- Author(s)
  Ji Wu, Kazuteru Namba
- Organizer
  IEICE DC
- Data Source
  KAKENHI-PROJECT-20K11728
[Presentation] 動作電圧引き下げによる低消費電力ニューラルネットワークのための6T-8TハイブリッドSRAM2022
- Author(s)
  余若曦, 難波一輝
- Organizer
  IEICE DC
- Data Source
  KAKENHI-PROJECT-20K11728
[Presentation] マルチレベルセル相変化メモリを用いた連想メモリ2021
- Author(s)
  高橋知宏, 難波一輝
- Organizer
  信学技報, DC
- Data Source
  KAKENHI-PROJECT-20K11728
[Presentation] Relaxing device requirements for non-linearity in Deep Neural Networks accelerators with Phase Change Memory2021
- Author(s)
  Keisuke Kozu and Kazuteru Namba
- Organizer
  IEEE Int'l Conf. Consum. Electron. Taiwan
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-20K11728
[Presentation] SRAMの動作電圧引き下げによるニューラルネットワークの低電力化2021
- Author(s)
  高津啓佑, 難波一輝
- Organizer
  信学技報, DC
- Data Source
  KAKENHI-PROJECT-20K11728
[Presentation] 相変化メモリを用いた赤黒木構造の書き込み時間削減2020
- Author(s)
  楊昊天, 難波一輝
- Organizer
  信学技報, FIIS
- Data Source
  KAKENHI-PROJECT-20K11728
[Presentation] Cycle-Set Code：MLC PCMの書き込み遅延時間削減のための符号2017
- Author(s)
  陳星宇, 難波一輝
- Organizer
  FTC研究会
- Data Source
  KAKENHI-PROJECT-15K00069
[Presentation] 耐ソフトエラー性を有するRSフリップフロップ2010
- Author(s)
  中島健吾, 難波一輝, 伊藤秀男
- Organizer
  電子情報通信学会,機能集積情報システム研究会
- Place of Presentation
  京都
- Year and Date
  2010-03-05
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] Test Vector Reduction by Reordering Flip-flops for Scan Architecture with Delay Fault Testability2010
- Author(s)
  松本清紀, 難波一輝, 伊藤秀男
- Organizer
  Workshop on RTL and High Level Testing
- Place of Presentation
  Shanghai SHERATON Hotel(中華人民共和国)
- Year and Date
  2010-12-06
- Data Source
  KAKENHI-PROJECT-21700053
[Presentation] 千葉大スキャンの接続順序変更によるテストパターン削減手法2010
- Author(s)
  松本清紀, 難波一輝, 伊藤秀男
- Organizer
  FTC研究会
- Place of Presentation
  サンロード吉備路,岡山県
- Year and Date
  2010-01-22
- Data Source
  KAKENHI-PROJECT-21700053
[Presentation] ソフトエラー訂正機能を有するBILBOフリップフロップ2010
- Author(s)
  難波一輝, 伊藤秀男
- Organizer
  電子情報通信学会,ディペンダブルコンピューティング研究会
- Place of Presentation
  東京
- Year and Date
  2010-04-13
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] BILBO FF with soft error correcting capability2010
- Author(s)
  Kazuteru NAMBA, Hideo ITO
- Organizer
  電子情報通信学会, ディペンダブルコンピューティング研究会
- Place of Presentation
  東京
- Year and Date
  2010-04-13
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] 耐ソフトエラー性を有するRSフリップフロップ2010
- Author(s)
  中島健吾, 難波一輝, 伊藤秀男
- Organizer
  電子情報通信学会, 機能集積情報システム研究会
- Place of Presentation
  京都
- Year and Date
  2010-03-05
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] 千葉大スキャンの接続順序変更によるテストパターン削減手法2010
- Author(s)
  松本清紀, 難波一輝, 伊藤秀男
- Organizer
  第62回FTC研究会
- Place of Presentation
  サンロード吉備路(岡山県)
- Year and Date
  2010-01-22
- Data Source
  KAKENHI-PROJECT-21700053
[Presentation] Test Vector Reduction by Reordering Flip-flops for Scan Architecture with Delay Fault Testability, Proc.2010
- Author(s)
  K.Matsumoto, K.Namba, H.Ito
- Organizer
  11th IEEE Workshop RTL & High Level Test.pp.111-116
- Place of Presentation
  Shanghai SHERATON Hotel,中華人民共和国
- Year and Date
  2010-12-06
- Data Source
  KAKENHI-PROJECT-21700053
[Presentation] ラッチ内2重ノード反転ソフトエラーの耐性設計2009
- Author(s)
  坂田雅俊, 難波一輝, 伊藤秀男
- Organizer
  電子情報通信学会,機能集積情報システム研究会
- Place of Presentation
  東京
- Year and Date
  2009-10-16
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] Testing of Switch Bloacks in Three-Dimensional FPGA2009
- Author(s)
  Takumi Hoshi, Kazuteru Namba, Hideo Ito
- Organizer
  2009 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT2009)
- Place of Presentation
  Chicago
- Year and Date
  2009-10-03
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] ラッチ内2重ノード反転ソフトエラーの耐性設計2009
- Author(s)
  坂田雅俊, 難波一輝, 伊藤秀男
- Organizer
  電子情報通信学会, 機能集積情報システム研究会
- Place of Presentation
  東京
- Year and Date
  2009-10-16
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] 遅延故障テスト容易化SHEラッチにおけるエンハンスドスキャンテスト2008
- Author(s)
  難波一輝, 伊藤秀男
- Organizer
  電子情報通信学会, 機能集積情報システム研究会
- Place of Presentation
  奈良市
- Year and Date
  2008-10-31
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] SEU/SET対策FFを用いた遅延故障テスト容易化スキャン構造2008
- Author(s)
  池田卓史, 難波一輝, 伊藤秀男
- Organizer
  2008年電子情報通信学会総合大会
- Place of Presentation
  北九州市
- Year and Date
  2008-03-18
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] ソフトエラーラッチの調査と分類2008
- Author(s)
  坂田雅俊, 難波一輝, 伊藤秀男
- Organizer
  電子情報通信学会, 機能集積情報システム研究会
- Place of Presentation
  筑波市
- Year and Date
  2008-06-27
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] Delay Fault Testability on Two-Rail Logic Circuits2008
- Author(s)
  Kazuteru Namba, Hideo Ito
- Organizer
  23^<rd> IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT2008)
- Place of Presentation
  Boston
- Year and Date
  2008-10-02
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] Soft Error Hardened FF Capable of Detecting Wide Error Pulse2008
- Author(s)
  Shuangyou Ruan, Kazuteru Namba, Hideo Ito
- Organizer
  23^<rd> IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT2008)
- Place of Presentation
  Boston
- Year and Date
  2008-10-02
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] 幅の広いエラーパルス検出機能を有する耐ソフトエラーFF2008
- Author(s)
  阮双玉, 難波一輝, 伊藤秀男
- Organizer
  電子情報通信学会, ディペンダブルコンピューティング研究会
- Place of Presentation
  東京
- Year and Date
  2008-04-23
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] ソフトエラーラッチの検出不可能な固定故障の影響2008
- Author(s)
  中島健吾, 難波一輝, 伊藤秀男
- Organizer
  電子情報通信学会, ディペンダブルコンピューティング研究会
- Place of Presentation
  東京
- Year and Date
  2008-04-23
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] Path Delay Fault Test Set for Two-Rail Logic Circuits2008
- Author(s)
  Kazuteru Namba, Hideo Ito
- Organizer
  2008 14^<th> IEEE Pacific Rim International Symposium on Dependable Computing (PRDC2008)
- Place of Presentation
  Taipei
- Year and Date
  2008-12-15
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] 耐ソフトエラーラッチの検出不可能な固定故障の影響2008
- Author(s)
  中島健吾, 難波一輝, 伊藤秀男
- Organizer
  電子情報通信学会, ディペンダブルコンピューティング研究会
- Place of Presentation
  東京
- Year and Date
  2008-04-23
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] Design for Delay Fault Testing of 2-Rail Logic Circuits2008
- Author(s)
  Kentaroh Katoh, Kazuteru Namba, Hideo Ito
- Organizer
  Indonesia-Japan Joint Scientific Symposium 2008
- Place of Presentation
  Chiba
- Year and Date
  2008-09-10
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] 2線式論理回路に対するパス遅延故障テスト集合2008
- Author(s)
  難波一輝, 伊藤秀男
- Organizer
  電子情報通信学会, 機能集積情報システム研究会
- Place of Presentation
  千葉市
- Year and Date
  2008-03-07
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] 二線式論理を用いたFPGAのソフトエラーに対するフォールトセキュア性2008
- Author(s)
  三浦健宏, 難波一輝, 伊藤秀男
- Organizer
  電子情報通信学会, ディペンダブルコンピューティング研究会
- Place of Presentation
  東京
- Year and Date
  2008-02-08
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing2007
- Author(s)
  Takashi Ikeda, Kazuteru Namba, Hideo Ito
- Organizer
  22^<nd> IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT2007)
- Place of Presentation
  Rome
- Year and Date
  2007-09-27
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] 遅延故障テスト容易化ソフトエラーラッチの設計2007
- Author(s)
  池田卓史, 難波一輝, 伊藤秀男
- Organizer
  電子情報通信学会, ディペンダブルコンピューティング研究会
- Place of Presentation
  東京
- Year and Date
  2007-04-20
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] 2線式論理回路における遅延故障テスト2007
- Author(s)
  難波一輝, 伊藤秀男
- Organizer
  電子情報通信学会, 機能集積情報システム
- Place of Presentation
  神戸
- Year and Date
  2007-10-26
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] Soft Error Hardened Latch Scheme for Enhanced Sean Based Delay Fault Testing2007
- Author(s)
  Takashi Ikeda, Kazuteru Namba, and Hideo Ito
- Organizer
  22th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems(DFT2007)
- Place of Presentation
  Rome
- Year and Date
  2007-09-27
- Data Source
  KAKENHI-PROJECT-19560335

1. Yin You (10520124)

# of Collaborated Projects: 3 results

# of Collaborated Products: 0 results
2. ITO Hideo (90042647)

# of Collaborated Projects: 2 results

# of Collaborated Products: 28 results
3. KITAKAMI Masato (20282832)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
4. Josaphat Tetuko Sri Sumantyo (40396693)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
5. 加藤健太郎 (10569859)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results

Namba Kazuteru 難波 一輝

Kazuteru NAMBA 難波 一輝

NAMBA Kazuteru 難波 一輝

Research Projects

Research Products

Co-Researchers

Ultra-High-Performance, Innovative Neuromorphic Information Processing Devices

Principal Investigator

Project Period (FY)

Research Category

Review Section

Research Institution

Ultrafast Superlattice Phase-change Artificial Synapse

Principal Investigator

Project Period (FY)

Research Category

Review Section

Research Institution

Write latency reduction on PCM for approximate computingPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Review Section

Research Institution

Improvement on High Resolution of Environmental Remote Sensed Imagery using Multi Beam Synthetic Aperture Radar

Principal Investigator

Project Period (FY)

Research Category

Review Section

Research Institution

Write time reduction code for PRAMPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Proposal of test data reduction method for scan design facilitating delay fault testingPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

VLSI CIRCUIT DESIGNS with SOFT ERROR TOLERANCE

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Design for Fault-Tolerant Programmable Chips

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

[Journal Article] Low Power Neural Network by Reducing SRAM Operating Voltage2022

Author(s)

Journal Title

DOI

Data Source

[Journal Article] On coding for endurance enhancement and error control of phase change memories (PCMs) with write latency reduction2018

Author(s)

Journal Title

DOI

Data Source

[Journal Article] A Coding Scheme for Write Time Improvement of Phase Change Memory (PCM) Systems2016

Author(s)

Journal Title

DOI

Data Source

[Journal Article] A Calibration Technique for DVMC with Delay Time Controllable Inverter2016

Author(s)

Journal Title

DOI

NAID

ISSN

Language

Data Source

[Journal Article] Chiba Scan Delay Fault Testing with Short Test Application Time2010

Author(s)

Journal Title

Namba Kazuteru 難波一輝

Kazuteru NAMBA 難波一輝

NAMBA Kazuteru 難波一輝