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Masuda Yutaka
増田 豊
Connect your ORCID iD
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Researcher Number
60845527
Other IDs
Affiliation (Current)
2022: 名古屋大学, 情報学研究科, 助教
Affiliation (based on the past Project Information)
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2019 – 2022: 名古屋大学, 情報学研究科, 助教
Review Section/Research Field
Principal Investigator
1001:Information science, computer engineering, and related fields
/
Basic Section 60040:Computer system-related
Except Principal Investigator
Basic Section 60040:Computer system-related
/
Computer system
Keywords
Principal Investigator
近似コンピューティング / 低消費電力設計 / クリティカルパス・アイソレーション / ビット幅削減 / 適応的電圧制御 / 高信頼設計 / CAD / 計算重要度
Except Principal Investigator
計算機システム / 光集積回路
…
More
/ 低消費電力設計 / 設計最適化 / 低消費電力 / エネルギー効率化 / システムオンチップ / 環境発電 / マイクロプロセッサ / 低消費電力・高エネルギー密度
Less
Research Projects
(
4
results)
Research Products
(
10
results)
Co-Researchers
(
4
People)
Project Start Year (Newest)
Project Start Year (Oldest)
光と電子が密に融合する集積回路のアーキテクチャと設計技術
Principal Investigator
Ishihara Tohru
Project Period (FY)
2020 – 2022
Research Category
Grant-in-Aid for Scientific Research (B)
Review Section
Basic Section 60040:Computer system-related
Research Institution
Nagoya University
近似コンピューティング回路の遅延特性と計算重要度を融合した新CAD技術の開発
Principal Investigator
Principal Investigator
増田 豊
Project Period (FY)
2020 – 2022
Research Category
Grant-in-Aid for Early-Career Scientists
Review Section
Basic Section 60040:Computer system-related
Research Institution
Nagoya University
Study on design optimization of VLSI circuits for efficient approximate computing
Principal Investigator
Principal Investigator
Masuda Yutaka
Project Period (FY)
2019 – 2020
Research Category
Grant-in-Aid for Research Activity Start-up
Review Section
1001:Information science, computer engineering, and related fields
Research Institution
Nagoya University
Research on computing infrastructure aimed at realizing an IoT society to come
Principal Investigator
Ishihara Tohru
Project Period (FY)
2017 – 2019
Research Category
Grant-in-Aid for Scientific Research (B)
Research Field
Computer system
Research Institution
Nagoya University
All
2021
2020
All
Presentation
[Presentation] Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design
2021
Author(s)
Yutaka Masuda, Jun Nagayama, TaiYu Cheng, Tohru Ishihara, Yoichi Momiyama, and Masanori Hashimoto
Organizer
IEEE Design, Automation and Test in Europe Conference (DATE)
Data Source
KAKENHI-PROJECT-20K19767
[Presentation] Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design
2021
Author(s)
Yutaka Masuda, Jun Nagayama, TaiYu Cheng, Tohru Ishihara, Yoichi Momiyama, and Masanori Hashimoto
Organizer
IEEE Design, Automation and Test in Europe Conference (DATE)
Int'l Joint Research
Data Source
KAKENHI-PROJECT-19K24341
[Presentation] An Accuracy Reconfigurable Multiply-Accumulate Unit Based on Operand-Decomposed Mitchell’s Multiplier
2021
Author(s)
L. Hou, Y. Masuda, T. Ishihara
Organizer
Workshop on Synthesis And System Integration of Mixed Information technologies
Int'l Joint Research
Data Source
KAKENHI-PROJECT-17H01712
[Presentation] Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling
2020
Author(s)
Yutaka Masuda, Jun Nagayama, TaiYu Cheng, Tohru Ishihara, Yoichi Momiyama, and Masanori Hashimoto
Organizer
International Workshop on Logic & Synthesis (IWLS)
Int'l Joint Research
Data Source
KAKENHI-PROJECT-19K24341
[Presentation] Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling
2020
Author(s)
Yutaka Masuda, Jun Nagayama, TaiYu Cheng, Tohru Ishihara, Yoichi Momiyama, and Masanori Hashimoto
Organizer
International Workshop on Logic & Synthesis (IWLS)
Data Source
KAKENHI-PROJECT-20K19767
[Presentation] クリティカルパス・アイソレーションとビット幅削減を用いた過電圧スケーリング向け省電力設計手法
2020
Author(s)
増田豊, 長山準, 鄭泰禹, 石原亨, 籾山陽一, 橋本昌宜
Organizer
情報処理学会DA シンポジウム
Data Source
KAKENHI-PROJECT-19K24341
[Presentation] クリティカルパス・アイソレーションとビット幅削減を用いた過電圧スケーリング向け省電力設計手法
2020
Author(s)
増田豊, 長山準, 鄭泰禹, 石原亨, 籾山陽一, 橋本昌宜
Organizer
情報処理学会DA シンポジウム
Data Source
KAKENHI-PROJECT-20K19767
[Presentation] ファジングを用いた近似コンピューティング回路の品質検証手法の一検討
2020
Author(s)
吉末和樹,増田豊,石原亨
Organizer
デザインガイア2020
Data Source
KAKENHI-PROJECT-20K19767
[Presentation] Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy
2020
Author(s)
Kiyawat Khyati、Masuda Yutaka、Shiomi Jun、Ishihara Tohru
Organizer
IEEE Computer Society Annual Symposium on VLSI
Int'l Joint Research
Data Source
KAKENHI-PROJECT-17H01712
[Presentation] ポストムーア時代に向けた回路設計検証技術
2020
Author(s)
増田豊
Organizer
第7回NCESシンポジウム
Data Source
KAKENHI-PROJECT-19K24341
# of Projects (Dsc)
# of Projects (Asc)
1.
Ishihara Tohru
(30323471)
# of Collaborated Projects:
2 results
# of Collaborated Products:
2 results
2.
塩見 準
(40809795)
# of Collaborated Projects:
1 results
# of Collaborated Products:
0 results
3.
納富 雅也
(50393799)
# of Collaborated Projects:
1 results
# of Collaborated Products:
0 results
4.
小野寺 秀俊
(80160927)
# of Collaborated Projects:
1 results
# of Collaborated Products:
0 results
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