Masuda Yutaka 増田豊

Researcher Number	60845527
Other IDs
Affiliation (Current)	2025: 名古屋大学, 情報学研究科, 准教授
Affiliation (based on the past Project Information) *help	2021 – 2025: 名古屋大学, 情報学研究科, 准教授 2019 – 2021: 名古屋大学, 情報学研究科, 助教
Review Section/Research Field	Principal Investigator Basic Section 60040:Computer system-related / 1001:Information science, computer engineering, and related fields Except Principal Investigator Broad Section J / Basic Section 60040:Computer system-related / Computer system
Keywords	Principal Investigator 近似コンピューティング / 複製型ファジング / 品質検証基盤 / 計算結果の品質 (QoR) / 計算重要度 / CAD / 高信頼設計 / 適応的電圧制御 / ビット幅削減 / クリティカルパス・アイソレーション / 低消費電力設計 … More Except Principal Investigator … More 光ニューラルネットワーク / 計算機システム / 高次多値変調 / 省エネルギー / AI推論 / 光トランシーバ / 設計最適化 / 低消費電力設計 / 光集積回路 / 光コンピューティング / 光電融合回路 / 低消費電力・高エネルギー密度 / マイクロプロセッサ / 環境発電 / システムオンチップ / エネルギー効率化 / 低消費電力 Less

複製型ファジングで切り拓く近似コンピューティング回路の品質検証基盤Principal Investigator
- Principal Investigator
  
  増田豊
- Project Period (FY)
  2024 – 2026
- Research Category
  
  Grant-in-Aid for Early-Career Scientists
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Nagoya University
Highly Energy Efficient and Broadband Information Processing Platform based on Optical Functional Circuits
- Principal Investigator
  
  石原亨
- Project Period (FY)
  2024 – 2028
- Research Category
  
  Grant-in-Aid for Scientific Research (S)
- Review Section
  
  Broad Section J
- Research Institution
  Nagoya University
Development of a novel CAD technique considering timing characteristics and computational importance of approximate computing circuitsPrincipal Investigator
- Principal Investigator
  
  Yutaka Masuda
- Project Period (FY)
  2020 – 2022
- Research Category
  
  Grant-in-Aid for Early-Career Scientists
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Nagoya University
Research on architecture of optoelectronic integrated circuits and their design methodology
- Principal Investigator
  
  Ishihara Tohru
- Project Period (FY)
  2020 – 2022
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Nagoya University
Study on design optimization of VLSI circuits for efficient approximate computingPrincipal Investigator
- Principal Investigator
  
  Masuda Yutaka
- Project Period (FY)
  2019 – 2020
- Research Category
  
  Grant-in-Aid for Research Activity Start-up
- Review Section
  
  1001:Information science, computer engineering, and related fields
- Research Institution
  Nagoya University
Research on computing infrastructure aimed at realizing an IoT society to come
- Principal Investigator
  
  Ishihara Tohru
- Project Period (FY)
  2017 – 2019
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system
- Research Institution
  Nagoya University

All 2024 2023 2022 2021 2020

All Journal Article Presentation

[Journal Article] Dynamic Verification Framework of Approximate Computing Circuits using Quality-Aware Coverage-Based Grey-Box Fuzzing2023
- Author(s)
  MASUDA Yutaka、HONDA Yusei、ISHIHARA Tohru
- Journal Title
  
  IEICE Trans. Fundamentals
  
  Volume: E106.A Issue: 3 Pages: 514-522
- DOI
  10.1587/transfun.2022VLP0002
- ISSN
  0916-8508, 1745-1337
- Year and Date
  2023-03-01
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20K19767
[Journal Article] Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling2022
- Author(s)
  MASUDA Yutaka、NAGAYAMA Jun、CHENG TaiYu、ISHIHARA Tohru、MOMIYAMA Yoichi、HASHIMOTO Masanori
- Journal Title
  
  IEICE Trans. Fundamentals
  
  Volume: E105.A Issue: 3 Pages: 509-517
- DOI
  10.1587/transfun.2021VLP0002
- NAID
  130008165469
- ISSN
  0916-8508, 1745-1337
- Year and Date
  2022-03-01
- Language
  English
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-20K19767
[Journal Article] Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation2021
- Author(s)
  HATTORI Naoki、SHIOMI Jun、MASUDA Yutaka、ISHIHARA Tohru、SHINYA Akihiko、NOTOMI Masaya
- Journal Title
  
  IEICE Trans. Fundamentals
  
  Volume: E104.A Issue: 11 Pages: 1477-1487
- DOI
  10.1587/transfun.2020KEP0016
- NAID
  130008109846
- ISSN
  0916-8508, 1745-1337
- Year and Date
  2021-11-01
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20H04155
[Journal Article] Optical-electronic implementation of artificial neural network for ultrafast and accurate inference processing2021
- Author(s)
  Hattori Naoki、Masuda Yutaka、Ishihara Tohru、Shiomi Jun、Shinya Akihiko、Notomi Masaya
- Journal Title
  
  Proc. AI and Optical Data Sciences II. International Society for Optics and Photonics
  
  Pages: 415-421
- DOI
  10.1117/12.2577966
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20H04155
[Journal Article] 集積ナノフォトニクスに基づく光ニューラルネットワークを対象とした回路アーキテクチャ探索2020
- Author(s)
  服部直樹, 増田豊, 石原亨, 塩見準, 新家昭彦, 納富雅也
- Journal Title
  
  第33回回路とシステムワークショップ論文集
  
  Volume: IEICE-VLD2019-137 Pages: 10-15
- NAID
  40022400516
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20H04155
[Presentation] An optoelectronic pipelined convolutional-RNN architecture for energy-efficient AI accelerator2024
- Author(s)
  Chunlu Wang, Yutaka Masuda, Tohru Ishihara
- Organizer
  Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-20H04155
[Presentation] 近似計算の品質検証に向けたファジングのフィードバック調整手法の一検討2023
- Author(s)
  本多佑成、増田豊、石原亨
- Organizer
  第 244 回 ARC・第 202 回 SLDM・第 62 回 EMB 合同研究発表会 (ETNET2023)
- Data Source
  KAKENHI-PROJECT-20K19767
[Presentation] An efficient fault injection algorithm for identifying unimportant FFs in approximate computing circuits2023
- Author(s)
  Jiaxuan Lu、Yutaka Masuda、Tohru Ishihara
- Organizer
  Design, Automation and Test in Europe Conference (DATE2023)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-20K19767
[Presentation] 近似計算回路の低消費電力化に向けた故障挿入を用いた冗長なフリップフロップの特定2023
- Author(s)
  陸佳萱、増田豊、石原亨
- Organizer
  電子情報通信学会 VLSI 設計技術研究会
- Data Source
  KAKENHI-PROJECT-20K19767
[Presentation] Importance evaluation methodology of FFs for design optimization of approximate computing circuit2022
- Author(s)
  Jiaxuan Lu、Yutaka Masuda、Tohru Ishihara
- Organizer
  24th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI2022)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-20K19767
[Presentation] Power-Aware Pruning for Ultrafast, Energy-Efficient, and Accurate Optical Neural Network Design2022
- Author(s)
  Naoki Hattori, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi
- Organizer
  Design Automation Conference (DAC)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-20H04155
[Presentation] Optoelectronic Implementation of Compact and Power-Efficient Recurrent Neural Networks2022
- Author(s)
  Taisei Ichikawa, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi
- Organizer
  IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-20H04155
[Presentation] 省面積と低電力を両立する光電融合RNN アーキテクチャ2022
- Author(s)
  市川大生, 増田豊, 石原亨, 新家昭彦, 納富雅也
- Organizer
  第35 回回路とシステムワークショップ論文集
- Data Source
  KAKENHI-PROJECT-20H04155
[Presentation] 近似コンピューティング回路の設計最適化に向けた計算重要度評価技術2021
- Author(s)
  陸佳萱, 増田豊, 石原亨
- Organizer
  第195回システムとLSIの設計技術研究
- Data Source
  KAKENHI-PROJECT-20K19767
[Presentation] An Accuracy Reconfigurable Multiply-Accumulate Unit Based on Operand-Decomposed Mitchell’s Multiplier2021
- Author(s)
  L. Hou, Y. Masuda, T. Ishihara
- Organizer
  Workshop on Synthesis And System Integration of Mixed Information technologies
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01712
[Presentation] Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design2021
- Author(s)
  Yutaka Masuda, Jun Nagayama, TaiYu Cheng, Tohru Ishihara, Yoichi Momiyama, and Masanori Hashimoto
- Organizer
  IEEE Design, Automation and Test in Europe Conference (DATE)
- Data Source
  KAKENHI-PROJECT-20K19767
[Presentation] Dynamic verification of approximate computing circuits using coverage-based grey-box fuzzing2021
- Author(s)
  K. Yoshisue, Y. Masuda, and T. Ishihara
- Organizer
  2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-20K19767
[Presentation] Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design2021
- Author(s)
  Yutaka Masuda, Jun Nagayama, TaiYu Cheng, Tohru Ishihara, Yoichi Momiyama, and Masanori Hashimoto
- Organizer
  IEEE Design, Automation and Test in Europe Conference (DATE)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19K24341
[Presentation] 近似コンピューティング回路の品質検証を高速化するファジングテスト法2021
- Author(s)
  本多佑成, 増田豊, 石原亨
- Organizer
  第195回システムとLSIの設計技術研究
- Data Source
  KAKENHI-PROJECT-20K19767
[Presentation] Optical-electronic implementation of artificial neural network for ultrafast and accurate inference processing2021
- Author(s)
  Hattori Naoki、Masuda Yutaka、Ishihara Tohru、Shiomi Jun、Shinya Akihiko、Notomi Masaya
- Organizer
  SPIE Conference 11703, AI and Optical Data Sciences II
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-20H04155
[Presentation] ファジングと高位合成を用いた近似コンピューティング回路のタイミング検証手法2021
- Author(s)
  熊谷僚太, 増田豊, 石原亨
- Organizer
  第195回システムとLSIの設計技術研究
- Data Source
  KAKENHI-PROJECT-20K19767
[Presentation] Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy2020
- Author(s)
  Kiyawat Khyati、Masuda Yutaka、Shiomi Jun、Ishihara Tohru
- Organizer
  IEEE Computer Society Annual Symposium on VLSI
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01712
[Presentation] Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling2020
- Author(s)
  Yutaka Masuda, Jun Nagayama, TaiYu Cheng, Tohru Ishihara, Yoichi Momiyama, and Masanori Hashimoto
- Organizer
  International Workshop on Logic & Synthesis (IWLS)
- Data Source
  KAKENHI-PROJECT-20K19767
[Presentation] クリティカルパス・アイソレーションとビット幅削減を用いた過電圧スケーリング向け省電力設計手法2020
- Author(s)
  増田豊, 長山準, 鄭泰禹, 石原亨, 籾山陽一, 橋本昌宜
- Organizer
  情報処理学会DA シンポジウム
- Data Source
  KAKENHI-PROJECT-19K24341
[Presentation] ポストムーア時代に向けた回路設計検証技術2020
- Author(s)
  増田豊
- Organizer
  第7回NCESシンポジウム
- Data Source
  KAKENHI-PROJECT-19K24341
[Presentation] Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling2020
- Author(s)
  Yutaka Masuda, Jun Nagayama, TaiYu Cheng, Tohru Ishihara, Yoichi Momiyama, and Masanori Hashimoto
- Organizer
  International Workshop on Logic & Synthesis (IWLS)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19K24341
[Presentation] 集積ナノフォトニクスに基づく光ニューラルネットワークを対象とした回路アーキテクチャ探索2020
- Author(s)
  服部直樹, 増田豊, 石原亨, 塩見準, 新家昭彦, 納富雅也
- Organizer
  第33回回路とシステムワークショップ
- Data Source
  KAKENHI-PROJECT-20H04155
[Presentation] ファジングを用いた近似コンピューティング回路の品質検証手法の一検討2020
- Author(s)
  吉末和樹，増田豊，石原亨
- Organizer
  デザインガイア2020
- Data Source
  KAKENHI-PROJECT-20K19767
[Presentation] クリティカルパス・アイソレーションとビット幅削減を用いた過電圧スケーリング向け省電力設計手法2020
- Author(s)
  増田豊, 長山準, 鄭泰禹, 石原亨, 籾山陽一, 橋本昌宜
- Organizer
  情報処理学会DA シンポジウム
- Data Source
  KAKENHI-PROJECT-20K19767

1. Ishihara Tohru (30323471)

# of Collaborated Projects: 3 results

# of Collaborated Products: 10 results
2. 小野寺秀俊 (80160927)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
3. 塩見準 (40809795)

# of Collaborated Projects: 1 results

# of Collaborated Products: 4 results
4. 納富雅也 (50393799)

# of Collaborated Projects: 1 results

# of Collaborated Products: 7 results
5. 長谷川浩 (40323802)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
6. 森洋二郎 (10722100)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results

Masuda Yutaka 増田 豊

Research Projects

Research Products

Co-Researchers

複製型ファジングで切り拓く近似コンピューティング回路の品質検証基盤Principal Investigator

Principal Investigator

Project Period (FY)

Research Category

Review Section

Research Institution

Highly Energy Efficient and Broadband Information Processing Platform based on Optical Functional Circuits

Principal Investigator

Project Period (FY)

Research Category

Review Section

Research Institution

Development of a novel CAD technique considering timing characteristics and computational importance of approximate computing circuitsPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Review Section

Research Institution

Research on architecture of optoelectronic integrated circuits and their design methodology

Principal Investigator

Project Period (FY)

Research Category

Review Section

Research Institution

Study on design optimization of VLSI circuits for efficient approximate computingPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Review Section

Research Institution

Research on computing infrastructure aimed at realizing an IoT society to come

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

[Journal Article] Dynamic Verification Framework of Approximate Computing Circuits using Quality-Aware Coverage-Based Grey-Box Fuzzing2023

Author(s)

Journal Title

DOI

ISSN

Year and Date

Language

Data Source

[Journal Article] Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling2022

Author(s)

Journal Title

DOI

NAID

ISSN

Year and Date

Language

Data Source

[Journal Article] Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation2021

Author(s)

Journal Title

DOI

NAID

ISSN

Year and Date

Language

Data Source

[Journal Article] Optical-electronic implementation of artificial neural network for ultrafast and accurate inference processing2021

Author(s)

Journal Title

DOI

Data Source

[Journal Article] 集積ナノフォトニクスに基づく光ニューラルネットワークを対象とした回路アーキテクチャ探索2020

Author(s)

Journal Title

NAID

Data Source

[Presentation] An optoelectronic pipelined convolutional-RNN architecture for energy-efficient AI accelerator2024

Author(s)

Organizer

Data Source

Masuda Yutaka 増田豊

[Presentation] 近似計算回路の低消費電力化に向けた故障挿入を用いた冗長なフリップフロップの特定2023