FUJIWARA Hideo 藤原秀雄

Researcher Number	70029346
Other IDs
External Links
Affiliation (based on the past Project Information) *help	2008 – 2010: Nara Institute of Science and Technology, 情報科学研究科, 教授 2003 – 2006: 奈良先端科学技術大学院大学, 情報科学研究科, 教授 1997 – 2000: 奈良先端科学技術大学院大学, 情報科学研究科, 教授 1994 – 1995: 奈良先端科学技術大学院大学, 情報科学研究科, 教授 1991 – 1992: 明治大学, 理工学部, 教授
Review Section/Research Field	Principal Investigator 計算機科学 / Computer system/Network / 情報工学
Keywords	Principal Investigator DESIGN FOR TESTABILITY / テスト容易化設計 / VLSI / テスト生成 / システムオンチップ / スキャン設計 / CORE-BAES DESIGN / CO-OPTIMIZATION / TEST ACCESS MECHANISM / TEST ARCHITECTURE … More / CONSECUTIVE TRANSPARENCY / CONSECUTIVE TESTABILITY / SYSTEM-ON-CHIP / コアベース設計 / 相互最適化 / テストアクセス機構 / テストアーキテクチャ / 連続透明 / 連続可検査 / CONTROLLER / DATA PATH / REGISTER TRANSFERLEVEL / DATA FLOW GRAPH / VLSITEST / HIGHLEVEL SYNTHESIS / SYNTHESIS FOR TESTABILITY / テスト容易化合物 / コントローラ / データパス / レジスタ転送レベル / データフローグラフ / VLSIテスト / 高位合成 / テスト容易化合成 / performance analysis / fault parallelizm / multi-processor system / parallel processing / test generation / VLSI circuit / 性能解析 / 故障並列法 / マルチプロセッサシステム / 並列処理 / 大規模論理回路 / Fault Detection / Algorithms / Test Generation / Logic Circuits / Neural Networks / ニュ-ラルネットワ-ク / 故障検査 / アルゴリズム / 論理回路 / ニューラルネットワーク / 設計自動化 / 高信頼性ネットワーク / ディペンダブルコンピューティング / 安全性(セキュリティ) / テスト容易性 / ネットワークオンチップ / VLSIのテスト / VLSI設計技術 Less

Basic Studies on Testability and Security for Network-on-ChipPrincipal Investigator
- Principal Investigator
  
  FUJIWARA Hideo
- Project Period (FY)
  2008 – 2010
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Nara Institute of Science and Technology
BASIC STUDIES ON TEST ARCHITECTURE AND DESIGN FOR TESTABILITY FOR SYSTEM-ON-CHIPPrincipal Investigator
- Principal Investigator
  
  FUJIWARA Hideo
- Project Period (FY)
  2003 – 2006
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  NARA INSTITUTE OF SCIENCE AND TECHNOLOGY
BASIC STUDIES ON VLSISYNTHESIS FOR TESTABILITY FROM HIGHER LEVELPrincipal Investigator
- Principal Investigator
  
  FUJIWARA Hideo
- Project Period (FY)
  1997 – 2000
- Research Category
  
  Grant-in-Aid for Scientific Research (B).
- Research Field
  
  計算機科学
- Research Institution
  NARA INSTITUTE OF SCIENCE AND TECHNOLOGY
Studies on parallel processing of test generation for VLSI circuitsPrincipal Investigator
- Principal Investigator
  
  FUJIWARA Hideo
- Project Period (FY)
  1994 – 1995
- Research Category
  
  Grant-in-Aid for General Scientific Research (C)
- Research Field
  
  計算機科学
- Research Institution
  Nara Institute of Science and Technology
Study on Neural Network for Test Generation of Large Scale Logic CircuitsPrincipal Investigator
- Principal Investigator
  
  FUJIWARA Hideo
- Project Period (FY)
  1991 – 1992
- Research Category
  
  Grant-in-Aid for General Scientific Research (C)
- Research Field
  
  情報工学
- Research Institution
  Meiji University

All 2011 2010 2009 2008 2007 2006 2005 2004 2003 Other

All Journal Article Presentation Book

[Book] ディジタルシステムの設計とテスト2004
- Author(s)
  藤原秀雄
- Total Pages
  262
- Publisher
  工学図書(株)
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] F-Scan : A DFT Method for Functional Scan at RTL2011
- Author(s)
  Marie Engelene Jimenez Obien, Satoshi Ohtake, Hideo Fujiwara
- Journal Title
  
  IEICE Trans. on Inf. and Syst. Vol.E94-D, No.1
  
  Pages: 104-113
- NAID
  10027989592
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300018
[Journal Article] セキュアスキャン設計のためのシフトレジスタ等価回路の列挙と合成2010
- Author(s)
  藤原克哉
- Journal Title
  
  電子情報通信学会和文論文誌D-I
  
  Volume: J93-D Pages: 2426-2436
- NAID
  110007880365
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300018
[Journal Article] A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint2010
- Author(s)
  Ryoichi Inoue, Toshinori Hosokawa, Hideo Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems Vol.E93-D, No.1
  
  Pages: 24-32
- NAID
  10026812987
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300018
[Journal Article] An Approach for Verification Assertions Reuse in RTL Test Pattern Generation2010
- Author(s)
  Maksim Jenihhin, Jaan Raik, Raimund Ubar, Taavi Viilukas, Hideo Fujiwara
- Journal Title
  
  Journal of Shanghai Normal University Vol.39, No.5
  
  Pages: 441-447
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300018
[Journal Article] RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences2010
- Author(s)
  Hongxia Fang, Krishnendu Chakrabarty, Hideo Fujiwara
- Journal Title
  
  Journal of Electronic Testing : Theory and Applications Volume 26, Issue 2
  
  Pages: 151-164
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300018
[Journal Article] Design and Optimization of Transparency-Based TAM for SoC Test2010
- Author(s)
  Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara
- Journal Title
  
  IEICE Trans. on Inf. and Syst. Vol.E93-D, No.6
  
  Pages: 1549-1559
- NAID
  10027987897
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300018
[Journal Article] A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification2010
- Author(s)
  Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara
- Journal Title
  
  IEICE Trans. on Information and Systems Vol.E93-D, No.7
  
  Pages: 1857-1865
- NAID
  10027363954
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300018
[Journal Article] A New Class of Easily Testable Assignment Decision Diagram2010
- Author(s)
  Norlina Paraman, Chia Yee Ooi, Ahmad Zuri Sha'ameri, Hideo Fujiwara
- Journal Title
  
  Malayaisan Journal Computer Science Vol.23, No.1
  
  Pages: 1-17
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300018
[Journal Article] セキュアスキャン設計のためのシフトレジスタ等価回路の列挙と合成2010
- Author(s)
  藤原克哉、藤原秀雄、オビエン・マリー・エンジェリン, 玉本英夫
- Journal Title
  
  電子情報通信学会和文論文誌D-I Vol.J93-D, No.11
  
  Pages: 2426-2436
- NAID
  110007880365
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300018
[Journal Article] 部分スルー可検査性に基づく順序回路のテスト生成法2009
- Author(s)
  岡伸也, Chia Yee Ooi, 市原英行, 井上智生, 藤原秀雄
- Journal Title
  
  電子情報通信学会和文論文誌D-I Vol.J92-D, No.12
  
  Pages: 2207-2216
- NAID
  110007482414
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300018
[Journal Article] A Non-Scan Design-for-Testability for Register-Transfer Level Circuits to Guarantee Linear-Depth Time Expansion Models2008
- Author(s)
  Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi
- Journal Title
  
  IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems Vol.27, No.9
  
  Pages: 1535-1544
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300018
[Journal Article] NoC-compatible Wrapper Design and Optimization Under Channel Bandwidth and Test Time Constraints2008
- Author(s)
  Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems Vol.E91-D, No.7
  
  Pages: 2008-2017
- NAID
  10026805045
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300018
[Journal Article] On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time2008
- Author(s)
  Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems Vol.E91-D, No.7
  
  Pages: 1999-2007
- NAID
  10026805015
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300018
[Journal Article] Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips2008
- Author(s)
  Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems Vol.E91-D, No.10
  
  Pages: 2440-2448
- NAID
  10026805953
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300018
[Journal Article] Reconfigured Scan Forest for Test Application Cost, Test Data Volume and Test Power Reduction2007
- Author(s)
  Dong Xiang, Kaiwei Li, Jiaguang Sun, Hideo Fujiwara
- Journal Title
  
  IEEE Trans. on Computers Vol.56, No.4
  
  Pages: 557-562
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] Error identification in at-speed scan BIST environment in the presence of circuit and tester speed mismatch2006
- Author(s)
  Yoshiyuki Nakamura, Thomas Clouqueur, Kewai K.Saluja, Hideo Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems Vol.E89-D, No.3
  
  Pages: 1165-1172
- NAID
  110004719394
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] A Memory Grouping Method for reducing Memory BIST Logic of System-on-Chips2006
- Author(s)
  Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems Vol.E89-D, No.4
  
  Pages: 1490-1497
- NAID
  110007504501
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] Instruction-Based Self-Testing of Delay Faults it Pipelined Processors2006
- Author(s)
  Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
- Journal Title
  
  IEEE Trans. on Very Large Scale Integration (VLSI) Systems Vol.14, No.11
  
  Pages: 1203-1215
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] System-on-Chip Test Scheduling with Reconfigurable Core Wrappers2006
- Author(s)
  Erik Larsson, Hideo Fujiwara
- Journal Title
  
  IEEE Trans. on Very Large Scale Integration (VLSI) Systems Vol.14, No.3
  
  Pages: 305-309
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] Non-Scan Design for Single-Port-Change Delay Fault Testability2006
- Author(s)
  Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara
- Journal Title
  
  IPSJ (Information Processing Society of Japan) Journal (Special Issue on Design Methodology of System LSIs) Vol.47, No.6
  
  Pages: 1619-1628
- NAID
  130000022321
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] A DET Method Based on Partially Strong Testability of RTL Data Paths to Guarantee Complete Fault Efficiency2006
- Author(s)
  Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara
- Journal Title
  
  Trans. of IEICE (DI) Vol.J89-D, No.8
  
  Pages: 1643-1653
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] A Low Power Deterministic Test Using Scan Chain Disable Technique2006
- Author(s)
  Zhiqiang You, Tsuyoshi Iwagaki, Michiko Inoue, Hideo Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems Vol.E89-D, No.6
  
  Pages: 1931-1939
- NAID
  110007503110
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] Effect of BIST Pretest on IC Defect Level2006
- Author(s)
  Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems Vol.E89-D No.10
  
  Pages: 2626-2636
- NAID
  110007538467
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths2005
- Author(s)
  Zhiqiang You, Ken'ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems Vol.E88-D, No.3
  
  Pages: 1940-1947
- NAID
  110003214398
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] Improving Test Effectiveness of Scan-Based BIST by Scan Chain Partitioning2005
- Author(s)
  Dong Xiang, Ming-jing Chen, Jia-guang Sun, Hideo Fujiwara
- Journal Title
  
  IEEE Trans. on CAD Vol.24, No.6
  
  Pages: 916-927
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] A Test Generation Method for Path Delay Faults Using Stuck-at Fault Test Generation Algorithms2005
- Author(s)
  Kouhei Ohtani, Satoshi Ohtake, Hideo Fujiwara
- Journal Title
  
  Trans. of IEICE (DI) (in Japanese) Vol.J88-D-I, No.6
  
  Pages: 1057-1064
- NAID
  110003203379
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] Software-Based Self-Test of Processors for Stuck-at Faults and Path Delay Faults2005
- Author(s)
  Michiko Inoue, Kazuko Kambe, Virendra Singh, Hideo Fujiwara
- Journal Title
  
  Trans. of IEICE (DI), (Invited Paper) (in Japanese) Vol.J88-D-I, No.6
  
  Pages: 1003-1011
- NAID
  110003203373
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST2005
- Author(s)
  Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems Vol.E88-D, No.6
  
  Pages: 1210-1216
- NAID
  110003214301
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] Classification of Sequential Circuits based on tau^k Notation and Its Applications2005
- Author(s)
  Chia Yee Ooi, Thomas Clouqueur, Hideo Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems Vol.E88-D, No.12
  
  Pages: 2738-2747
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] Delay Fault Testing of Processor Cores in Functional Mode2005
- Author(s)
  Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems Vol.E88-D, No.3
  
  Pages: 610-618
- NAID
  110003214225
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] Design for consecutive transparency method of RTL circuits2004
- Author(s)
  Tomokazu Yoneda, Hideo Fujiwara
- Journal Title
  
  Trans. of IEICE (DI) (in Japanese) Vol.J87-D-I, No.12
  
  Pages: 1110-1118
- NAID
  110003203297
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency2004
- Author(s)
  Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara
- Journal Title
  
  Journal of Electronic Testing : Theory and Applications Vol.20, No.3
  
  Pages: 315-323
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] Efficient Test Solutions for Core-based Designs2004
- Author(s)
  Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng
- Journal Title
  
  IEEE Trans. on CAD Vol.23, No.5
  
  Pages: 758-775
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] A Design Scheme for Delay Testing of Controllers Using StateTransition Information2004
- Author(s)
  Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
- Journal Title
  
  IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences Vol.E87-A, No.12
  
  Pages: 3200-3207
- NAID
  110003212858
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] Preemptive System-on-Chip Test Scheduling2004
- Author(s)
  Erik Larsson, Hideo Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems. Vol.E87-D, No.3
  
  Pages: 620-629
- NAID
  110003213919
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] A DFT Selection Method for Reducing Test Application Time of System-on-Chips2004
- Author(s)
  Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems Vol.E87-D, No.3
  
  Pages: 609-619
- NAID
  110003213918
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] Non-Scan Design for Testability for Synchronous Sequential Circuits Based on Fault-Oriented Conflict Analysis2003
- Author(s)
  Dong Xiang, Shan Gu, Hideo Fujiwara
- Journal Title
  
  IEICE Transactions on Information and Systems Vol.E86-D, No.11
  
  Pages: 2407-2417
- NAID
  10012452264
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] Internally balanced structure with hold and switching functions2003
- Author(s)
  Chikateru Jinno, Michiko Inoue, Hideo Fujiwara
- Journal Title
  
  Trans. of IEICE (DI) (in Japanese) Vol.J86-D-I, No.9
  
  Pages: 682-690
- NAID
  110003171271
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] A Non-Scan DFT Method at Register-Transfer Level to Achieve 100% Fault Efficiency,2003
- Author(s)
  Satoshi Ohtake, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara
- Journal Title
  
  IPSJ (Information Processing Society of Japan) Journal. Vol.44, No.5
  
  Pages: 1266-1275
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] Design for two-pattern testability of controller-data path circuits2003
- Author(s)
  Md.Altaf-Ul-Amin, Satoshi Ohtake, Hideo Fujiwara
- Journal Title
  
  IEICE Trans. on Information and Systems Vol.E86-D, No.6
  
  Pages: 1042-1049
- NAID
  110004024945
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] A Test Generation Method for Path Delay Faults in Sequential Circuits with Discontinuous Reconvergence Structure2003
- Author(s)
  Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
- Journal Title
  
  Trans, of IEICE (DI) (in Japanese) Vol.J86-D-I, No.12
  
  Pages: 872-883
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] Hierarchical BIST : Test-Per-Clock BIST Scheme with Low Overhead2003
- Author(s)
  Ken-ichi Yamaguchi, Michiko Inoue, Hideo Fujiwara
- Journal Title
  
  Trans. of IEICE (in Japanese) Vol.J86-D-I, No.7
  
  Pages: 469-479
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] A new class of sequential circuits with combinational test generation complexity for path delay faults2003
- Author(s)
  Shunjiro Miwa, Satoshi Ohtake, Hideo Fujiwara
- Journal Title
  
  Trans. of IEICE (DI) (in Japanese) Vol.186-D-I, No.11
  
  Pages: 809-820
- NAID
  110003171214
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] Non-Scan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution2003
- Author(s)
  Dong Xiang, Yi Xu, Hideo Fujiwara
- Journal Title
  
  IEEE Trans. on Computers Vol.52, No.8
  
  Pages: 1063-1075
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint2003
- Author(s)
  Toshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka, Hideo Fujiwara
- Journal Title
  
  IEICE Trans. on Information and Systems Vol.E86-D, No.12
  
  Pages: 2674-2683
- NAID
  10012560209
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Journal Article] Diagnosing At-speed Scan BIST Circuit : Using a Low Speed and Low Memory Tester
- Author(s)
  Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara
- Journal Title
  
  IEEE Trans. on VLSI Systems (to appear)
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300018
[Presentation] Secure Scan Design Using Shift Register Equivalents against Differential Behavior Attack2011
- Author(s)
  Hideo Fujiwara, Katsuya Fujiwara, Hideo Tamamoto
- Organizer
  16th Asia and South Pacific Design Automation Conference
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Secure Scan Design Using Shift Register Equivalents against Differential Behavior Attack2011
- Author(s)
  Hideo Fujiwara
- Organizer
  16th Asia and South Pacific Design Automation Conference
- Place of Presentation
  横浜
- Year and Date
  2011-01-28
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Aging Test Strategy and Adaptive Test Scheduling for SoC Failure Prediction2010
- Author(s)
  Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara
- Organizer
  IEEE International On-Line Testing Symposium
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Graph Theoretical Approach for Scan Cell Reordering to Minimize Peak Shift Power2010
- Author(s)
  Jaynarayan Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara
- Organizer
  ACM Great Lake Symposium on VLSI
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Delay Fault ATPG for F-Scannable RTL Circuits2010
- Author(s)
  Marie Engelene Jimenez Obien, Satoshi Ohtake, Hideo Fujiwara
- Organizer
  IEEE Int.Symp. on Communications and Information Technologies
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Test Pattern Selection to Optimize Delay Test Quality with a Limited Size of Test Set2010
- Author(s)
  Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata, Hideo Fujiwara
- Organizer
  2010 IEEE European Test Symposium
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] On Minimization of Test Application Time for RAS2010
- Author(s)
  Raghavendra Adiga, Arpit Gandhi, Virendra Singh, Kewal K.Saluja, Hideo Fujiwara, Adit D.Singh
- Organizer
  23rd Internaional Conference on VLSI Design
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] An Approach for Verification Assertions Reuse in RTL Test Pattern Generation2010
- Author(s)
  Maksim Jenihhin, Jaan Raik, Hideo Fujiwara, Raimund Ubar, Taavi Viilukas
- Organizer
  11th IEEE Workshop on RTL and High Level Testing
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Bipartite Full Scan Design : A DFT Method for Asynchronous Circuits2010
- Author(s)
  Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara
- Organizer
  Proc. of IEEE the 19th Asian Test Symposium
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] A Method of Unsensitizable Path Identification using High Level Design Information2010
- Author(s)
  Satoshi Ohtake, Naotsugu Ikeda, Michiko Inoue, Hideo Fujiwara
- Organizer
  5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Seed Ordering and Selection for High Quality Delay Test2010
- Author(s)
  Tomokazu Yoneda, Michiko Inoue, Akira Taketani, Hideo Fujiwara
- Organizer
  Proc. of IEEE the 19th Asian Test Symposium
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Capture in Turn Scan for Reduction of Test Date Volume, Test Application Time and Test Power2010
- Author(s)
  Zhiqiang You, Jiedi Huang, Michiko Inoue, Jishun Kuang, Hideo Fujiwara
- Organizer
  Proc. of IEEE the 19th Asian Test Symposium
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] SREEP-2 : SR-Equivalent Generator for Secure and Testable Scan Design2010
- Author(s)
  Katsuya Fujiwara
- Organizer
  11th IEEE workshop on RTL and High Level Testing
- Place of Presentation
  上海、中国
- Year and Date
  2010-12-06
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Thermal-Uniformity-Aware X-Filling to Reduce Temperature-Induced Delay Variation for Accurate At-Speed Testing2010
- Author(s)
  Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Hideo Fujiwara
- Organizer
  28th IEEE VLSI Test Symposium
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] SREEP : Shift Register Equivalents Enumeration and Synthesis Program for Secure Scan Design2010
- Author(s)
  Katsuya Fujiwara, Hideo Fujiwara, Marie Engelene J.Obien, Hideo Tamamoto
- Organizer
  13th IEEE International Symposium on Design and Diagnosis of Electronic Circuits and Systems
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Secure and Testable Scan Design Using Extended de Bruijn Graphs2010
- Author(s)
  Hideo Fujiwara
- Organizer
  15th Asia and South Pacific Design Automation Conference
- Place of Presentation
  Taipei, Taiwan
- Year and Date
  2010-01-19
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Constrained ATPG for Functional RTL Circuits Using F-Scan2010
- Author(s)
  Marie Engelene J.Obien, Satoshi Ohtake, Hideo Fujiwara
- Organizer
  2010 IEEE International Test Conference
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] SREEP : Shift Register Equivalents Enumeration and Synthesis Program for Secure Scan Design2010
- Author(s)
  Katsuya Fujiwara
- Organizer
  13th IEEE International Symposium on Design and Diagnosis of Electronic Circuits and Systems
- Place of Presentation
  Vienna, Austria
- Year and Date
  2010-04-15
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] RedSOCs-3D : Thermal-safe Test Scheduling for 3D-Stacked SoC2010
- Author(s)
  Fawnizu Azmadi Hussin, Thomas Edison Chua Yu, Tomokazu Yoneda, Hideo Fujiwara
- Organizer
  2010 Asia Pacific Conference on Circuits and Systems
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] A Synthesis Method to Propagate False Path Information from RTL to Gate Level2010
- Author(s)
  Satoshi Ohtake, Hiroshi Iwata, Hideo Fujiwara
- Organizer
  13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Scan Cells Reordering to Minimize Peak Power during Test Cycle : A Graph Theoretic Approach2010
- Author(s)
  Jaynarayan Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara
- Organizer
  2010 IEEE European Test Symposium
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Functional Fault Model for Micro Operation Faults of High Correlation with Stuck-At Faults2010
- Author(s)
  Chia Yee Ooi, Hideo Fujiwara
- Organizer
  11th IEEE Workshop on RTL and High Level Testing
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Enhancing False Path Identification from RTL for Reducing Design and Test Futileness2010
- Author(s)
  Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara
- Organizer
  The 5th IEEE International Symposium on Electronic Design, Test & Applications
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Secure and Testable Scan Design Using Extended de Bruijn Graphs2010
- Author(s)
  Hideo Fujiwara, Marie E.J.Obien
- Organizer
  15th Asia and South Pacific Design Automation Conference
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] SREEP-2 : SR-Equivalent Generator for Secure and Testable Scan Design2010
- Author(s)
  Katsuya Fujiwara, Hideo Fujiwara, Hideo Tamamoto
- Organizer
  11th IEEE Workshop on RTL and High Level Testing
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] RT-Level Design-for-Testability and Expansion of Functional Test Sequences for Enhanced Defect Coverage2010
- Author(s)
  Alodeep Sanyal, Krishnendu Chakrabarty, Mahmt Yilmaz, Hideo Fujiwara
- Organizer
  2010 IEEE International Test Conference
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Test Generation and DFT Based on Partial Thru Testability2009
- Author(s)
  Nobuya Oka, Chia Yee Ooi, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara
- Organizer
  2009 IEEE European Test Symposium, poster session
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] A Synthesis Method to Alleviate Over-testing of Delay Faults Based on RTL Don't Care Path Identification2009
- Author(s)
  Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara
- Organizer
  IEEE 27th VLSI Test Symposium
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] F-Scan : An Approach to Functional RTL Scan for Assignment Decision Diagrams2009
- Author(s)
  Marie Engelene J.Obien, Hideo Fujiwara
- Organizer
  Proc.IEEE 8th International Conference on ASIC
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] A Response Compactor for Extended Compatibility Scan Tree Construction2009
- Author(s)
  Zhiqiang You, Jiedi Huang, Michiko Inoue, Jishun Kuang, Hideo Fujiwara
- Organizer
  Proc. EEE 8th International Conference on ASIC
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Partial Scan Approach for Secret Information Protection2009
- Author(s)
  Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara
- Organizer
  2009 IEEE European Test Symposium
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Test Infrastructure Design for Core-Based System-on-Chip Under Cycle-Accurate Thermal Constraints2009
- Author(s)
  Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara
- Organizer
  14th Asia and South Pacific Design Automation Conference
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Fast False Path Identification Based on Functional Unsensitizability Using RTL Information2009
- Author(s)
  Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara
- Organizer
  14th Asia and South Pacific Design Automation Conference
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-Cycle Paths2008
- Author(s)
  Thomas Edison Yu, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara
- Organizer
  Proc. of IEEE the 17th Asian Test Symposium
- Data Source
  KAKENHI-PROJECT-20300018
[Presentation] Untestable Fault Identification in Sequential Circuits Using Model-Checking2008
- Author(s)
  Jaan Raik, Hideo Fujiwara, Raimund Ubar, Anna Krivenko
- Organizer
  Proc. of IEEE the 17th Asian Test Symposium
- Data Source
  KAKENHI-PROJECT-20300018

1. INOUE Michiko (30273840)

# of Collaborated Projects: 3 results

# of Collaborated Products: 23 results
2. OHTAKE Satoshi (20314528)

# of Collaborated Projects: 2 results

# of Collaborated Products: 20 results
3. YONEDA Tomokazu (20359871)

# of Collaborated Projects: 2 results

# of Collaborated Products: 16 results
4. INOUE Tomoo (40252829)

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
5. MASUZAWA Toshimitsu (50199692)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results

FUJIWARA Hideo 藤原 秀雄

Research Projects

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Co-Researchers

Basic Studies on Testability and Security for Network-on-ChipPrincipal Investigator

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BASIC STUDIES ON TEST ARCHITECTURE AND DESIGN FOR TESTABILITY FOR SYSTEM-ON-CHIPPrincipal Investigator

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BASIC STUDIES ON VLSISYNTHESIS FOR TESTABILITY FROM HIGHER LEVELPrincipal Investigator

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Studies on parallel processing of test generation for VLSI circuitsPrincipal Investigator

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Study on Neural Network for Test Generation of Large Scale Logic CircuitsPrincipal Investigator

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[Book] ディジタルシステムの設計とテスト2004

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[Journal Article] F-Scan : A DFT Method for Functional Scan at RTL2011

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Journal Title

NAID

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[Journal Article] セキュアスキャン設計のためのシフトレジスタ等価回路の列挙と合成2010

Author(s)

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NAID

Data Source

[Journal Article] A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint2010

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NAID

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[Journal Article] An Approach for Verification Assertions Reuse in RTL Test Pattern Generation2010

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[Journal Article] RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences2010

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[Journal Article] Design and Optimization of Transparency-Based TAM for SoC Test2010

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NAID

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[Journal Article] A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification2010

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NAID

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[Journal Article] A New Class of Easily Testable Assignment Decision Diagram2010

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Data Source

[Journal Article] セキュアスキャン設計のためのシフトレジスタ等価回路の列挙と合成2010

Author(s)

Journal Title

NAID

FUJIWARA Hideo 藤原秀雄