TOMABECHI Nobuhiro 苫米地宣裕

… Alternative Names

苫米地宣裕トマベチノブヒロ

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Researcher Number	70048180
Other IDs
External Links
Affiliation (based on the past Project Information) *help	2003 – 2004: 八戸工業大学, 工学部, 教授 1996 – 2001: 八戸工業大学, 工学部, 教授 1989 – 1990: 八戸工業大学, 工学部, 教授 1986: 八戸工大, 工学部, 教授
Review Section/Research Field	Principal Investigator Control engineering / 計測・制御工学 / Computer system/Network / 計測・制御工学 Except Principal Investigator 計測・制御工学
Keywords	Principal Investigator 構成法 / プロセッサ / 冗長2進数 / 高速 / RSA暗号 / WSI / 超高集積 / VLSI / ディジタル信号処理 / パルス列剰余数演算回路 … More / 剰余数系 / Gigabit / Pipeline / Table-look-up / Redundant binary number / Design / Processor / RSA cryptosystem / ギガビット / パイプライン / テーブルルックアップ / 冗長2進 / design / residue table / redundant binary number / Dprocessor / high-speed / RSA cryptsystem / 剰余テーブル / control / robot / yield enhancement / neuro-procossor / hierarchical redundancy design / 多次元サブシステム分割法 / 歩留り改善 / 多次元サブシステム分割 / ロボット制御 / 歩留まり改善 / ニューロプロセッサ / 階層冗長構成法 / DESIGN / OROCESSOR / CONTROL / ROBOT / HIGHLY INTEGRATED / REDUNDANCY / 歩留り / 制御 / ロボット / 冗長 / フォールトトレラント / LSI / 高信頼化 / フォ-ルトトレラント / 雑音 / 位相モ-ド多値論理回路 / 超高信頼 / 多相クロック … More Except Principal Investigator Residue Arithmetic VLSI / Current-Mode CMOS Integrated Circuit / Highly-Parallel Multiply Adder / Signed-Digit Arithmetic Circuit / Multiple-Valued Current-Mode Logic / Symmetric Residue Number System / 双方向電流モ-ドCMOS / 多値演算回路 / 高並列演算 / 剰余数演算回路 / VLSI / 剰余数演算VLSI / 電流モ-ドCMOS集積回路 / 高並列積和演算器 / SignedーDigit数演算回路 / 多値電流モ-ド論理 / 対称剰余数系 Less

Design of a Gigabit RSA encryption processor based on redundant binary arithmeticPrincipal Investigator
- Principal Investigator
  
  TOMABECHI Nobuhiro
- Project Period (FY)
  2003 – 2004
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system/Network
- Research Institution
  Hacinohe Institute of Technology
Design of a Super-ffigh'-Speed RSA Encryption Processor Based on the Residue Table for Redundant Binary NumbersPrincipal Investigator
- Principal Investigator
  
  TOMABECHI Nobuhiro
- Project Period (FY)
  2000 – 2001
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Control engineering
- Research Institution
  Hacbinohe Institute of Technology
Design of a Highly Integrated Neuro-Processor for Robot Control Based on the Hierarchical Redundancy Design MethodPrincipal Investigator
- Principal Investigator
  
  TOMABECHI Nobuhiro
- Project Period (FY)
  1998 – 1999
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Control engineering
- Research Institution
  Hachinohe Institute of Technology
DESIGN OF A HIGHLY ROBOT CONTROL PROCESSOR BY INTRODUCING REDUNDANCYPrincipal Investigator
- Principal Investigator
  
  TOMABECHI Nobuhiro
- Project Period (FY)
  1996 – 1997
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  計測・制御工学
- Research Institution
  HACHINOHE INSTITUTE OF TECHNOLOGY05AA : 08650505
多相クロック化剰余数演算回路に基づく超高信頼ディジタル信号処理システムPrincipal Investigator
- Principal Investigator
  
  苫米地宣裕
- Project Period (FY)
  1990
- Research Category
  
  Grant-in-Aid for General Scientific Research (C)
- Research Field
  
  計測・制御工学
- Research Institution
  Hachinohe Institute of Technology
Implementation of an Ultra-Higyly Parallel Residue Arithemtic Integrated Circuit Based on Multiple-Vlaued Logic and its Evaluation
- Principal Investigator
  
  KAMEYAMA Michitaka
- Project Period (FY)
  1989 – 1990
- Research Category
  
  Grant-in-Aid for Developmental Scientific Research (B).
- Research Field
  
  計測・制御工学
- Research Institution
  Tohoku University
パルス列剰余数演算回路に基づくVLSI向きディジタル信号処理システムの高信頼化Principal Investigator
- Principal Investigator
  
  苫米地宣裕
- Project Period (FY)
  1986
- Research Category
  
  Grant-in-Aid for General Scientific Research (C)
- Research Field
  
  計測・制御工学
- Research Institution
  Hachinohe Institute of Technology

All 2005 2004 2003 2002

All Journal Article

[Journal Article] 剰余テーブルを循環する高速RSA暗号プロセッサのパイプラインアーキテクチャ2005
- Author(s)
  苫米地宣裕
- Journal Title
  
  八戸工業大学紀要 24
  
  Pages: 117-121
- NAID
  110003483489
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-15500050
[Journal Article] Pipelined architecture of high-speed RSA encryption processor using redundant binary arithmetic and table-look-up2004
- Author(s)
  Nobuhiro Tomabechi
- Journal Title
  
  Proc.of 2004 IEEE International Conference on Electrical and Computer Engineering 3
  
  Pages: 593-596
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-15500050
[Journal Article] Reconfigurable architecture of the high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers2004
- Author(s)
  Nobuhiro Tomabechi
- Journal Title
  
  Proc.of 2004 IEEE International Conference on High Performance Computing 11
  
  Pages: 1-5
- Data Source
  KAKENHI-PROJECT-15500050
[Journal Article] Reconfigurable architecture of the high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers2004
- Author(s)
  Nobuhiro Tomabechi
- Journal Title
  
  Web Proc.of 2004 IEEE International Conference on High Performance Computing 11
  
  Pages: 1-5
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-15500050
[Journal Article] Reconfigurable architecture of the high-speed RSA Encryption processor with built-in table for residue calculation of Redundant binary numbers.2004
- Author(s)
  N.Tomabechi
- Journal Title
  
  Web Proc.Of 2004 IEEE Int.Conf.On High Performance Computing Vol.11
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15500050
[Journal Article] ギガビットネットワークを用いた動画像伝送遅延時間の評価2003
- Author(s)
  藤岡与周, 苫米地宣裕
- Journal Title
  
  八戸工業大学異分野融合科学研究所 1
  
  Pages: 121-128
- NAID
  120005892101
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-15500050
[Journal Article] Design of a parallel VLSI processor for tele-robot systems based on dynamic reconfiguration of power supply voltages2003
- Author(s)
  Y.Fujioka, N.Tomabechi, M.Kameyama
- Journal Title
  
  Proc.of SICE 2003 Annual Conference
  
  Pages: 2638-2643
- NAID
  130005440950
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-15500050
[Journal Article] Design of a parallel VLSI Processor for telr-robot systems based on dynamic reconfiguration of Power supply voltages.2003
- Author(s)
  Y.Fujioka, N.Tomabechi, M.Kameyama
- Journal Title
  
  Proc.Of SICE 2003 Annual Conf.
  
  Pages: 2638-2643
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15500050
[Journal Article] An evaluation of the delay time for video image transfer via Japan Gigabit Network.2003
- Author(s)
  Y.Fujioka, N.Tomabechi
- Journal Title
  
  Bulletin of Research Institute for Interdisciplinary Science Hachnohe Institute of Technology Vol.1
  
  Pages: 121-128
- NAID
  120005892101
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15500050
[Journal Article] Pipelined design of the high-speed RSA encryption Processor with built-in table for residue calculation of redundant Binary numbers.2002
- Author(s)
  N.Tomabechi, T.Ito
- Journal Title
  
  Proc.of 2002 IEEE Region 10 Conf.On Computer, Communication, Control and Power Engineering
  
  Pages: 412-415
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15500050
[Journal Article] Pipelined design of the high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers2002
- Author(s)
  N.Tomabechi, T.Ito
- Journal Title
  
  Proc.of 2002 IEEE Region 10 Conf.on Computer, Communication, Control and Power Engineering
  
  Pages: 412-415
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-15500050

1. KAMEYAMA Michitaka (70124568)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
2. FUJIOKA Yoshichika (70275527)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results

TOMABECHI Nobuhiro 苫米地 宣裕

苫米地 宣裕 トマベチ ノブヒロ

Research Projects

Research Products

Co-Researchers

Design of a Gigabit RSA encryption processor based on redundant binary arithmeticPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Design of a Super-ffigh'-Speed RSA Encryption Processor Based on the Residue Table for Redundant Binary NumbersPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Design of a Highly Integrated Neuro-Processor for Robot Control Based on the Hierarchical Redundancy Design MethodPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

DESIGN OF A HIGHLY ROBOT CONTROL PROCESSOR BY INTRODUCING REDUNDANCYPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

多相クロック化剰余数演算回路に基づく超高信頼ディジタル信号処理システムPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Implementation of an Ultra-Higyly Parallel Residue Arithemtic Integrated Circuit Based on Multiple-Vlaued Logic and its Evaluation

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

パルス列剰余数演算回路に基づくVLSI向きディジタル信号処理システムの高信頼化Principal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

[Journal Article] 剰余テーブルを循環する高速RSA暗号プロセッサのパイプラインアーキテクチャ2005

Author(s)

Journal Title

NAID

Description

Data Source

[Journal Article] Pipelined architecture of high-speed RSA encryption processor using redundant binary arithmetic and table-look-up2004

Author(s)

Journal Title

Description

Data Source

[Journal Article] Reconfigurable architecture of the high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers2004

Author(s)

Journal Title

Data Source

[Journal Article] Reconfigurable architecture of the high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers2004

Author(s)

Journal Title

Description

Data Source

[Journal Article] Reconfigurable architecture of the high-speed RSA Encryption processor with built-in table for residue calculation of Redundant binary numbers.2004

Author(s)

Journal Title

Description

Data Source

[Journal Article] ギガビットネットワークを用いた動画像伝送遅延時間の評価2003

Author(s)

Journal Title

NAID

Description

Data Source

[Journal Article] Design of a parallel VLSI processor for tele-robot systems based on dynamic reconfiguration of power supply voltages2003

Author(s)

TOMABECHI Nobuhiro 苫米地宣裕

苫米地宣裕トマベチノブヒロ