SHI Youhua 史又華

Researcher Number	70409655
Other IDs
External Links
Affiliation (Current)	2025: 早稲田大学, 理工学術院, 教授
Affiliation (based on the past Project Information) *help	2018 – 2020: 早稲田大学, 理工学術院, 教授 2015 – 2016: 早稲田大学, 理工学術院, 准教授 2012 – 2014: 早稲田大学, 高等研究所, 准教授 2011: 早稲田大学, 理工学術院, 助教 2008 – 2009: Waseda University, IT研究機構, 講師 2007: Waseda University, 理工学術院, 助手
Review Section/Research Field	Principal Investigator Computer system/Network / Basic Section 60040:Computer system-related / Computer system Except Principal Investigator Electron device/Electronic equipment
Keywords	Principal Investigator ディペンダブルコンピューティング / LSI設計 / 自立電源 / 圧電素子 / エネルギーハーベスティング回路 / 自電源回路 / 低周波 / 広帯域 / 高効率インターフェース回路 / 振動発電 … More / 広帯域化 / 自己駆動型スイッチング制御回路 / インターフェース回路 / Energy harvesting / Energy Harvesting / 低消費エネルギー / ばらつき耐性 / LSI設計技術 / タイミングエラー / 信頼化設計 / ソフトエラー / 製造ばらつき / 高信頼化 / VLSI 設計技術とCAD / VLSI設計技術とCAD / 遅延解析 / 低消費電力化 / 高信頼設計 / 低消費電力設計 / 過剰テスト / 合成システム / タイミング解析 / テストアーキテクチャ / テスト設計 / システムLSIテスト / フォールスパス解析 / 設計自動化システム / 回路設計・CAD / VLSI設計技術 / 回路とシステム / 設計自動化 … More Except Principal Investigator SD-SFF / スキャンベース攻撃 / 暗号処理LSI / スキャンチェイン / テスト容易化設計 / LSI設計 Less

Efficient self-powered energy harvesting circuit designsPrincipal Investigator
- Principal Investigator
  
  SHI Youhua
- Project Period (FY)
  2018 – 2020
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Waseda University
Timing Error Prediction for Variation-Resilient LSI DesignsPrincipal Investigator
- Principal Investigator
  
  SHI YOUHUA
- Project Period (FY)
  2014 – 2016
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system
- Research Institution
  Waseda University
Research on delay test techniques for ultra-low power designsPrincipal Investigator
- Principal Investigator
  
  SHI YOUHUA
- Project Period (FY)
  2011 – 2013
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Waseda University
Design Methods for Crypto LSI Implementations and Testing
- Principal Investigator
  
  YANAGISAWA Masao
- Project Period (FY)
  2009 – 2011
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  Waseda University
Automatic False Path Identification and Test Synthesis System Development to Avoid OvertestingPrincipal Investigator
- Principal Investigator
  
  SHI Youhua
- Project Period (FY)
  2007 – 2009
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Waseda University

All 2019 2018 2017 2016 2015 2014 2013 2012 2010 2009 2008 2007

All Journal Article Presentation Patent

[Journal Article] Timing monitoring paths selection for wide voltage IC2016
- Author(s)
  Weiwei Shan, Wentao Dai, Youhua Shi, Peng Cao, and Xiaoyan Xiang
- Journal Title
  
  IEICE Electron. Express
  
  Volume: 13 Issue: 8 Pages: 20160095-20160095
- DOI
  10.1587/elex.13.20160095
- NAID
  130005147724
- ISSN
  1349-2543
- Language
  English
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26330073
[Journal Article] An Effective Suspicious Timing-Error Prediction Circuit Insertion Algorithm Minimizing Area Overhead2015
- Author(s)
  Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa and Nozomu Togawa
- Journal Title
  
  IEICE Trans. Fundamentals
  
  Volume: E98.A Issue: 7 Pages: 1406-1418
- DOI
  10.1587/transfun.E98.A.1406
- NAID
  130005085793
- ISSN
  0916-8508, 1745-1337
- Language
  English
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-26330073
[Journal Article] Floorplan Driven Architecture and High-level Synthesis Algorithm for Dynamic Multiple Supply Voltages2013
- Author(s)
  Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, and Nozomu Togawa
- Journal Title
  
  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
  
  Volume: vol.E96-A, no.12 Pages: 2597-2611
- NAID
  130003385313
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23700065
[Journal Article] Rubust Secure Scan Design against Scan-Based Differential Cryptanalysis2012
- Author(s)
  Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
- Journal Title
  
  IEEE Trans.on Very Large Scale Integration (VLSI) Systems
  
  Volume: 20 Issue: 3 Pages: 176-181
- DOI
  10.1109/tvlsi.2012.2187408
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21560370
[Journal Article] MH<sup>4</sup> : multiple-supply-voltages aware high-level synthesis for high-integrated and high-frequency circuits for HDR architectures2012
- Author(s)
  Shin-ya Abe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
- Journal Title
  
  IEICE Electron. Express
  
  Volume: 9 Issue: 17 Pages: 1414-1422
- DOI
  10.1587/elex.9.1414
- NAID
  130001921526
- ISSN
  1349-2543
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23700065
[Journal Article] Robust Secure Scan Design against Scan-based Differential Cryptanalysis2012
- Author(s)
  Y. Shi
- Journal Title
  
  IEEE Transactions on Very Large Scale Integration Systems (TVLSI)
  
  Volume: 20 Issue: 1 Pages: 176-181
- DOI
  10.1109/tvlsi.2011.2120635
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23700065
[Journal Article] Rubust Secure Scan Design against Scan-Based Differential Cryptanalysis2012
- Author(s)
  Youhua Shi, Nozomu Togawa, Masao Yanagisawa, and Tatsuo Ohtsuki
- Journal Title
  
  IEEE Trans. on Very Large Scale Integration(VLSI) Systems
  
  Volume: vol.20, no.1 Pages: 176-181
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21560370
[Journal Article] X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction2009
- Author(s)
  Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
- Journal Title
  
  IEICE Trans. on Fundamentals of Electronics Communications and Computer Science Vol.E92-A, No.12
  
  Pages: 3119-3127
- NAID
  10026861520
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19700045
[Journal Article] X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction2009
- Author(s)
  Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
- Journal Title
  
  IEICE Trans. on Fundamentals of Electronics Communications and Computer Science Vol.E92-A,No.12
  
  Pages: 3119-3127
- NAID
  10026861520
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19700045
[Journal Article] A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss2008
- Author(s)
  Youhua Shi, Nozomu Togawa, Masao Yanagisawa, and Tatsuo Ohtsuki
- Journal Title
  
  IEICE Trans. on Fundamentals of Elebtronics Communications and Computer Science Vol E91-A, No.12
  
  Pages: 3514-3523
- NAID
  10026853923
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19700045
[Journal Article] A Secure Test Technique for Pipelined Advanced Encryption Standard2008
- Author(s)
  Y. Shi, N. Togawa, N. Yanagisawa and T. Ohtsuki
- Journal Title
  
  IEICE Transactions on Fundamentals of Electronics Communications and Computer Science E91-D, 3
  
  Pages: 776-780
- NAID
  10026802210
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19700045
[Journal Article] A Secure Test Technique for Pipelined Advanced Encryption Standard2008
- Author(s)
  Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
- Journal Title
  
  IEICE Trans. on Fundamentals of Electronics Communications and Computer Science Vol.E91-D,No.3
  
  Pages: 776-780
- NAID
  10026802210
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19700045
[Journal Article] A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss2008
- Author(s)
  Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
- Journal Title
  
  IEICE Trans. on Fundamentals of Electronics Communications and Computer Science Vol.E91-A,No.12
  
  Pages: 3514-3523
- NAID
  10026853923
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19700045
[Patent] 信号処理装置および信号処理方法2014
- Inventor(s)
  史又華、戸川望、柳澤政生、五十嵐博昭
- Industrial Property Rights Holder
  学校法人早稲田大学
- Industrial Property Rights Type
  特許
- Filing Date
  2014-02-18
- Overseas
- Data Source
  KAKENHI-PROJECT-23700065
[Patent] 信号処理装置および信号処理方法2014
- Inventor(s)
  史又華, 戸川望, 柳澤政生，五十嵐博昭
- Industrial Property Rights Holder
  史又華, 戸川望, 柳澤政生，五十嵐博昭
- Industrial Property Rights Type
  特許
- Filing Date
  2014-02-18
- Data Source
  KAKENHI-PROJECT-23700065
[Patent] 信号処理装置および信号処理方法2013
- Inventor(s)
  史又華、戸川望、柳澤政生、五十嵐博昭
- Industrial Property Rights Holder
  学校法人早稲田大学
- Industrial Property Rights Type
  特許
- Industrial Property Number
  2013-037620
- Filing Date
  2013-02-27
- Data Source
  KAKENHI-PROJECT-23700065
[Presentation] Static Error Analysis and Optimization of Faithfully Truncated Adders for Area-Power Efficient FIR Designs2019
- Author(s)
  J. Ye, N. Togawa, M. Yanagisawa and Y. Shi
- Organizer
  IEEE International Symposium on Circuits and Systems (ISCAS)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11227
[Presentation] 低周波圧電エネルギーハーベスティングにおけるMOSs SP-SSHI手法2018
- Author(s)
  杉山貴紀, 戸川望, 柳澤政生, 史又華
- Organizer
  電子情報通信学会第31回回路とシステムワークショップ
- Data Source
  KAKENHI-PROJECT-18K11227
[Presentation] 最大エラー距離に基づくGeAr回路の最適化2017
- Author(s)
  早水謙, 戸川望, 柳澤政生, 史又華
- Organizer
  回路とシステムワークショップ
- Place of Presentation
  北九州国際会議場
- Year and Date
  2017-05-11
- Data Source
  KAKENHI-PROJECT-26330073
[Presentation] C-element を用いたソフトエラー耐性をもつSHCラッチの設計2017
- Author(s)
  田島咲季, 史又華, 戸川望, 柳澤政生
- Organizer
  回路とシステムワークショップ
- Place of Presentation
  北九州国際会議場
- Year and Date
  2017-05-12
- Data Source
  KAKENHI-PROJECT-26330073
[Presentation] 内部ノードを利用したソフトエラー検出ラッチの設計2017
- Author(s)
  中垣直道, 戸川望, 柳澤政生, 史又華
- Organizer
  回路とシステムワークショップ
- Place of Presentation
  北九州国際会議場
- Year and Date
  2017-05-12
- Data Source
  KAKENHI-PROJECT-26330073
[Presentation] 高速かつ低電力なソフトエラー耐性をもつFast-SEHラッチの設計2016
- Author(s)
  田島咲季, 史又華, 戸川望, 柳澤政生
- Organizer
  回路とシステムワークショップ
- Place of Presentation
  北九州国際会議場
- Year and Date
  2016-05-12
- Data Source
  KAKENHI-PROJECT-26330073
[Presentation] 15nmプロセスにおける低電力な耐ソフトエラーラッチの設計2015
- Author(s)
  田島咲季, 史又華, 戸川望, 柳澤政生
- Organizer
  デザインガイア2015
- Place of Presentation
  長崎県勤労福祉会館
- Year and Date
  2015-12-02
- Data Source
  KAKENHI-PROJECT-26330073
[Presentation] An effective robust design using improved monitoring-path selection algorithm for suspicious timing error prediction2015
- Author(s)
  Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, and Nozomu Togawa
- Organizer
  IEEE International Conference on ASIC (ASICON)
- Place of Presentation
  Chengdu, China
- Year and Date
  2015-11-05
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26330073
[Presentation] A low-power soft error tolerant latch scheme2015
- Author(s)
  Saki Tajima, Youhua Shi, Nozomu Togawa, and Masao Yanagisawa
- Organizer
  IEEE International Conference on ASIC (ASICON)
- Place of Presentation
  Chengdu, China
- Year and Date
  2015-11-04
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26330073
[Presentation] A universal delay line circuit for variation resilient IC with self-calibrated time-to-digital converter2015
- Author(s)
  Shuai Shao, Youhua Shi, Wentao Dai, Jianyi Meng and Weiwei Shan
- Organizer
  IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC)
- Place of Presentation
  Singapore
- Year and Date
  2015-06-02
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26330073
[Presentation] 低電力耐ソフトエラーラッチの設計2015
- Author(s)
  田島咲季, 史又華, 戸川望, 柳澤政生
- Organizer
  VLD研究会
- Place of Presentation
  沖縄県青年会館
- Year and Date
  2015-03-03
- Data Source
  KAKENHI-PROJECT-26330073
[Presentation] DTMOSを用いたサブスレッショルド回路の高速化設計2014
- Author(s)
  福留祐治, 史又華, 戸川望, 宇佐美公良, 柳澤政生
- Organizer
  デザインガイア
- Place of Presentation
  ビーコンプラザ（別府国際コンベンションセンター）
- Year and Date
  2014-11-26
- Data Source
  KAKENHI-PROJECT-26330073
[Presentation] InTimeTune: A Throughput Driven Timing Speculation Architecture for Overscaled Designs2014
- Author(s)
  Youhua Shi, Hiroaki Igarashi, Nozomu Togawa, and Masao Yanagisawa
- Organizer
  ACM/EDAC/IEEE Design Automation Conference，Work-in-process session
- Place of Presentation
  San Francisco, CA, USA
- Year and Date
  2014-06-04
- Data Source
  KAKENHI-PROJECT-26330073
[Presentation] In-situ Timing Monitoring Methods for Variation-Resilient Designs2014
- Author(s)
  Youhua Shi and Nozomu Togawa
- Organizer
  IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
- Place of Presentation
  Ishigaki, Okinawa, Japan
- Year and Date
  2014-11-20
- Invited
- Data Source
  KAKENHI-PROJECT-26330073
[Presentation] サブスレッショルド回路における遅延・エネルギーの温度依存性に関する実験および考察2014
- Author(s)
  櫛田浩樹, 史又華, 戸川望, 宇佐美公良, 柳澤政生
- Organizer
  電子情報通信学会　VLSI設計技術研究会
- Place of Presentation
  沖縄県青年会館 (沖縄県那覇市)
- Data Source
  KAKENHI-PROJECT-23700065
[Presentation] InTimeTune: A Throughput Driven Timing Speculation Architecture for Overscaled Designs2014
- Author(s)
  Youhua Shi, Hiroaki Igarashi, Nozomu Togawa, and Masao Yanagisawa
- Organizer
  ACM/EDAC/IEEE Design Automation Conference
- Place of Presentation
  San Francisco, USA
- Data Source
  KAKENHI-PROJECT-23700065
[Presentation] InTimeTune : A Throughput Driven Timing Speculation Architecture for Overscaled Designs2014
- Author(s)
  Youhua Shi, Hiroaki Igarashi, Nozomu Togawa, and Masao Yanagisawa
- Organizer
  ACM/EDAC/IEEE Design Automation Conference
- Place of Presentation
  San Francisco, USA.(Work-in-process session (Poster))
- Data Source
  KAKENHI-PROJECT-23700065
[Presentation] Throughput Driven Check Point Selection in Suspicious Timing Error Prediction based Designs2014
- Author(s)
  Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, and Nozomu Togawa
- Organizer
  IEEE Latin American Symposium on Circuits and Systems
- Place of Presentation
  Santiago, Chile
- Data Source
  KAKENHI-PROJECT-23700065
[Presentation] Throughput Driven Check Point Selection in Suspicious Timing Error Prediction based Designs2014
- Author(s)
  Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, and Nozomu Togawa
- Organizer
  Proc. IEEE Latin American Symposium on Circuits and Systems (LASCAS)
- Place of Presentation
  Santiago, Chile
- Data Source
  KAKENHI-PROJECT-23700065
[Presentation] An Area-Overhead-Oriented Monitoring-Path Selection Algorithm for Suspicious Timing Error Prediction2014
- Author(s)
  Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
- Organizer
  IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
- Place of Presentation
  Ishigaki, Okinawa, Japan
- Year and Date
  2014-11-19
- Data Source
  KAKENHI-PROJECT-26330073
[Presentation] タイミングエラーへの耐性を持つフリップフロップ設計2014
- Author(s)
  鈴木大渡, 史又華, 戸川望, 宇佐美公良, 柳澤政生
- Organizer
  デザインガイア
- Place of Presentation
  ビーコンプラザ（別府国際コンベンションセンター）
- Year and Date
  2014-11-26
- Data Source
  KAKENHI-PROJECT-26330073
[Presentation] サブスレッショルド回路における遅延・エネルギーの温度依存性に関する実験および考察2014
- Author(s)
  櫛田浩樹, 史又華, 戸川望, 宇佐美公良, 柳澤政生
- Organizer
  信学技報
- Place of Presentation
  沖縄県青年会館
- Data Source
  KAKENHI-PROJECT-23700065
[Presentation] Floorplan Driven architectures and High-level Synthesis algorithm for Dynamic Multiple Supply voltages2013
- Author(s)
  Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, and Nozomu Togawa
- Organizer
  Work-in-process (Poster: #61.68), Design Automation Conference
- Place of Presentation
  Austin, USA
- Data Source
  KAKENHI-PROJECT-23700065
[Presentation] An Energy-efficient High-level Synthesis Algorithm Incorporating Interconnection Delays and Dynamic Multiple Supply Voltages2013
- Author(s)
  Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, and Nozomu Togawa
- Organizer
  Proc. IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)
- Place of Presentation
  Hsinchu, Taiwan(pp.54-57)
- Data Source
  KAKENHI-PROJECT-23700065
[Presentation] Suspicious Timing Error Detection and Recovery with In-Cycle Clock Gating2013
- Author(s)
  Youhua Shi, Hiroaki Igarashi, Masao Yanagisawa, and Nozomu Togawa
- Organizer
  Proc. IEEE International Symposium on Quality Electronic Design (ISQED)
- Place of Presentation
  Santa Clara(pp.335-340)
- Data Source
  KAKENHI-PROJECT-23700065
[Presentation] チェックポイント観測によるタイミングエラー予測手法2013
- Author(s)
  五十嵐博昭,史又華,柳澤政生,戸川望
- Organizer
  電子情報通信学会デザインガイア
- Place of Presentation
  鹿児島県文化センター(vol. 113, No.320, pp.39-44)
- Data Source
  KAKENHI-PROJECT-23700065
[Presentation] An Energy-efficient High-level Synthesis Algorithm Incorporating Interconnection Delays and Dynamic Multiple Supply Voltages2013
- Author(s)
  Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, and Nozomu Togawa
- Organizer
  IEEE International Symposium on VLSI Design, Automation and Test
- Place of Presentation
  Hsinchu, Taiwan
- Data Source
  KAKENHI-PROJECT-23700065
[Presentation] Suspicious Timing Error Detection and Recovery with In-Cycle Clock Gating2013
- Author(s)
  Youhua Shi, Hiroaki Igarashi, Masao Yanagisawa, and Nozomu Togawa
- Organizer
  IEEE International Symposium on Quality Electronic Design (ISQED)
- Place of Presentation
  Santa Clara, USA
- Data Source
  KAKENHI-PROJECT-23700065
[Presentation] Floorplan Driven Architectures and High-level Synthesis Algorithm for Dynamic Multiple Supply Voltages2013
- Author(s)
  Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, and Nozomu Togawa
- Organizer
  ACM/EDAC/IEEE Design Automation Conference
- Place of Presentation
  Austin, USA
- Data Source
  KAKENHI-PROJECT-23700065
[Presentation] Predication based Timing Speculation Technique for Throughput Improvement2013
- Author(s)
  Youhua Shi, Hiroaki Igarashi, Masao Yanagisawa, and Nozomu Togawa
- Organizer
  Proc. International Conference on Integrated Circuits, Design, and Verification (ICDV)
- Place of Presentation
  Ho Chi Minh City, Vietnam(Invited Talk)
- Data Source
  KAKENHI-PROJECT-23700065
[Presentation] チェックポイント観測によるタイミングエラー予測手法2013
- Author(s)
  五十嵐博昭，史又華，柳澤政生，戸川望
- Organizer
  電子情報通信学会デザインガイア
- Place of Presentation
  鹿児島県文化センター (鹿児島県鹿児島市)
- Data Source
  KAKENHI-PROJECT-23700065
[Presentation] Predication based Timing Speculation Technique for Throughput Improvement2013
- Author(s)
  Youhua Shi, Hiroaki Igarashi, Masao Yanagisawa, and Nozomu Togawa
- Organizer
  International Conference on Integrated Circuits, Design, and Verification
- Place of Presentation
  Ho Chi Minh City, Vietnam
- Invited
- Data Source
  KAKENHI-PROJECT-23700065
[Presentation] State-dependent changeable scan architecture against scan-based side channel attacks2010
- Author(s)
  R.Nara, H.Atobe, Y.Shi, N.Togawa, M.Yanagisawa, T.Ohtsuki
- Organizer
  IEEE ISCAS 2010
- Place of Presentation
  Paris, France
- Year and Date
  2010-05-30
- Data Source
  KAKENHI-PROJECT-21560370
[Presentation] Constant-scan-based attack and its countermeasure for crypto hardware implementations2010
- Author(s)
  Y.Shi, N.Togawa, M.Yanagisawa, T.Ohtsuki
- Organizer
  情報処理学会DAシンポジウム2010
- Place of Presentation
  豊橋
- Year and Date
  2010-09-02
- Data Source
  KAKENHI-PROJECT-21560370
[Presentation] State-dependent Changeable Scan Architecture against Scan-based Side Channel Attacks2010
- Author(s)
  Ryuta Nara, Hiroshi Atobe, Youhua Shi, Nozomu Togawa, Masao Yanagisawa and Tatsuo Ohtsuki
- Organizer
  IEEE ISCAS 2010
- Place of Presentation
  Paris, France
- Year and Date
  2010-05-06
- Data Source
  KAKENHI-PROJECT-21560370
[Presentation] Constant-scan-based attack and its countermeasure for crypto hardware implementations2010
- Author(s)
  Youhua Shi, Nozomu Togawa, Masao Yanagisawa and Tatsuo Ohtsuki
- Organizer
  情報処理学会DAシンポジウム2010
- Place of Presentation
  愛知県豊橋市
- Data Source
  KAKENHI-PROJECT-21560370
[Presentation] Design-for-Secure- Test for Crypto Cores2009
- Author(s)
  Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
- Organizer
  IEEE International Test Conference
- Place of Presentation
  Austin, USA
- Year and Date
  2009-11-03
- Data Source
  KAKENHI-PROJECT-19700045
[Presentation] Handling More X's Using Current X-Tolerant Compactors with Maximal Compaction2009
- Author(s)
  Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
- Organizer
  IEEE European Test Symposium (ETS)
- Place of Presentation
  Sevilla, SPAIN
- Data Source
  KAKENHI-PROJECT-19700045
[Presentation] Design-for-Secure- Test for Crypto Cores2009
- Author(s)
  Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
- Organizer
  Proc. of IEEE International Test Conference (ITC)
- Place of Presentation
  Austin, USA
- Data Source
  KAKENHI-PROJECT-19700045
[Presentation] Handling More X' s Using Current X-Tolerant Cqnpactors with Maximal Compaction2009
- Author(s)
  Youhua Shi, Nozomu Togawa, Nasao Yanagisawa, Tatsuo Ohtsuki
- Organizer
  IEEE European Test Symposium
- Place of Presentation
  Sevilla, Spain
- Year and Date
  2009-05-28
- Data Source
  KAKENHI-PROJECT-19700045
[Presentation] X-Eliminator : A Technique to Mask All Unknown Responses with No Test Loss and Minimized Masking Data O verhead2008
- Author(s)
  Youhua Shi, Nozomu Togawa, Masao Yanagisawa, and Tatsuo Ohtsuki
- Organizer
  IFIP/IEEE International Conference on Very Large Scale Integration
- Place of Presentation
  Rhodes, Greece
- Year and Date
  2008-10-15
- Data Source
  KAKENHI-PROJECT-19700045
[Presentation] X-Eliminator: A Technique to Mask All Unknown Responses with No Test Loss and Minimized Masking Data Overhead2008
- Author(s)
  Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
- Organizer
  Proc. of 16th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC)
- Place of Presentation
  Rhodes Island, Greece
- Data Source
  KAKENHI-PROJECT-19700045
[Presentation] GECOM: Test Data Compression Combined with All Unknown Response Masking2008
- Author(s)
  Y. Shi, N. Togawa, M. Yanagisawa and T. Ohtsuki
- Organizer
  IEEE Asia and South Pacific Design Automation Conference
- Place of Presentation
  Seoul, Korea
- Year and Date
  2008-01-24
- Data Source
  KAKENHI-PROJECT-19700045
[Presentation] GECOM: Test Data Compression Combined with All Unknown Response Masking2008
- Author(s)
  Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
- Organizer
  Proc. of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC)
- Place of Presentation
  Seoul, Korea
- Data Source
  KAKENHI-PROJECT-19700045
[Presentation] Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard2007
- Author(s)
  Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
- Organizer
  Proc. of IEEE International Symposium on Circuits and Systems (ISCAS)
- Place of Presentation
  New Orleans, USA
- Data Source
  KAKENHI-PROJECT-19700045
[Presentation] CoDaMa: An XML-based Framework to Manipulate Control Data Flow Graphs2007
- Author(s)
  S. Kohara, Y. Shi, N. Togawa, M. Yanagisawa and T. Ohtsuki
- Organizer
  Workshop on Synthesis and System Integration of Mixed Information technologies
- Place of Presentation
  Hokkaido, Japan
- Year and Date
  2007-10-16
- Data Source
  KAKENHI-PROJECT-19700045

1. YANAGISAWA Masao (30170781)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
2. NARA Ryuta (30547047)

# of Collaborated Projects: 1 results

# of Collaborated Products: 2 results
3. 佐藤政生

# of Collaborated Projects: 0 results

# of Collaborated Products: 6 results

SHI Youhua 史 又華

Research Projects

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Co-Researchers

Efficient self-powered energy harvesting circuit designsPrincipal Investigator

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Timing Error Prediction for Variation-Resilient LSI DesignsPrincipal Investigator

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Research on delay test techniques for ultra-low power designsPrincipal Investigator

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Design Methods for Crypto LSI Implementations and Testing

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Automatic False Path Identification and Test Synthesis System Development to Avoid OvertestingPrincipal Investigator

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[Journal Article] Timing monitoring paths selection for wide voltage IC2016

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[Journal Article] An Effective Suspicious Timing-Error Prediction Circuit Insertion Algorithm Minimizing Area Overhead2015

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[Journal Article] Floorplan Driven Architecture and High-level Synthesis Algorithm for Dynamic Multiple Supply Voltages2013

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[Journal Article] Rubust Secure Scan Design against Scan-Based Differential Cryptanalysis2012

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[Journal Article] MH<sup>4</sup> : multiple-supply-voltages aware high-level synthesis for high-integrated and high-frequency circuits for HDR architectures2012

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[Journal Article] Robust Secure Scan Design against Scan-based Differential Cryptanalysis2012

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[Journal Article] Rubust Secure Scan Design against Scan-Based Differential Cryptanalysis2012

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[Journal Article] X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction2009

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SHI Youhua 史又華