NANYA Takashi 南谷崇

Researcher Number	80143684
Other IDs
External Links
Affiliation (based on the past Project Information) *help	1996 – 2009: The University of Tokyo, Research Center for Advanced Science and Technology, Professor, 先端科学技術研究センター, 教授 1995: Tokyo Institute of Technology, Graduate School of information Science and Engineering, Professor, 大学院・情報理工学研究科, 教授 1994: 東京工業大学, 大学院情報理工学研究科, 教授 1989 – 1993: 東京工業大学, 工学部, 教授 1988: 東京工業大学, 工学部, 助教授
Review Section/Research Field	Principal Investigator 計算機科学 / 情報工学 / Computer system/Network / Science and Engineering / 計算機工学 Except Principal Investigator 計算機科学 / Computer system/Network / Science and Engineering
Keywords	Principal Investigator AINOS / CAD / SDIモデル / 非同期式回路 / Verilog RTL / SDI Model / ダブルバッファDDL / 非同期式ライブラリ / 事象駆動原理 / 設計支援CADシステム … More / メモリアーキテクチャ / 非同期式システム / Asynchronous Circuit Testing / Asynchronous Circuit / Asynchronous Processor / 非同期式回路テスト / VLSIシステム設計 / 非同期式VLSIシステム / 非同期式プロセッサ / 論理設計 / アーキテクチャ / マイクロプロセッサ / 論理回路 / セルフチェッキング / 1-out-of-4 Coding / Asynchronous System / Delay Variation / Low Power Consumption / Task Scheduling / Multi-Processor SoC / Hetero-Timing VLSI / ディペンダブルシステム / 情報システム / VLSIシステム / ヘテロタイミング / 1-out-of-4符号 / 遅延変動 / 低消費電力 / タスクスケジューリング / マルチプロセッサSoC / ヘテロタイミングVLSI / DI Interface / SDl model / Locally timed VLSI / STG / 同期・非同期融合型VLSIシステム / 暗号化回路 / 2線2相式データ転送 / DIインタフェース / 非同期式制御回路 / 同期・非同期融合型VLSI / Compile Technique / Memory system / Asynchronous system / Cascade ALU / Computer Architecture / 自己タイミング制御方式 / データフローアーキテクチャ / 多重並列演算方式 / 非同期式パイプライン / コンパイラ / SCIMA / カスケードALUアーキテクチャ / コンパイル技術 / メモリシステム / 設計支援CAD / カスケードALU / 計算機アーキテクチャ / Asynchronous Logic Design / VLSI system design / Asynchronous VLSI system / Asynchronous Circuits / VLSI設計 / 非同期式論理設計 / Asynchronous Logic Synthesis / ALSI System Design / Asynchronous VLSI System / 非同期式論理合成 / VLSI Design Education / Full custom LSI / Gate arrays / Multi-project chip / VLSI chip implementation service / VLSI設計教育 / フルカスタムLSI / ゲートアレイ / マルチプロジェクトチップ / VLSIチップ試作サービス / dependency graph / transition causality / delay models / two-rail two-phase / logic design / architecture / microprocessor / asynchronous circuits / 出力純粋遅延モデル / 依存性グラフ / 遷移因果律 / 遅延モデル / 2線2相式 / Logic Synthesis / Logic Circuits / Processor Organization / Self-checking / Fault-tolerance / 論理式除算 / 論理合成 / プロセッサ方式 / フォ-ルトトレランス / テスト容易化設計 / VLSIテスト / ディペンダブル VLSI / ディペンダブルVLSI / 半導体超微細化 / 計算機システム … More Except Principal Investigator Memory Hierarchy / Processor Architecture / メモリ階層 / プロセッサアーキテクチャ / クラスタシステム / Register / Static Power / Dynamic Power / Compiler / Low Power Consumption / Software Controlled Memory / 計算機アークテクチャ / キャッシュメモリ / コンパイル技術 / マイクロプロセッサ / メモリシステム / 計算機アーキテクチャ / 静的消費電力 / 動的消費電力 / レジスタファイル / 温度依存最適化 / リーク電流 / スタティック消費エネルギー / ダイナミック消費エネルギー / 低消費電力プロセッサ / レジスタ / スタティック消費電力 / ダイナミック消費電力 / コンパイラ / 低消費電力 / ソフトウェア可制御メモリ / System on a Chip / Real-Time Processing System / Intelligent Electronic System / Image Information Processing / シリコン集積回路 / システムオンチッ / 電子デバイス・機器 / 超高速情報処理 / 知的情報処理 / システムオンチップ / 瞬時処理システム / 知的電子システム / 画像情報処理 / High Performance Computing / Scientific Computing / プロセッサアーキテクチュ / ハイパフォーマンスコンピューティング / 科学技術計算 / 計算システム / 多重故障 / モデル化 / ディペンダブルコンピューティング / マルコフモデル / 時間的冗長度 / 空間的冗長度 / 故障率変動 / チェックポインティング / 高信頼化 / トレース理論 / 時相論理 / ペトリネット / 非同期式回路 / 形式的検証 Less

Dependable VLSI design methodology which conquers engineering limits due to shrinking device sizePrincipal Investigator
- Principal Investigator
  
  NANYA Takashi
- Project Period (FY)
  2007 – 2009
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  The University of Tokyo
故障率の変動を考慮した空間冗長度の時間畳み込みによるクラスタシステムの高信頼化
- Principal Investigator
  
  中村宏
- Project Period (FY)
  2006 – 2007
- Research Category
  
  Grant-in-Aid for Exploratory Research
- Research Field
  
  Computer system/Network
- Research Institution
  The University of Tokyo
Architecture and Design Method for High-Quality Hetero-Timing VLSI SystemsPrincipal Investigator
- Principal Investigator
  
  NANYA Takashi
- Project Period (FY)
  2005 – 2006
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  The University of Tokyo
空間冗長度の時間畳み込みによるクラスタシステムの高信頼化
- Principal Investigator
  
  NAKAMURA Hiroshi
- Project Period (FY)
  2004 – 2005
- Research Category
  
  Grant-in-Aid for Exploratory Research
- Research Field
  
  Computer system/Network
- Research Institution
  The University of Tokyo
Low-Power and High-Performance Processor based on Co-optimization of Architecture and Compiler
- Principal Investigator
  
  NAKAMURA Hiroshi
- Project Period (FY)
  2002 – 2005
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  計算機科学
- Research Institution
  The University of Tokyo
Design Methodology for Advanced VLSI Systems with Heterogeneous TimingPrincipal Investigator
- Principal Investigator
  
  NANYA Takashi
- Project Period (FY)
  2001 – 2002
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  計算機科学
- Research Institution
  The University of Tokyo
Ultra High-Performance Architecture for Real-Time ProcessingPrincipal Investigator
- Principal Investigator
  
  NANYA Takashi
- Project Period (FY)
  2000 – 2002
- Research Category
  
  Grant-in-Aid for Scientific Research on Priority Areas
- Review Section
  
  Science and Engineering
- Research Institution
  The University of Tokyo
Mixed Integrated Systems for Real-Time Intelligent Processing
- Principal Investigator
  
  OHMI Tadahiro
- Project Period (FY)
  1999 – 2003
- Research Category
  
  Grant-in-Aid for Scientific Research on Priority Areas
- Review Section
  
  Science and Engineering
- Research Institution
  TOHOKU UNIVERSITY
Research on Software Controlled Integrated Memory Architecture for Large Scientific Computing
- Principal Investigator
  
  NAKAMURA Hiroshi
- Project Period (FY)
  1998 – 1999
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  計算機科学
- Research Institution
  Research on Software Controlled Integrated Memory Architecture for Large Scientific Computing
Study on Asynchronous VLSI System Design MethodologyPrincipal Investigator
- Principal Investigator
  
  NANYA Takashi
- Project Period (FY)
  1997 – 1999
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  計算機科学
- Research Institution
  The University of Tokyo
Study on Implementation and Evaluation of High-performance Asynchronous MicroprocessorPrincipal Investigator
- Principal Investigator
  
  NANYA Takashi
- Project Period (FY)
  1995 – 1996
- Research Category
  
  Grant-in-Aid for Scientific Research (A)
- Research Field
  
  計算機科学
- Research Institution
  The University of Tokyo
  Tokyo Institute of Technology
非同期式プロセッサの設計検証システムに関する研究
- Principal Investigator
  
  TONEDA Tomohiro
- Project Period (FY)
  1994
- Research Category
  
  Grant-in-Aid for General Scientific Research (C)
- Research Field
  
  計算機科学
- Research Institution
  Tokyo Institute of Technology
Study on Advanced Environment for VLSI System Design Education in UniversitiesPrincipal Investigator
- Principal Investigator
  
  NANYA Takashi
- Project Period (FY)
  1994 – 1995
- Research Category
  
  Grant-in-Aid for Co-operative Research (A)
- Research Field
  
  計算機科学
- Research Institution
  Tokyo Institute of Technology
Study on Architecture and Design Methdology of Asynchronous ProcessorsPrincipal Investigator
- Principal Investigator
  
  NANYA Takashi
- Project Period (FY)
  1992 – 1993
- Research Category
  
  Grant-in-Aid for General Scientific Research (B)
- Research Field
  
  情報工学
- Research Institution
  Tokyo Institute of Technology
Research on Automatic Synthesis of Self-Checking Processors.Principal Investigator
- Principal Investigator
  
  NANYA Takashi
- Project Period (FY)
  1990 – 1991
- Research Category
  
  Grant-in-Aid for General Scientific Research (B)
- Research Field
  
  情報工学
- Research Institution
  Tokyo Institute of Technology
セルフチェッキング機能に基づくVLSIテスト方式に関する研究Principal Investigator
- Principal Investigator
  
  南谷崇
- Project Period (FY)
  1988 – 1989
- Research Category
  
  Grant-in-Aid for General Scientific Research (C)
- Research Field
  
  計算機工学
- Research Institution
  Tokyo Institute of Technology

All 2010 2009 2008 2007 2006 2005 2004

All Journal Article Presentation Book

[Book] 論理回路の基礎2009
- Author(s)
  南谷崇
- Total Pages
  232
- Publisher
  サイエンス社
- Data Source
  KAKENHI-PROJECT-19300009
[Journal Article] A Behavioral Synthesis System for Asynchronous Circuits with Bundled-Data Implementation2009
- Author(s)
  Naohiro Hamada, Yuki Shiga, Takao Konishi, Hiroshi Saito, Tomohiro Yoneda, Chris Myers, Takashi Nanya
- Journal Title
  
  IPSJ Journal Vol. 2
  
  Pages: 65-79
- NAID
  130000120666
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19300009
[Journal Article] Scheduling Methods for Asynchronous Circuits in Bundled-Data Implementation Based on the Approximation of Start Times2007
- Author(s)
  Hiroshi Saito, Naohiro Hamada, Nattha Jindapetch, Tomohiro Yoneda, Chris Myers, Takashi Nanya
- Journal Title
  
  IEICE Trans. on Fundamentals of Electronics, Communications, and Computer Sciences Vol. E90-A, No. 12
  
  Pages: 2790-2799
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19300009
[Journal Article] An optimal Solution for Caching Multimedia Objects in Transcoding Proxies2007
- Author(s)
  W. Qu, K. Li, M. Kitsuregawa, T. Nanya
- Journal Title
  
  Computer Communications Vol. 30, No. 8
  
  Pages: 1802-1810
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19300009
[Journal Article] Determination of worst-case independent clock periods for resource-constrained systems2006
- Author(s)
  K.Jindapetch, H.Saito, K.Thongnoo, T.Nanya
- Journal Title
  
  Proc. ECTI-CON2006 Vol.1
  
  Pages: 344-347
- Data Source
  KAKENHI-PROJECT-17300013
[Journal Article] A novel design method for asynchronous bundled-data transfer circuits considering characteristics of delay variations2006
- Author(s)
  M.Imai, T.Nanya
- Journal Title
  
  Proc. ASYNC2006
  
  Pages: 68-77
- Data Source
  KAKENHI-PROJECT-17300013
[Journal Article] 非同期ネットワークオンチップ技術の可能性と課題2006
- Author(s)
  南谷崇
- Journal Title
  
  日本学術振興会シリコン超集積化システム第165委員会第41回研究会資料
  
  Pages: 50-70
- Data Source
  KAKENHI-PROJECT-17300013
[Journal Article] 束データ方式による非同期式回路の動作合成手法の提案2006
- Author(s)
  濱田尚宏, 小西隆夫, 齋藤寛, 米田友洋, 南谷崇
- Journal Title
  
  情報処理学会システムLSI設計技術研究会資料 Vol.2006, No.126
  
  Pages: 71-76
- NAID
  110005717340
- Data Source
  KAKENHI-PROJECT-17300013
[Journal Article] ILP-based Scheduling for Asynchronous Circuits in Bundled-Data Implementation2006
- Author(s)
  H.Saito, N.Jindapetch, T.Yoneda, C.Myers, T.Nanya
- Journal Title
  
  Proc. CIT2006 (CD-ROM)
- Data Source
  KAKENHI-PROJECT-17300013
[Journal Article] 1 out of 4符号を用いた低消費電力非同期式回路設計2006
- Author(s)
  藤井智弘, 今井雅, 中村宏, 南谷崇
- Journal Title
  
  電子情報通信学会集積回路研究会資料 Vol.106, No.27
  
  Pages: 19-24
- NAID
  110004824024
- Data Source
  KAKENHI-PROJECT-17300013
[Journal Article] A design method of high performance and low power functional units considering delay variations2006
- Author(s)
  K.Watanabe, M.Imai, M.Kondo, H.Nakamura, T.Nanya
- Journal Title
  
  IEICE Trans. on Fundamentals Vol.E89-A, No.12
  
  Pages: 3519-3528
- NAID
  110007537855
- Data Source
  KAKENHI-PROJECT-17300013
[Journal Article] 空間的に故障率が異なる計算機クラスタシステムにおけるチェックポインティング2006
- Author(s)
  東美和子, 近藤正章, 今井雅, 中村宏, 南谷崇
- Journal Title
  
  電子情報通信学会論文誌分冊D Vol.J89-D
  
  Pages: 1705-1716
- NAID
  110007380510
- Data Source
  KAKENHI-PROJECT-18650010
[Journal Article] GALS型SoCの低消費電力化のためのタスクスケジューリング手法2005
- Author(s)
  渡辺亮, 近藤正章, 今井雅, 中村宏, 南谷崇
- Journal Title
  
  情報処理学会アーキテクチャ研究会 2005-ARC-164
  
  Pages: 61-66
- Data Source
  KAKENHI-PROJECT-17300013
[Journal Article] BIT単位の遅延変動を考慮した高性能低消費電力演算回路の設計2005
- Author(s)
  渡邊孝一, 今井雅, 近藤正章, 中村宏, 南谷崇
- Journal Title
  
  電子情報通信学会VLD研究会 VLD2005-59,ICD2005-154,DC2005-36
  
  Pages: 37-42
- NAID
  110004018519
- Data Source
  KAKENHI-PROJECT-17300013
[Journal Article] A novel design method using delay-variation-aware cell libraries for asynchronous bundled-data transfer circuits2005
- Author(s)
  M.Imai, C.Kogure, T.Nanya
- Journal Title
  
  ITC-CSCC
  
  Pages: 441-442
- Data Source
  KAKENHI-PROJECT-17300013
[Journal Article] 遅延変動特性を考慮したタイシング信号設計方式に関する検討2005
- Author(s)
  今井雅, 渡邊孝一, 近藤正章, 中村宏, 南谷崇
- Journal Title
  
  電子情報通信学会VLD研究会 VLD2005-59,ICD2005-154,DC2005-36
  
  Pages: 31-36
- Data Source
  KAKENHI-PROJECT-17300013
[Journal Article] A scheduling method for asychronous bundled-data implementations based on the completion of data operations2005
- Author(s)
  H.Saito, N.Jindapetch, T.Yoneda, C.Meyers, T.Nanya
- Journal Title
  
  ITC-CSCC
  
  Pages: 433-434
- Data Source
  KAKENHI-PROJECT-17300013
[Journal Article] 空間的・時間的な故障率の変動を考慮したチェックポインティング手法の初期検討2005
- Author(s)
  東美和子, 近藤正章, 今井雅, 中村宏, 南谷崇
- Journal Title
  
  信学技報 DC2005-14
  
  Pages: 7-12
- NAID
  110003224491
- Data Source
  KAKENHI-PROJECT-16650008
[Journal Article] 多重故障を考慮した計算機クラスタ向けSkewed Checkpointingの検討2004
- Author(s)
  田島裕也, 林田卓朗, 近藤正章, 今井雅, 中村宏, 南谷崇
- Journal Title
  
  信学技報 DC2004-19(2004-07)
  
  Pages: 37-42
- NAID
  110003173715
- Data Source
  KAKENHI-PROJECT-16650008
[Journal Article] 多重故障に適応したSkewed Checkpointingの提案2004
- Author(s)
  田島裕也, 林田卓朗, 近藤正章, 今井雅, 中村宏, 南谷崇
- Journal Title
  
  先進的計算基盤システムシンポジウムSACSIC2004
  
  Pages: 153-154
- Data Source
  KAKENHI-PROJECT-16650008
[Journal Article] Skewed Checkpointing for Tolerating Multi-Node Failures2004
- Author(s)
  H.Nakamura, T.Hayashida, M.Kondo, Y.Tajima, M.Imai, T.Nanya
- Journal Title
  
  Proceedings of IEEE SRDS '04
  
  Pages: 116-125
- Data Source
  KAKENHI-PROJECT-16650008
[Presentation] Inter-Module Error Propagation Paths in Monolithic Operating System Kernels2010
- Author(s)
  Roberto Jung Drebes, Takashi Nanya
- Organizer
  EDCC2010
- Place of Presentation
  Valencia, Spain (to appear)
- Data Source
  KAKENHI-PROJECT-19300009
[Presentation] Zapmem : a Framework for Testing the Effect of Memory Corruption Errors on Operating System Kernel Reliability2009
- Author(s)
  Roberto Jung Drebes, Takashi Nanya
- Organizer
  PRDC2009
- Place of Presentation
  Shanghai, China
- Year and Date
  2009-11-16
- Data Source
  KAKENHI-PROJECT-19300009
[Presentation] プロセス二重化とプロセス対交換によるチップマルチプロセッサの高信頼化手法2009
- Author(s)
  長井智英,今井雅,南谷崇
- Organizer
  デザインガイア 2009
- Place of Presentation
  高知
- Year and Date
  2009-12-03
- Data Source
  KAKENHI-PROJECT-19300009
[Presentation] Fine-grain Leakage Power Reduction Method for m-out-of-n Encoded Circuits Using Multi-Threshold-Voltage Transistors2009
- Author(s)
  Masashi Imai, Kouei Takada, Takashi Nanya
- Organizer
  Async2009
- Place of Presentation
  Chapel Hill, NC, USA
- Year and Date
  2009-05-20
- Data Source
  KAKENHI-PROJECT-19300009
[Presentation] A Design Method for 1-out-of-4 Encoded Low-Power Self-Timed Circuits using Standard Cell Libraries2008
- Author(s)
  Masashi Imai, Takashi Nanya
- Organizer
  ACSD2008
- Place of Presentation
  Xian, China
- Data Source
  KAKENHI-PROJECT-19300009
[Presentation] AN Optimization Method for Synchronous Fine-Grained Pipelines Based on Optimal Pipeline Stage Partitioning2008
- Author(s)
  Nattha Jindapetch, Hiroshi Saito, Krerkchai Thongnoo, Takashi Nanya
- Organizer
  ICESIT2008
- Place of Presentation
  Bangkok, Thailand
- Data Source
  KAKENHI-PROJECT-19300009
[Presentation] Discovering Implicit Redundancies in Network Communications for Detecting Inconsistent Values2008
- Author(s)
  Bogdan Tomoyuki Nassu, Takashi Nanya, Hiroshi Nakamura
- Organizer
  International Conference on Data Mining
- Place of Presentation
  Pisa, Italy
- Data Source
  KAKENHI-PROJECT-19300009
[Presentation] Interaction Faults Caused by Third-Party External Systems-a Case Study and Challenge2008
- Author(s)
  B. T. Nassu, T. Nanya
- Organizer
  ISAS2008
- Place of Presentation
  東京
- Data Source
  KAKENHI-PROJECT-19300009
[Presentation] Detecting Inconsistent Values caused by Interaction Faults Using Automatically Located Implicit Redundancies2008
- Author(s)
  Bogdan Tomoyuki Nassu, Takashi Nanya, Hiroshi Nakamura
- Organizer
  PRDC2008
- Place of Presentation
  Taipei, Taiwan
- Data Source
  KAKENHI-PROJECT-19300009
[Presentation] A Behavioral Synthesis Method for Asynchronous Circuits with Bundled-Data Implementation2008
- Author(s)
  H. Hamada, Y. Shiga, Hiroshi Saito, Tomohiro Yoneda, Chris Myers, Takashi Nanya
- Organizer
  ACSD2008
- Place of Presentation
  Xian, China
- Data Source
  KAKENHI-PROJECT-19300009
[Presentation] Limitations of the Linux Fault Injection Framework to Test DMA Address Errors2008
- Author(s)
  Roberto Jung Drebes, Takashi Nanya
- Organizer
  PRDC2008
- Place of Presentation
  Taipei, Taiwan
- Data Source
  KAKENHI-PROJECT-19300009
[Presentation] Injecting Inconsistent Values Caused by Interaction Faults for Experimental Dependability Evaluation2008
- Author(s)
  B. T. Nassu, T. Nanya
- Organizer
  EDCC2008
- Place of Presentation
  Lithuania
- Data Source
  KAKENHI-PROJECT-19300009
[Presentation] Performance Comparison between Self-Timed Circuits and Synchronous Circuits Based on the Technology Roadmap of Semiconductors2008
- Author(s)
  Masashi Imai, Takashi Nanya
- Organizer
  WDSN2008
- Place of Presentation
  Anchorage, USA
- Data Source
  KAKENHI-PROJECT-19300009
[Presentation] マルチ閾値電圧トランジスタを用いた2線2相式非同期式回路のリーク電力削減手法2008
- Author(s)
  高田幸永, 今井雅, 中村宏, 南谷崇
- Organizer
  デザインガイア 2008
- Place of Presentation
  福岡
- Data Source
  KAKENHI-PROJECT-19300009
[Presentation] 共有資源の優先度制御によるチップ・マルチプロセッサの省電力化手法2008
- Author(s)
  椎名公康, 近藤正章, 今井雅, 中村宏, 南谷崇
- Organizer
  SACSIS2008
- Place of Presentation
  広島
- Data Source
  KAKENHI-PROJECT-19300009
[Presentation] プロセス変動を考慮した電流制御による低電力化手法2007
- Author(s)
  金均東, 今井雅, 中村宏, 南谷崇
- Organizer
  デザインガイア2007
- Place of Presentation
  福岡
- Data Source
  KAKENHI-PROJECT-19300009
[Presentation] Topology Discovery in Dynamic and Decentralized Networks with MobileAgents and Swarm Intelligence2007
- Author(s)
  Bogdan T. Nassu, Takashi Nanya, Elias Procopio Duarte Jr.
- Organizer
  ISDA2007
- Place of Presentation
  Rio de Janeiro, Brazil
- Data Source
  KAKENHI-PROJECT-19300009
[Presentation] An Efficient Method for Improving Data Collection Precision in Lifetime-adaptive Wireless Sensor Networks2007
- Author(s)
  W. Qu, M. Kitsuregawa, K. Li, T. Nanya
- Organizer
  ICC2007
- Place of Presentation
  Glasgow, Scotland
- Data Source
  KAKENHI-PROJECT-19300009
[Presentation] Power Reduction of Chip Multi-Processors using Shared Resource Control Cooperating with DVFS2007
- Author(s)
  R. Watanabe, M. Kondo, H. Nakamura, T. Nanya
- Organizer
  ICCD2007
- Place of Presentation
  CA, USA
- Data Source
  KAKENHI-PROJECT-19300009
[Presentation] 共有資源の優先度と電源電圧の協調制御によるチップマルチプロセッサの省電力化2007
- Author(s)
  椎名公康, 近藤正章, 今井雅, 中村宏, 南谷崇
- Organizer
  デザインガイア2007
- Place of Presentation
  福岡
- Data Source
  KAKENHI-PROJECT-19300009

1. NAKAMURA Hiroshi (20212102)

# of Collaborated Projects: 8 results

# of Collaborated Products: 10 results
2. TONEDA Tomohiro (30182851)

# of Collaborated Projects: 5 results

# of Collaborated Products: 0 results
3. IMAI Masahi (70323665)

# of Collaborated Projects: 3 results

# of Collaborated Products: 15 results
4. KONDO Masaaki (30376660)

# of Collaborated Projects: 3 results

# of Collaborated Products: 8 results
5. TOHMA Yoshihiro (50016317)

# of Collaborated Projects: 3 results

# of Collaborated Products: 0 results
6. FUJIWARA Eiji (20211526)

# of Collaborated Projects: 3 results

# of Collaborated Products: 0 results
7. YASUURA Hiroto (80135540)

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
8. UENO Yoichiro (70262285)

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
9. KAMIYAMA Kazuto (60447331)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
10. TAKAHASHI Ryuichi (30236335)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
11. HIROSE Masataka (10034406)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
12. AMANO Hideharu (60175932)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
13. UEDA Kazuhiro (60203436)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
14. HOH Kohichiro (60211538)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
15. KAGOTANI Hiroto (50271060)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
16. KUWAKO Masashi (20292766)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
17. OHMI Tadahiro (20016463)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
18. IWATA Akira (30263734)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
19. YAMANAKA Takeshi (00005547)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
20. ASADA Kunihiro (70142239)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
21. SATO Mitsuhisa (60333481)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
22. 白川功 (10029100)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
23. 寺田浩詔 (80028985)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
24. FUKUMA Masao

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
25. 山田八郎

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results

NANYA Takashi 南谷 崇

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Dependable VLSI design methodology which conquers engineering limits due to shrinking device sizePrincipal Investigator

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故障率の変動を考慮した空間冗長度の時間畳み込みによるクラスタシステムの高信頼化

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Architecture and Design Method for High-Quality Hetero-Timing VLSI SystemsPrincipal Investigator

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空間冗長度の時間畳み込みによるクラスタシステムの高信頼化

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Low-Power and High-Performance Processor based on Co-optimization of Architecture and Compiler

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Design Methodology for Advanced VLSI Systems with Heterogeneous TimingPrincipal Investigator

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Ultra High-Performance Architecture for Real-Time ProcessingPrincipal Investigator

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Mixed Integrated Systems for Real-Time Intelligent Processing

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Research on Software Controlled Integrated Memory Architecture for Large Scientific Computing

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Study on Asynchronous VLSI System Design MethodologyPrincipal Investigator

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Study on Implementation and Evaluation of High-performance Asynchronous MicroprocessorPrincipal Investigator

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非同期式プロセッサの設計検証システムに関する研究

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Study on Advanced Environment for VLSI System Design Education in UniversitiesPrincipal Investigator

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NANYA Takashi 南谷崇