KAJIHARA Seiji 梶原誠司

… Alternative Names

梶原誠司カジハラセイジ

Less

Researcher Number	80252592
Other IDs
External Links
Affiliation (based on the past Project Information) *help	2013 – 2022: 九州工業大学, 大学院情報工学研究院, 教授 2014: 九州工業大学, 情報工学研究院, 教授 2012: 九州工業大学, 情報工学研究院, 教授 2008 – 2011: 九州工業大学, 大学院・情報工学研究院, 教授 2003 – 2007: 九州工業大学, 情報工学部, 教授 … More 2003: 九州工大, 助教授 2002: Kyushu Institute of Technology Department of Computer Science and Electronics, Associate Professor, 情報工学研究科, 助教授 1995 – 2001: 九州工業大学, 情報工学部, 助教授 1993: 大阪大学, 工学部, 助手 Less
Review Section/Research Field	Principal Investigator 計算機科学 / Computer system/Network / Basic Section 60040:Computer system-related / Intensification of Artifact Systems / Computer system Except Principal Investigator 計算機科学 / Computer system/Network / Computer system / Basic Section 60040:Computer system-related
Keywords	Principal Investigator テストパターン生成 / 論理回路 / 計算機システム / ディペンダブル・コンピューティング / テストパターン圧縮 / データマイニング / LSIテスト / システムオンチップ / テストコスト削減 / フォールトトレランス … More / 故障シミュレーション / テスト生成 / 遅延故障 / VLSI / 縮退故障 / 機能安全 / VLSI設計 / コンカレントエラーディテクション / 組み込み自己テスト / 予防安全 / 組込み自己テスト / VLSIテスト / フィールド高信頼化 / ＬＳＩテスト / バーインテスト / アダプティブテスト / fault simulation / dependability / delay fault / bridging fault / fault diagnosis / test pattern generation / logic circuit / design and test of LSIs / N回検出テスト / X故障モデル / ディペンダビリティ / ブリッジ故障 / 故障診断 / LSIの設計とテスト / (1)ディペンダブル・コンピューティング / VLSIの設計とテスト / 高信頼設計 / VLSI の設計とテスト / システムLSIのテスト / ハフマン符号 / 低消費電力テスト / 多重スキャン設計 / テスト圧縮 / VLSI CAD / 故障検査 / 冗長故障判定 / 論理設計 / パス遅延故障 / 組合せ論理回路 / 独立故障集合 / 組合せ回路 … More Except Principal Investigator BDD / LSIテスト / 論理設計 / 関数分解 / FPGA / IR-Drop / 再構成可能論理 / テスト生成 / 遅延テスト / 低電力テスト / 高信頼化 / シフトエラー / Logic design / FGPA / Logic Minimization / AND-OR-EXOR / シフト電力 / LSI回路 / 誤テスト / テスト電力 / スキャンテスト / 高品質化 / 活性化パス / 微小遅延故障 / テスト電力調整 / メモリ / 欠陥検出設計 / 欠陥影響最小化設計 / 欠陥影響定量化 / 欠陥 / 耐ソフトエラー記憶素子 / ディペンダブル・コンピュー / ディペンダブル・コンピュータ / グルーピング / テストクロック / シフトタイミング / ディペンダブル・コンピューティング / 電子デバイス・機器 / 計算機システム / クロックパス / パス遅延 / 信号値遷移 / 誤テスト回避 / テスト電力制御 / クロック / IR Drop / Low Power Test / Scan Design / LSI Test / IRドロップ / 低消費電力テスト / スキャン設計 / functional decomposition / Binary decision diagram / Reconfigurable logic / Memory / 再構成可能倫理 / 再編成可能論理 / Logic synthesis / Reconfigurable logic device / Functional decomposition / Design verification / Logic simulator / 倫理シミュレータ / 設計検証 / 論理シミュレータ / Test pattern generation / Path selection / Path delay fault / Delay testing / High-performance VLSI / 遅延故障 / 故障検査 / VLSI / テストパターン変換 / ハフマン符号 / テストデータ圧縮 / ドント・ケア / 遅延故障テスト / テストパターン生成 / パス選択 / パス遅延故障 / 二分決定グラフ / 高性能VLSI / Multiple-Valued Logic / Time domain multiplexing (TDM) / Symmetric functions / Multiple-output logic function / Multilevel Logic Synthesis / FPGA design / Functional Decomposition / 最小形 / 論理関数 / Complexity of logic networks / Multi-level Logic Synthesis / EXOR Logic Synthesis / Programmable logic device / Three-Level Logic / PLD / 非冗長論理和形 / 論理関数の複雑度 / 論理関数の分解 / 検査容易化設計 / EXOR / 多段論理回路 / 論理合成 / マスク回路 / 入力遷移 / テスト電力安全性 / テストデータ変更 / クロックストレッチ / IR-Dop / キャプチャ電力 / テストデータ / テスト品質 / 最適電力テスト / クロックスキュー / スキャンテスト電力 Less

A study on concurrent error detection for functional safety of logic LSIsPrincipal Investigator
- Principal Investigator
  
  梶原誠司
- Project Period (FY)
  2021 – 2023
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Kyushu Institute of Technology
Research on Defect-Aware Soft-Error Mitigation for Reliable LSIs
- Principal Investigator
  
  温暁青
- Project Period (FY)
  2021 – 2024
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Kyushu Institute of Technology
Preventive safety for VLSIs Based on Adaptive Test during Field OperationPrincipal Investigator
- Principal Investigator
  
  梶原誠司
- Project Period (FY)
  2018 – 2022
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Intensification of Artifact Systems
- Research Institution
  Kyushu Institute of Technology
Shift-Power-Safe Scan Test Methodology for High-Quality Low-Power LSI Circuits
- Principal Investigator
  
  Wen Xiaoqing
- Project Period (FY)
  2017 – 2020
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system
- Research Institution
  Kyushu Institute of Technology
Research on High-Quality Test Method for Avoiding False Testing of Next-Generation Low-Power LSIs
- Principal Investigator
  
  Wen Xiaoqing
- Project Period (FY)
  2015 – 2017
- Research Category
  
  Grant-in-Aid for Challenging Exploratory Research
- Research Field
  
  Computer system
- Research Institution
  Kyushu Institute of Technology
Reliability prediction using manufacturing test results of VLSIsPrincipal Investigator
- Principal Investigator
  
  Kajihara Seiji
- Project Period (FY)
  2015 – 2017
- Research Category
  
  Grant-in-Aid for Challenging Exploratory Research
- Research Field
  
  Computer system
- Research Institution
  Kyushu Institute of Technology
Research on Extra-Low-Power Self-Test for LSI Circuits in Implantable Medical Devices
- Principal Investigator
  
  WEN XIAOQING
- Project Period (FY)
  2013 – 2017
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system
- Research Institution
  Kyushu Institute of Technology
Research on Logic Switching Activity Balanced Test for High-Quality Low-Cost LSIs
- Principal Investigator
  
  WEN Xiaoqing
- Project Period (FY)
  2012 – 2014
- Research Category
  
  Grant-in-Aid for Challenging Exploratory Research
- Research Field
  
  Computer system/Network
- Research Institution
  Kyushu Institute of Technology
Power Adjustment Testing for Next-Generation Low-Power LSI Circuits
- Principal Investigator
  
  WEN Xiaoqing
- Project Period (FY)
  2010 – 2012
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Kyushu Institute of Technology
A study on high quality field test for VLSIsPrincipal Investigator
- Principal Investigator
  
  KAJIHARA Seiji
- Project Period (FY)
  2009 – 2012
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Kyushu Institute of Technology
Research on Advanced VLSI Test for Avoiding Signal Degradation
- Principal Investigator
  
  WEN Xiaoqing
- Project Period (FY)
  2007 – 2009
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system/Network
- Research Institution
  Kyushu Institute of Technology
Research on False Test Avoidance for LSI Yield Improvement
- Principal Investigator
  
  WEN Xiaoqing
- Project Period (FY)
  2005 – 2006
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system/Network
- Research Institution
  Kyushu Institute of Technology
ルック・アップ・テーブル・リングの論理合成
- Principal Investigator
  
  SASAO Tsutomu
- Project Period (FY)
  2004 – 2005
- Research Category
  
  Grant-in-Aid for Exploratory Research
- Research Field
  
  Computer system/Network
- Research Institution
  Kyushu Institute of Technology
Study on LSI testing for multiple fault modelsPrincipal Investigator
- Principal Investigator
  
  KAJIHARA Seiji
- Project Period (FY)
  2004 – 2006
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system/Network
- Research Institution
  Kyushu Institute of Technology
システムLSIに対するテスト効率化手法に関する研究Principal Investigator
- Principal Investigator
  
  梶原誠司
- Project Period (FY)
  2002 – 2004
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  計算機科学
- Research Institution
  Kyushu Institute of Technology
Research on programmable logic elements using the virtual wiring and their logic synthesis method
- Principal Investigator
  
  SASAO Tsutomu
- Project Period (FY)
  2002 – 2004
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  計算機科学
- Research Institution
  Kyusyu Institute of Technology
Development of hardware logic simulator using decision diagrams
- Principal Investigator
  
  SASAO Tsutomu
- Project Period (FY)
  2000 – 2002
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  計算機科学
- Research Institution
  Kyushu Institute of Technology
ULSI時代の高機能テスト生成システムの開発Principal Investigator
- Principal Investigator
  
  梶原誠司
- Project Period (FY)
  1999 – 2000
- Research Category
  
  Grant-in-Aid for Encouragement of Young Scientists (A)
- Research Field
  
  計算機科学
- Research Institution
  Kyushu Institute of Technology
Studies on logic design and testing methodology for very high performance VLSIs
- Principal Investigator
  
  SASAO Tsutomu
- Project Period (FY)
  1999 – 2001
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  計算機科学
- Research Institution
  Kyushu Institute of Technology
Decomposition of Large-Scale Logic Functions
- Principal Investigator
  
  SASAO Tsutomu
- Project Period (FY)
  1998 – 2000
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  計算機科学
- Research Institution
  Kyushu Institute of Technology
A Research on the realization of three-level logic networks
- Principal Investigator
  
  SASAO Tsutomu
- Project Period (FY)
  1996 – 1997
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  計算機科学
- Research Institution
  Kyusyu Institute of Technology
論理回路の遅延故障のテストパターン生成手法に関する研究Principal Investigator
- Principal Investigator
  
  梶原誠司
- Project Period (FY)
  1995
- Research Category
  
  Grant-in-Aid for Encouragement of Young Scientists (A)
- Research Field
  
  計算機科学
- Research Institution
  Kyushu Institute of Technology
組合せ論理回路のテスト集合の圧縮手法に関する研究Principal Investigator
- Principal Investigator
  
  梶原誠司
- Project Period (FY)
  1993
- Research Category
  
  Grant-in-Aid for Encouragement of Young Scientists (A)
- Research Field
  
  計算機科学
- Research Institution
  Osaka University

[Book] はかる×わかる半導体-入門編2013
- Author(s)
  浅田邦博(監修),温暁青,梶原誠司, (他5名)
- Publisher
  日経 BPコンサルティング
- Data Source
  KAKENHI-PROJECT-21300015
[Book] ディペンダブルシステム2005
- Author(s)
  米田友洋, 梶原誠司, 土屋達弘
- Total Pages
  243
- Publisher
  共立出版
- Data Source
  KAKENHI-PROJECT-16500036
[Journal Article] Probability of Switching activity to Locate Hotspots in Logic Circuits2021
- Author(s)
  Y. Zhang, S. Holst, X. Wen, K. Miyase, S. Kajihara, J. Qian
- Journal Title
  
  IEICE Trans. on Inf. & Syst.
  
  Volume: E104-D
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Journal Article] High Precision PLL Delay Matrix with Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital Converter2020
- Author(s)
  Poki Chen, Jian-Ting Lan, Ray-Ting Wang, Nguyen My Qui, Yousuke Miyake and Seiji Kajihara
- Journal Title
  
  IEEE Transactions on Very Large Scale Integration Systems
  
  Volume: Volume: 28, Issue: 4 Issue: 4 Pages: 904-913
- DOI
  10.1109/tvlsi.2019.2962606
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18KT0014, KAKENHI-PROJECT-19K20236
[Journal Article] On Evaluation for Aging-Tolerant Ring Oscillators with Accelerated Life Test And Its Application to A Digital Sensor2020
- Author(s)
  Masayuki Gondo, Yousuke Miyake, Takaaki Kato, Seiji Kajihara
- Journal Title
  
  Proc. IEEE Asian Test Symposium
  
  Volume: - Pages: 1-6
- DOI
  10.1109/ats49688.2020.9301588
- NAID
  120007006769
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18KT0014, KAKENHI-PROJECT-19K20236
[Journal Article] Path Delay Measurement with Correction for Temperature and Voltage Variations2020
- Author(s)
  Yousuke Miyake,Takaaki Kato, Seiji KAJIHARA
- Journal Title
  
  IEEE International Test Conference in Asia
  
  Volume: - Pages: 112-117
- DOI
  10.1109/itc-asia51099.2020.00031
- NAID
  120007006757
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18KT0014, KAKENHI-PROJECT-19K20236
[Journal Article] On-Chip Delay Measurement for Degradation Detection And Its Evaluation under Accelerated Life Test2020
- Author(s)
  Yousuke Miyake, Takaaki Kato, Seiji KAJIHARA, Masao ASO, Haruji FUTAMI, Satoshi MATSUNAGA, Yukiya MIURA,
- Journal Title
  
  IEEE International Symposium on On-Line Testing and Robust System Design, On-line symposium
  
  Volume: - Pages: 1-6
- DOI
  10.1109/iolts50870.2020.9159717
- NAID
  120007006773
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18KT0014, KAKENHI-PROJECT-19K20236
[Journal Article] A Selection Method of Ring Oscillators for An On-Chip Digital Temperature And Voltage Sensor2019
- Author(s)
  Miyake Yousuke、Sato Yasuo、Kajihara Seiji
- Journal Title
  
  IEEE International Test Conference in Asia
  
  Volume: - Pages: 13-18
- DOI
  10.1109/itc-asia.2019.00016
- NAID
  120006777000
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18KT0014, KAKENHI-PROJECT-19K20236
[Journal Article] On-Chip Test Clock Validation Using A Time-to-Digital Converter in FPGAs2019
- Author(s)
  Yousuke Miyake, Seiji Kajihara, Poki Chen
- Journal Title
  
  IEEE International Test Conference in Asia
  
  Volume: - Pages: 57-162
- DOI
  10.1109/itc-asia.2019.00040
- NAID
  120006777001
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18KT0014, KAKENHI-PROJECT-19K20236
[Journal Article] On-Chip Delay Measurement for In-Field Test of FPGAs2019
- Author(s)
  Yousuke Miyake, Yasuo Sato, Seiji Kajihara
- Journal Title
  
  IEEE Pacific Rim International Symposium on Dependable Computing
  
  Volume: - Pages: 130-137
- DOI
  10.1109/itc-asia.2019.00026
- NAID
  120007006775
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18KT0014
[Journal Article] Good die prediction modelling from limited test items2018
- Author(s)
  Takeru Nishimi, Yasuo Sato, Seiji kajihara, Yoshiyuki Nakamura
- Journal Title
  
  Proc. IEEE Int’l Test Conference in Asia
  
  Volume: 2 Pages: 1-6
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-15K12004
[Journal Article] Good die prediction modelling from limited test items2018
- Author(s)
  98.Takeru Nishimi, Yasuo Sato, Seiji kajihara, Yoshiyuki Nakamura
- Journal Title
  
  Proc. IEEE International Test Conference in Asia.
  
  Volume: - Pages: 115-120
- DOI
  10.1109/itc-asia.2018.00030
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18KT0014
[Journal Article] On Flip-Flop Selection for Multi-Cycle Scan Test with Partial Observation in Logic BIST2018
- Author(s)
  100.Shigeyuki Oshima, Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara
- Journal Title
  
  Proc. IEEE Asian Test Symposium
  
  Volume: - Pages: 30-35
- DOI
  10.1109/ats.2018.00017
- NAID
  120006776996
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18KT0014
[Journal Article] Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing2018
- Author(s)
  99.Yucong Zhang, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Hans-Joachim Wunderlich, Jun Qian
- Journal Title
  
  Proc. IEEE Asian Test Symposium
  
  Volume: - Pages: 149-154
- DOI
  10.1109/ats.2018.00037
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18KT0014
[Journal Article] On the effects of real time and contiguous measurement with a digital temperature and voltage sensor2017
- Author(s)
  Yousuke Miyake, Yasuo Sato, Seiji Kajihara
- Journal Title
  
  Proc. IEEE Int’l Test Conference in Asia
  
  Volume: 1 Pages: 1-6
- DOI
  10.1109/itc-asia.2017.8097126
- NAID
  120006776995
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-15K12004
[Journal Article] Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors2017
- Author(s)
  Stefan Holst, Hiroshi Kawagoe, Eric Schneider, Michael A. Kochte, Kohei Miyase, Hans-Joachim Wunderlich, Seiji Kajihara, Xiaoqing Wen
- Journal Title
  
  Proc. IEEE International Test Conference
  
  Volume: 48 Pages: 1-8
- DOI
  10.1109/test.2017.8242055
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K12004
[Journal Article] Locating Hot Spot with Justification Techniques in a Layout Design2017
- Author(s)
  Kohei Miyase, Yudai Kawano, Xiaoqing Wen, Seiji Kajihara
- Journal Title
  
  IEEE Workshop on RTL and High Level Testing
  
  Volume: 17 Pages: 1-4
- NAID
  40021491185
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-15K12004
[Journal Article] Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption2017
- Author(s)
  Yucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Jun Qian
- Journal Title
  
  Proc. IEEE Asian Test Symposium
  
  Volume: 26 Pages: 140-145
- DOI
  10.1109/ats.2017.37
- NAID
  120006784400
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K12004
[Journal Article] A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips2017
- Author(s)
  T. Kato, S. Wang, Y. Sato, S. Kajihara, X. Wen
- Journal Title
  
  IEEE Trans. on Emerging Topics in Computing
  
  Volume: PP Issue: 3 Pages: 1-1
- DOI
  10.1109/tetc.2017.2767070
- NAID
  120007006783
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-15K12003, KAKENHI-PROJECT-15K12004
[Journal Article] Temperature and Voltage Measurement for Field Test Using an Aging-Tolerant Monitor2016
- Author(s)
  Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Yukiya Miura
- Journal Title
  
  IEEE Transactions on Very Large Scale Integration Systems
  
  Volume: 24 Issue: 11 Pages: 3282-3295
- DOI
  10.1109/tvlsi.2016.2540654
- NAID
  120006324033
- Peer Reviewed / Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-15K12004
[Journal Article] Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation2016
- Author(s)
  F. Li, X. Wen, K. Miyase, S. Holst, S. Kajihara
- Journal Title
  
  IEICE Trans. Fundamentals
  
  Volume: E99.A Issue: 12 Pages: 2310-2319
- DOI
  10.1587/transfun.E99.A.2310
- NAID
  130005170516
- ISSN
  0916-8508, 1745-1337
- Language
  English
- Peer Reviewed / Acknowledgement Compliant / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280016, KAKENHI-PROJECT-15K12003, KAKENHI-PROJECT-15K12004
[Journal Article] Physical Power Evaluation of Low Power Logic-BIST Scheme using TEG Chip2015
- Author(s)
  S. Wang, Y. Sato, S. Kajihara, H. Takahashi
- Journal Title
  
  ASP Journal of Low Power Electronics
  
  Volume: 11 Issue: 4 Pages: 1-13
- DOI
  10.1166/jolpe.2015.1410
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-15K12004
[Journal Article] On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST2014
- Author(s)
  A. Tomita, X. Wen, Y. Sato, S. Kajihara, P. Girard, M. Tehranipoor, L.-T. Wang,
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: E97.D Issue: 10 Pages: 2706-2718
- DOI
  10.1587/transinf.2014EDP7039
- NAID
  130004696754
- ISSN
  0916-8532, 1745-1361
- Language
  English
- Peer Reviewed / Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-24650022, KAKENHI-PROJECT-25280016
[Journal Article] LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing2013
- Author(s)
  Y. Yamato, X. Wen, M. A. Kochte, K. Miyase, S. Kajihara, L.-T. Wang
- Journal Title
  
  IEEE Design & Test of Computers
  
  Volume: Vol. 30, No. 4 Issue: 4 Pages: 60-70
- DOI
  10.1109/mdt.2012.2221152
- NAID
  120005895737
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-24650022, KAKENHI-PROJECT-25280016
[Journal Article] A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing2013
- Author(s)
  K. Miyase, R. Sakai, X. Wen, Xiaoqing, M. Aso, H. Furukawa, Y. Yamato, S. Kajihara
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: E96.D Issue: 9 Pages: 2003-2011
- DOI
  10.1587/transinf.E96.D.2003
- NAID
  130003370989
- ISSN
  0916-8532, 1745-1361
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-24650022, KAKENHI-PROJECT-25280016
[Journal Article] DART: Dependable VLSI Test Architecture and Its Implementation2012
- Author(s)
  Yasuo Sato, Seiji Kajihara
- Journal Title
  
  Proc. IEEE Int.Test Conference
  
  Volume: 15 Pages: 2-2
- DOI
  10.1109/test.2012.6401581
- NAID
  120006665005
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing2011
- Author(s)
  Y.Yamato, X.Wen, R.Miyase, H.Furukawa, S.Kajihara
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: E94-D Issue: 4 Pages: 833-840
- DOI
  10.1587/transinf.E94.D.833
- NAID
  10029506602
- ISSN
  0916-8532, 1745-1361
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22300017
[Journal Article] Delay Testing: Improving Test Quality and Avoiding Over-testing2011
- Author(s)
  Seiji Kajihara, (他2名)
- Journal Title
  
  IPSJ Transactions on System LSI Design Methodology
  
  Volume: 4 Pages: 117-130
- DOI
  10.2197/ipsjtsldm.4.117
- NAID
  110009598052
- ISSN
  1882-6687
- Language
  English
- Data Source
  KAKENHI-PROJECT-21300015, KAKENHI-PROJECT-22700054
[Journal Article] Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing2011
- Author(s)
  K. Miyase, K. Noda, H. Ito, K. Hatayama, T. Aikyo, Y. Yamato, H. Furukawa, X. Wen, and S. Kajihara
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: Vol. E94-D, No. 6 Pages: 1216-1226
- NAID
  10029805011
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22300017
[Journal Article] On Delay Test Quality for Test Cubes2010
- Author(s)
  S. Oku, S. Kajihara, Y. Sato, K. Miyase, X. Wen
- Journal Title
  
  IPSJ Transactions on System LSI Design Methodology
  
  Volume: 3 Pages: 283-291
- DOI
  10.2197/ipsjtsldm.3.283
- NAID
  110009599095
- ISSN
  1882-6687
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] On Estimation of NBTI-Induced Delay Degradation2010
- Author(s)
  M.Noda, S.Kajihara, Y.Sato, K.Miyase, X.Wen, Y.Miura
- Journal Title
  
  Proc.of 5th IEEE European Test Symposium
  
  Pages: 107-111
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] Aging test strategy and adaptive test scheduling for soc failure prediction2010
- Author(s)
  H.Yi, T.Yoneda, M.Inoue, Y.Sato, S.Kajihara, H.Fujiwara
- Journal Title
  
  Proc.of IEEE International On-Line Testing Symposium
  
  Pages: 21-26
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] A Study of Capture-Safe Test Generation Flow for At-Speed Testing2010
- Author(s)
  K.Miyase, X.Wen, S.Kajihara, Y.Yamato, A.Takashima, H.Furukawa, K.Noda, N.Ito, K.Hatayama, T.Aikyo, K.Saluja
- Journal Title
  
  IEICE Trans.Inf.& Syst.
  
  Volume: E93-A Pages: 1309-1318
- NAID
  10027367482
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22300017
[Journal Article] High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme2010
- Author(s)
  Kohei Miyase, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara, (他3名)
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: E93-D Issue: 1 Pages: 2-9
- DOI
  10.1587/transinf.E93.D.2
- NAID
  10026812940
- ISSN
  0916-8532, 1745-1361
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] On Test Pattern Compaction with Multi-Cycle and Multi-Observation Scan Test2010
- Author(s)
  Seiji Kajihara, Makoto Matsuzono, Hisato Yamaguchi, Yasuo Sato, Kohei Miyase, Xiaoqing Wen
- Journal Title
  
  Int. Symp. on Communications and Information Technologies
  
  Pages: 723-726
- DOI
  10.1109/iscit.2010.5665084
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] On Delay Test Quality for Test Cubes2010
- Author(s)
  S.Oku, S.Kajihara, Y.Sato, K.Miyase, X.Wen
- Journal Title
  
  IPSJ Transactions on System LSI Design Methodology
  
  Volume: Vol.3 Pages: 283-291
- NAID
  130000418476
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] On Test Pattern Compaction with Multi-Cycle and Multi-Observation Scan Test2010
- Author(s)
  S.Kajihara, M.Matsuzono, H.Yamaguchi, Y.Sato, K.Miyase, X.Wen
- Journal Title
  
  Proc.of 10th International Symposium on Communications and Information Technologies
  
  Pages: 723-726
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] High Launch Switching Activity Reduction in At-Speed Scan Testing using CTX : A Clock-Gating-Based Test Relaxation and X-Filling Scheme2010
- Author(s)
  K.Miyase, X.Wen, H.Furukawa, Y.Yamato, S.Kajihara, P.Girard, L.-T.Wang, M.Tehranipoor
- Journal Title
  
  IEICE Transactions on Information and Systems Vol.E93-D
  
  Pages: 2-9
- NAID
  10026812940
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] On Estimation of NBTI-Induced Delay Degradation2010
- Author(s)
  M. Noda, S. Kajihara, Y. Sato, K. Miyase, X. Wen, Y. Miura
- Journal Title
  
  15thIEEE European Test Symp
  
  Pages: 107-111
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] High Launch Switching Activity Reduction in At-Speed Scan Testing using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme2009
- Author(s)
  K. Miyase, X. Wen, H. Furukawa, Y. Yamato, S. Kajihara, P. Girard, L.-T. Wang, M. Tehranipoor
- Journal Title
  
  IEICE Trans. Inf. & Syst. Vol.E93-D,No.1
  
  Pages: 2-9
- NAID
  10026812940
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19500047
[Journal Article] On Calculation of Delay Range in Fault Simulation for Test Cubes2009
- Author(s)
  S.KAJIHARA, S.OKU, K.MIYASE, X.WEN, Y.SATO
- Journal Title
  
  Proc.of International Symposium on VLSI Design, Automation, and Test
  
  Pages: 64-67
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] A GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-Speed Scan Testing2009
- Author(s)
  Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara
- Journal Title
  
  IEEE 15th Pacific Rim Int. Symp. on Dependable Computing
  
  Pages: 81-86
- DOI
  10.1109/prdc.2009.21
- NAID
  120006784394
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] On Calculation of Delay Range in Fault Simulation for Test Cubes2009
- Author(s)
  Seiji KAJIHARA, (他4名)
- Journal Title
  
  the 2009 Int.Symp. on VLSI Design, Automation, and Test
  
  Pages: 64-67
- DOI
  10.1109/vdat.2009.5158096
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] CAT : A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing2009
- Author(s)
  K.Enokimoto, X.Wen, Y.Yamato, K.Miyase, H.Sone, S.Kajihara, M.Aso, H.Furukawa
- Journal Title
  
  Proc.of Asian Test Symposium
  
  Pages: 99-104
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] A GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-Speed Scan Testing2009
- Author(s)
  Y.Yamato, X.Wen, K.Miyase, H.Furukawa, S.Kajihara
- Journal Title
  
  Proc.of IEEE 15th Pacific Rim International Symposium on Dependable Computing
  
  Pages: 81-86
- NAID
  120006784394
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] A Novel Post-ATPG IR-Drop Reduction Scheme for At-Speed Scan Testing in Broadcast-Scan-Based Test Compression Environment2009
- Author(s)
  K.Miyase, Y.Yamato, K.Noda, H.Ito, K.Hatayama, T.Aikyo, X.Wen, S.Kajihara
- Journal Title
  
  Proc.of International Conference on Computer-Aided Design
  
  Pages: 97-104
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing2009
- Author(s)
  Kazunari Enokimoto, Xiaoqing Wen, Yuta Yamato, Kohei Miyase, Hiroaki Sone, Seiji Kajihara(他2名)
- Journal Title
  
  Proc. Asian Test Symp
  
  Pages: 99-104
- DOI
  10.1109/ats.2009.22
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] High Launch Switching Activity Reduction in At-Speed Scan Testing using CTX : A Clock-Gating-Based Test Relaxation and X-Filling Scheme2009
- Author(s)
  K.Miyase, X.Wen, H.Furukawa, Y.Yamato, S.Kajihara, P.Girard, L.-T.Wang, M.Tehranipoor
- Journal Title
  
  IEICE Trans. Inf.& Syst. E93-D
  
  Pages: 2-9
- NAID
  10026812940
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19500047
[Journal Article] Estimation of Delay Test Quality and Its Application to Test Generation2008
- Author(s)
  S. Kajihara, S. Morishima, M. Yamamoto, X. Wen, M. Fukunaga, K. Hatayama, T. Aikyo
- Journal Title
  
  IPSJ Transaction of System LSI Design Methodology 1
  
  Pages: 104-115
- NAID
  130002073185
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19500047
[Journal Article] Estimation of Delay Test Quality and Its Application to Test Generation2008
- Author(s)
  S. Kajihara, S. Morishima, M. Yamamoto, X. Wen, M. Fukunaga, K. Hatayama, T. Aikyo
- Journal Title
  
  IPSJ Transaction of System LSI Design Methodology Vol.1
  
  Pages: 104-115
- NAID
  130002073185
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19500047
[Journal Article] A Framework of High-quality Transition Fault ATPG for Scan Circuits2006
- Author(s)
  Kajihara, Seiji
- Journal Title
  
  Proceedings of International Test Conference (CD-ROM)
  
  Pages: 6-6
- Data Source
  KAKENHI-PROJECT-16500036
[Journal Article] Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores2005
- Author(s)
  L.Li, K.Chakrabarty, S.Kajihara, S.Swaminathan
- Journal Title
  
  Proceedings of International Conference on VLSI Design
  
  Pages: 53-58
- Data Source
  KAKENHI-PROJECT-16500036
[Journal Article] 中間故障電圧値を扱う故障シミュレーションの高速化について2005
- Author(s)
  温暁青, 梶原誠司, 玉本英夫, K. K. Saluja, 樹下行三
- Journal Title
  
  電子情報通信学会論文誌D-I Vol. J88-D-1,No. 4
  
  Pages: 906-907
- NAID
  10016599053
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17500039
[Journal Article] Efficient Test Set Modification for Capture Power Reduction2005
- Author(s)
  Xiaoqing Wen, Tatsuya Suzuki, Seiji Kajihara, Kohei Miyase, Yoshihiro Minamoto, Laung-Terng Wang, K. K. Saluja
- Journal Title
  
  Journal of Low Power Electronics Issue 3
  
  Pages: 319-330
- NAID
  120006782190
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17500039
[Journal Article] Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation2005
- Author(s)
  Y.Doi, S.Kajihara, X.Wen, L.Li, K.Chakrabarty
- Journal Title
  
  Proceedings of Asia and South Pacific Design Automation Conference
  
  Pages: 59-64
- NAID
  110003318193
- Data Source
  KAKENHI-PROJECT-16500036
[Journal Article] On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies2005
- Author(s)
  X.WEN, S.KAJIHARA, H.TAMAMOTO, K.K.SALUJA, K.KINOSHITA
- Journal Title
  
  IEICE Trans. Info. and Syst. (発表予定)
- Data Source
  KAKENHI-PROJECT-16650013
[Journal Article] On Speed-Up of Fault Simulation for Handling Intermediate Faulty Voltages2005
- Author(s)
  Xiaoqing Wen, Seiji Kajihara, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita
- Journal Title
  
  IEICE Trans. Inf. ＆ Syst D-I, Vol. J88-D-I, No. 4
  
  Pages: 906-907
- NAID
  10016599053
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17500039
[Journal Article] Efficient Test Set Modification for Capture Power Reduction2005
- Author(s)
  X.Wen, T.Suzuki, S.Kajihara, K.Miyase, Y.Minamoto, L.-T.Wang, K.K.Saluja
- Journal Title
  
  Journal of Low Power Electronics Issue 3
  
  Pages: 319-330
- NAID
  120006782190
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17500039
[Journal Article] 中間故障電圧値を扱う故障シミュレーションの高速化について2005
- Author(s)
  温暁青, 梶原誠司, 玉本英夫, Kewal K.Saluja, 樹下行三
- Journal Title
  
  電子情報通信学会論文誌D-1(レター) (発表予定)
- NAID
  10016599053
- Data Source
  KAKENHI-PROJECT-16650013
[Journal Article] Scan tree design : test compression with test vector modification2004
- Author(s)
  K.Miyase, S.Kajihara
- Journal Title
  
  情報処理学会論文誌 Vol.44, No.5
  
  Pages: 1270-1278
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14380146
[Journal Article] Test data compression using don't-care identification and statistical encoding2004
- Author(s)
  S.Kajihara, K.Taniguchi, K.Miyase, I.Pomeranz, S.M.Reddy
- Journal Title
  
  IEICE Trans.Info.and Sys. Vol.87-D, No.3
  
  Pages: 544-550
- NAID
  110003317948
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-14380146
[Journal Article] Test cost reduction for logic circuits-Reduction of test data volume and test application time-2004
- Author(s)
  Y.Higami, S.Kajihara, H.Ichihara, Y.Takamatsu
- Journal Title
  
  IEICE Trans.Info.and Sys. Vol.E87-D-I, No.3
  
  Pages: 291-307
- NAID
  110003171307
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-14380146
[Journal Article] XID : Don't care identification of test patterns for combinational circuits2004
- Author(s)
  K.Miyase, S.Kajihara
- Journal Title
  
  IEEE Trans.Computer-Aided Design of Integrated Circuits and Systems Vol.23, No.2
  
  Pages: 321-326
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14380146
[Journal Article] On Per-Test Fault Diagnosis Using the X-Fault Model2004
- Author(s)
  X.Wen, T.Miyoshi, S.Kajihara, L.T.Wang, K.K.Saluja, K.Kinoshita
- Journal Title
  
  Proceedings of Int'l Conf.on Computer-Aided Design
  
  Pages: 633-640
- Data Source
  KAKENHI-PROJECT-16500036
[Journal Article] Scan tree design : test compression with test vector modification2004
- Author(s)
  K.Miyase, S.Kajihara
- Journal Title
  
  IPSJ Trans. Vol.44, No.5
  
  Pages: 1270-1278
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-14380146
[Journal Article] Multiple Scan Tree Design with Test Vector Modification2004
- Author(s)
  Kohei Miyase, Seiji Kajihara, Sudhakar M.Reddy
- Journal Title
  
  Proceedings of Asian Test Symposium
  
  Pages: 76-81
- Data Source
  KAKENHI-PROJECT-16500036
[Journal Article] 論理回路に対するテストコスト削減法-テストデータ量およびテスト実行時間の削減-(サーベイ論文)2004
- Author(s)
  樋上喜信, 梶原誠司, 市原英行, 高松雄三
- Journal Title
  
  電子情報通信学会論文誌D-I Vol.J87-D-I, No.3
  
  Pages: 291-307
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14380146
[Journal Article] Scan tree design : Test compression with test vector modification2004
- Author(s)
  K.Miyase, S.Kajihara
- Journal Title
  
  情報処理学会論文誌 Vol.44, No.5
  
  Pages: 1270-1278
- Data Source
  KAKENHI-PROJECT-16650013
[Journal Article] Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values2004
- Author(s)
  Seiji Kajihara, Kewal K.Saluja, Sudhakar M.Reddy
- Journal Title
  
  Proceedings of 9^<th> IEEE European Test Symposium
  
  Pages: 108-113
- Data Source
  KAKENHI-PROJECT-16500036
[Journal Article] 論理回路に対するテストコスト削減法-テストデータ量およびテスト実行時間の削減-(サーベイ論文)2004
- Author(s)
  樋上喜信, 梶原誠司, 市原英行, 高松雄三
- Journal Title
  
  電子情報通信学会論文誌D-I Vol.J87-D-I No.3
  
  Pages: 291-307
- Data Source
  KAKENHI-PROJECT-14380146
[Journal Article] Test data compression using don't-care identification and statistical encoding2004
- Author(s)
  S.Kajihara, K.Taniguchi, K.Miyase, I.Pomeranz, S.M.Reddy
- Journal Title
  
  IEICE Trans.Info.and Syst. Vol.E87-D, No.3
  
  Pages: 544-550
- NAID
  110003317948
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14380146
[Journal Article] On test data volume reduction for multiple scan chain designs2003
- Author(s)
  S.M.Reddy, K.Miyase, S.Kajihara, I.Pomeranz
- Journal Title
  
  ACM Transactions on Design Automation of Electronic Systems Vol.8, No.4
  
  Pages: 460-469
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14380146
[Journal Article] Evaluation of delay testing based on path selection2003
- Author(s)
  M.Fukunaga, S.Kajihara, S.Takeoka, S.Yoshimura
- Journal Title
  
  IEICE Trans.Fundamentals. E86-A, No.12
  
  Pages: 3208-3210
- NAID
  110003212604
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14380146
[Journal Article] On selecting testable paths in scan designs2003
- Author(s)
  Y.Shao, S.M.Reddy, I.Pomeranz, S.Kajihara
- Journal Title
  
  Journal of Electronic Testing Theory and Applications (Kluwer Academic Publishers) Vol.19, Issue 4
  
  Pages: 447-456
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14380146
[Journal Article] Evaluation of delay testing based on path selection2003
- Author(s)
  M.Fukunaga, S.Kajihara, S.Takeoka, S.Yoshimura
- Journal Title
  
  IEICE Trans.Fundamentals E86-A, No.12
  
  Pages: 3208-3210
- NAID
  110003212604
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-14380146
[Journal Article] On selecting testable paths in scan designs2003
- Author(s)
  Y.Shao, S.M.Reddy, I.Pomeranz, S.Kajihara
- Journal Title
  
  Journal of Electronic Testing Theory and Applications(Kluwer Academic Publishers) Vol.19, Issue 4
  
  Pages: 447-456
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-14380146
[Journal Article] A Method of static test compaction based on don't care identification2002
- Author(s)
  K.Miyase, S.Kajihara, S.M.Reddy
- Journal Title
  
  IPSJ Trans. Vol.43, No.5
  
  Pages: 1290-1293
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-14380146
[Journal Article] Hybrid BIST design for n-detection test using partially rotational scan2002
- Author(s)
  K.Ichino, T.Asakawa, S.Fukumoto, K.Iawasaki, S.Kajihara
- Journal Title
  
  IEICE Trans.Info.and Syst. Vol.E85-D, No.10
  
  Pages: 1490-1497
- NAID
  110006376578
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14380146
[Journal Article] Average power reduction in scan testing by test vector modification2002
- Author(s)
  S.Kajihara, K.Ishida, K.Miyase
- Journal Title
  
  IEICE Trans.Info.and Syst. Vol.E85-D, No.10
  
  Pages: 1483-1489
- NAID
  110006376577
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-14380146
[Journal Article] テストパターン中の特定ビットにおけるドントケア判定法について2002
- Author(s)
  宮瀬紘平, 梶原誠司, イリスポメランツ, スダーカレディ
- Journal Title
  
  FIT2002 情報科学技術フォーラム情報技術レターズ第1巻2002年, LC-3
  
  Pages: 47-48
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14380146
[Journal Article] Average power reduction in scan testing by test vector Modification2002
- Author(s)
  S.Kajihara, K.Ishida, K.Miyase
- Journal Title
  
  IEICE Trans.Info.and Syst. Vol.E85-D, No.10
  
  Pages: 1483-1489
- NAID
  110006376577
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14380146
[Journal Article] Don't-C are Identification on Specific Bits of Test Patterns2002
- Author(s)
  K.Miyase, S.Kajihara, I.Pomeranz, S.M.Reddy
- Journal Title
  
  FIT2002, Information Technology Letters Vol.1, LC-3
  
  Pages: 47-48
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-14380146
[Journal Article] A Method of static test compaction based on don't care identification2002
- Author(s)
  K.Miyase, S.Kajihara, S.M.Reddy
- Journal Title
  
  情報処理学会論文誌 Vol.43, No.5
  
  Pages: 1290-1293
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14380146
[Patent] 論理値決定方法及び論理値決定プログラム2008
- Inventor(s)
  宮瀬紘平, 温暁青, 梶原誠司, 大和勇太
- Industrial Property Rights Holder
  九州工業大学
- Industrial Property Number
  2008-211473
- Filing Date
  2008-08-02
- Data Source
  KAKENHI-PROJECT-19500047
[Patent] 論理値決定方法及び論理値決定プログラム2008
- Inventor(s)
  宮瀬絋平, 温暁青, 梶原誠司, 大和勇太
- Industrial Property Rights Holder
  九州工業大学
- Industrial Property Number
  2008-211473
- Filing Date
  2008-08-20
- Data Source
  KAKENHI-PROJECT-19500047
[Patent] 半導体論理回路装置のテスト方法、装置及び半導体論理回路装置のテストプログラムを記憶した記憶媒体2005
- Inventor(s)
  温暁青, 梶原誠司
- Industrial Property Rights Holder
  *九州工業大学
- Industrial Property Number
  2005-130806
- Filing Date
  2005-04-28
- Data Source
  KAKENHI-PROJECT-17500039
[Patent] 半導体論理回路装置のテストベクトル生成方法、装置及び半導体論理回路装置のテストベクトル生成プログラムを記憶した記憶媒体2005
- Inventor(s)
  温暁青, 梶原誠司
- Industrial Property Rights Holder
  九州工業大学
- Industrial Property Number
  2005-215214
- Filing Date
  2005-07-26
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17500039
[Patent] 半導体論理回路装置のテストベクトル生成方法、装置及び半導体論理回路装置のテストベクトル生成プログラムを記憶した記憶媒体2005
- Inventor(s)
  温暁青, 梶原誠司
- Industrial Property Rights Holder
  *九州工業大学
- Industrial Property Number
  2005-215214
- Filing Date
  2005-04-28
- Data Source
  KAKENHI-PROJECT-17500039
[Patent] 半導体論理回路装置のテスト方法、装置及び半導体論理回路装置のテストプログラムを記憶した記憶媒体2005
- Inventor(s)
  温暁青, 梶原誠司
- Industrial Property Rights Holder
  九州工業大学
- Industrial Property Number
  2005-130806
- Filing Date
  2005-04-28
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17500039
[Presentation] 信号値遷移確率を用いた高消費電力エリア特定技術の計算処理評価に関する研究2022
- Author(s)
  星野　龍, 宇都宮大喜, 宮瀬紘平, 温　暁青, 梶原誠司
- Organizer
  電子情報通信学会DC研究会
- Data Source
  KAKENHI-PROJECT-18KT0014
[Presentation] オンチップ遅延測定における製造バラツキを考慮した温度電圧影響の補正手法2022
- Author(s)
  加藤隆明, 三宅庸資, 梶原誠司
- Organizer
  電子情報通信学会DC研究会
- Data Source
  KAKENHI-PROJECT-18KT0014
[Presentation] Effective Switching Probability Calculation to Locate Hotspots in Logic Circuits2022
- Author(s)
  T. Utsunomiya, R. Hoshino, K. Miyase, S.-K. Lu, X. Wen, and S. Kajihara
- Organizer
  IEEE Int'l Test Conf. in Asia
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21653
[Presentation] メモリのサイズおよび形状に起因するロジック部の高消費電力エリア特定に関する研究2021
- Author(s)
  高藤大輝, 星野　龍, 宮瀬紘平, 温　暁青, 梶原誠司
- Organizer
  電子情報通信学会DC研究会
- Data Source
  KAKENHI-PROJECT-18KT0014
[Presentation] Evaluation of Power Consumption with Logic Simulation and Placement Information for At-Speed Testing2021
- Author(s)
  Taiki Utsunomiya, Kohei Miyase, Ryu Hoshino, Shyue-Kung Lu, Xiaoqing Wen, Seiji Kajihara
- Organizer
  IEEE Workshop on RTL and High Level Testing
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18KT0014
[Presentation] LSIの高消費電力エリアに対する信号値遷移制御率向上に関する研究2020
- Author(s)
  史傑, 宮瀬紘平, 温暁青, 梶原誠司
- Organizer
  信学技報, Vol. 119, No. 420, DC2019-94
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] 勾配降下法を用いた回路遅延の劣化予測について2020
- Author(s)
  森誠一郎, 権藤昌之, 三宅庸資, 加藤隆明, 梶原誠司
- Organizer
  電子情報通信学会DC研究会
- Data Source
  KAKENHI-PROJECT-18KT0014
[Presentation] Probability of Switching activity to Locate Hotspots in Logic Circuits2020
- Author(s)
  R. Oba, K. Miyase, R. Hoshino, S.-K. Lu, X. Wen, S. Kajihara
- Organizer
  IEEE Workshop on RTL and High Level Testing
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] 機械学習を用いたデジタル温度電圧センサの精度向上手法の検討2020
- Author(s)
  権藤昌之, 三宅庸資, 梶原誠司
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Data Source
  KAKENHI-PROJECT-18KT0014
[Presentation] メモリのサイズおよび形状に起因するロジック部の高消費電力エリア特定に関する研究2020
- Author(s)
  高藤大輝, 星野龍, 宮瀬紘平, 温暁青, 梶原誠司
- Organizer
  電子情報通信学会技術研究報告, DC2020-72
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] LSIの領域毎の信号値遷移確率に基づく電力評価に関する研究2020
- Author(s)
  大庭涼, 星野竜, 宮瀬紘平, 温暁青, 梶原誠司
- Organizer
  信学技報, Vol. 120, No. 236, DC2020-33
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] メモリ搭載LSIに対するロジック部の消費電力解析に関する研究2020
- Author(s)
  児玉優也, 宮瀬紘平, 高藤大輝, 温暁青, 梶原誠司
- Organizer
  信学技報, Vol. 119, No. 420, DC2019-93
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] オンチップ遅延測定における温度電圧影響の補正手法について2020
- Author(s)
  加藤隆明, 三宅庸資, 梶原誠司
- Organizer
  第82回FTC研究会
- Data Source
  KAKENHI-PROJECT-18KT0014
[Presentation] Innovative Test Practices in Asia2020
- Author(s)
  T. Iwasaki, M. Aso, H. Futami, S. Matsunaga, Y. Miyake, T. Kato, S. Kajihara, Y. Miura, S. Lai, G. Hung, H.H. Chen, H. Kobayashi, K. Hatayama
- Organizer
  IEEE VLSI Test Symposium
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18KT0014
[Presentation] LSIの領域毎の信号値遷移確率に基づく電力評価に関する研究2020
- Author(s)
  大庭　涼, 星野　竜, 宮瀬紘平, 温　暁青, 梶原誠司
- Organizer
  電子情報通信学会DC研究会
- Data Source
  KAKENHI-PROJECT-18KT0014
[Presentation] LSIのホットスポット分布の解析に関する研究2019
- Author(s)
  河野雄大, 宮瀬紘平, 呂學坤, 温暁青, 梶原誠司
- Organizer
  電子情報通信学会ディペンダブルコンピューティン研究会
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] A Static Method for Analyzing Hotspot Distribution on the LSI2019
- Author(s)
  K. Miyase, Y. Kawano, S.-K. Lu, X. Wen, S. Kajihara
- Organizer
  IEEE Int'l Test Conf. in Asia
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] LSIのホットスポット分布の解析に関する研究2019
- Author(s)
  河野雄大, 宮瀬紘平, 呂　學坤, 温　暁青, 梶原誠司
- Organizer
  電子情報通信学会DC研究会
- Data Source
  KAKENHI-PROJECT-18KT0014
[Presentation] Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption2019
- Author(s)
  Y. Zhang, S. Holst, X. Wen, K. Miyase, S. Kajihara, J. Qian
- Organizer
  第11回LSIテストセミナー
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] 長期信頼性試験におけるオンチップ遅延測定による劣化観測2019
- Author(s)
  三宅庸資, 加藤隆明, 梶原誠司, 麻生正雄, 二見治司, 松永恵士, 三浦幸也
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Data Source
  KAKENHI-PROJECT-18KT0014
[Presentation] FPGAにおける周期的なフィールドテストのためのオンチップ遅延測定2018
- Author(s)
  三宅庸資, 佐藤康夫, 梶原誠司
- Organizer
  電子情報通信学会DC研究会
- Data Source
  KAKENHI-PROJECT-18KT0014
[Presentation] FPGAにおける自己補正可能なオンチップデジタル温度センサ2018
- Author(s)
  三宅庸資, 梶原誠司
- Organizer
  第17回情報科学技術フォーラム講演論文集(FIT2018)
- Data Source
  KAKENHI-PROJECT-18KT0014
[Presentation] Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing2018
- Author(s)
  Y. Zhang, X. Wen, S. Holst, K. Miyase, S. Kajihara, H.-J. Wunderlich, J. Qian
- Organizer
  IEEE Asian Test Symposium
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] 特定のテスト項目を用いた良品予測モデル作成2018
- Author(s)
  西見武，梶原誠司，中村芳行
- Organizer
  第78回FTC研究会
- Data Source
  KAKENHI-PROJECT-15K12004
[Presentation] Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption2018
- Author(s)
  Y. Zhang, S. Holst, X. Wen, K. Miyase, S. Kajihara, J. Qian
- Organizer
  第17 回情報科学技術フォーラム
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] 論理BISTのテスト電力制御手法とTEG評価について2018
- Author(s)
  加藤隆明, 王　森レイ, 佐藤康夫, 梶原誠司
- Organizer
  電子情報通信学会DC研究会
- Data Source
  KAKENHI-PROJECT-18KT0014
[Presentation] デジタル温度電圧センサにおける特定温度電圧領域の推定精度向上手法2018
- Author(s)
  井上賢二，三宅庸資，梶原誠司
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Data Source
  KAKENHI-PROJECT-15K12004
[Presentation] 正当化操作を用いたレイアウト上のホットスポット特定に関する研究2018
- Author(s)
  河野雄大, 宮瀬紘平, 温暁青, 梶原誠司
- Organizer
  電子情報通信学会DC研究会
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] FPGAにおける自己補正可能なオンチップデジタル温度センサ2018
- Author(s)
  三宅庸資, 梶原誠司
- Organizer
  第17回情報科学技術フォーラム
- Data Source
  KAKENHI-PROJECT-18KT0014
[Presentation] Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors2017
- Author(s)
  S. Holst, E. Schneiderz, H. Kawagoe, M. A. Kochtez, K. Miyase, H.-J. Wunderlichz, S. Kajihara, X. Wen
- Organizer
  Proc. of IEEE Int'l Test Conf.
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] Locating Hot Spot with Justification Techniques in a Layout Design2017
- Author(s)
  K. Miyase, Y. Kawano, X. Wen, S. Kajihara
- Organizer
  IEEE Workshop on RTL and High Level Testing
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K12003
[Presentation] 電源ネットワークに対するIR-Dropの影響範囲特定に関する研究2017
- Author(s)
  宮瀬紘平, 濱崎機一, ザウアーマティアス, ポリアンイリア, ベッカーベルンド, 温暁青, 梶原誠司
- Organizer
  電子情報通信学会 DC研究会
- Place of Presentation
  東京都
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors2017
- Author(s)
  S. Holst, E. Schneider, H. Kawagoe, M. A. Kochtez, K. Miyase, H.-J. Wunderlichz, S. Kajihara, X. Wen
- Organizer
  IEEE Int'l Test Conf.
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K12003
[Presentation] FPGAの自己テストのためのTDCを用いたテストクロック観測手法の検討2017
- Author(s)
  三宅庸資,佐藤康夫,梶原誠司
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Data Source
  KAKENHI-PROJECT-15K12004
[Presentation] Locating Hot Spot with Justification Techniques in a Layout Design2017
- Author(s)
  K. Miyase, Y. Kawano, X. Wen, S. Kajihara
- Organizer
  Proc. of IEEE Workshop on RTL and High Level Testing
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption2017
- Author(s)
  Y. Zhang, S. Holst, X. Wen, K. Miyase, S. Kajihara, J. Qia
- Organizer
  IEEE Asian Test Symp.
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K12003
[Presentation] On Avoiding Test Data Corruption by Optimal Scan Chain Grouping2017
- Author(s)
  Y. Zhang, S. Holst, X. Wen, K. Miyase, S. Kajihara, J. Qian
- Organizer
  第181回SLDM・第46回EMB合同研究発表会
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] 製造テスト項目毎の予測モデルに基づくテストコスト削減について2017
- Author(s)
  木村浩隆,　梶原誠司,　佐藤康夫,　中村芳行
- Organizer
  第76回 FTC研究会
- Place of Presentation
  宮崎市
- Year and Date
  2017-01-19
- Data Source
  KAKENHI-PROJECT-15K12004
[Presentation] Locating Hot Spot with Justification Techniques in a Layout Design2017
- Author(s)
  K. Miyase, Y. Kawano, X. Wen, S. Kajihara
- Organizer
  IEEE Workshop on RTL and High Level Testing
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] 高品質実速度スキャンテスト生成に関する研究2017
- Author(s)
  宮崎俊紀、温暁青、ホルストシュテファン、宮瀬紘平、梶原誠司
- Organizer
  第9回LSIテストセミナー
- Place of Presentation
  福岡市
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption2017
- Author(s)
  Y. Zhang, S. Holst, X. Wen, K. Miyase, S. Kajihara, J. Qian
- Organizer
  Proc. of IEEE Asian Test Symp.
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] スキャンベース論理BISTにおけるマルチサイクルテストの中間観測FF選出手法について2017
- Author(s)
  大島繁之，加藤隆明，王森レイ，佐藤康夫，梶原誠司
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Data Source
  KAKENHI-PROJECT-15K12004
[Presentation] FPGAのフィールドテストにおけるオンチップ遅延劣化検出システムについて2016
- Author(s)
  三宅庸資，佐藤康夫，梶原誠司
- Organizer
  第74回FTC研究会
- Place of Presentation
  廿日市市(広島)
- Year and Date
  2016-01-21
- Data Source
  KAKENHI-PROJECT-15K12004
[Presentation] Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test2016
- Author(s)
  S. Holst, E. Schneider, X. Wen, S. Kajihara, Y. Yamato, H.-J. Wunderlich, M. A. Kochte
- Organizer
  IEEE Asian Test Symp.
- Place of Presentation
  Hiroshima, Japan
- Year and Date
  2016-11-24
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K12003
[Presentation] Measurement of On-Chip Temperature and Voltage Variation Using Digital Sensors2016
- Author(s)
  Yousuke Miyake, Yasuo Sato, Seiji Kajihara
- Organizer
  IEEE Workshop on RTL and High Level Testing
- Place of Presentation
  広島
- Year and Date
  2016-11-24
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K12004
[Presentation] 論理BISTにおけるスキャンイン電力制御手法とTEG評価2016
- Author(s)
  加藤隆明, 王森レイ,　佐藤康夫,　梶原誠司,　温暁青
- Organizer
  情報処理学会DAシンポジウム2016
- Place of Presentation
  加賀市
- Year and Date
  2016-09-14
- Data Source
  KAKENHI-PROJECT-15K12004
[Presentation] A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST2016
- Author(s)
  Takaaki KATO, Senling WANG, Yasuo SATO, Seiji KAJIHARA
- Organizer
  IEEE Asian Test Symposium
- Place of Presentation
  広島
- Year and Date
  2016-11-21
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K12004
[Presentation] Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At- Speed Scan Test2016
- Author(s)
  S. Holst, E. Schneider, X. Wen, S. Kajihara, Y. Yamato, H.-J. Wunderlich, M. A. Kochte
- Organizer
  IEEE Asian Test Symp.
- Place of Presentation
  Hiroshima, Japan
- Year and Date
  2016-11-21
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation2016
- Author(s)
  F. Li, X. Wen, S. Holst, K. Miyase, S. Kajihara
- Organizer
  Int'l Symp. on Applied Engineering and Sciences
- Place of Presentation
  Kitakyushu, Japan
- Year and Date
  2016-12-17
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K12003
[Presentation] 論理BISTにおけるスキャンイン電力制御手法とTEG評価2016
- Author(s)
  加藤隆明, 王森レイ, 佐藤康夫, 梶原誠司, 温暁青
- Organizer
  情報処理学会 DAシンポジウム
- Place of Presentation
  石川県加賀市
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation2016
- Author(s)
  F. Li, X. Wen, S. Holst, K. Miyase, S. Kajihara
- Organizer
  Int'l Symp. on Applied Engineering and Sciences
- Place of Presentation
  Kitakyushu, Japan
- Year and Date
  2016-12-17
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] VLSIテスト技術によるシステムディペンダビリティ向上への期待2015
- Author(s)
  梶原誠司
- Organizer
  電子情報通信学会デザインガイア2015
- Place of Presentation
  長崎市
- Year and Date
  2015-12-01
- Invited
- Data Source
  KAKENHI-PROJECT-15K12004
[Presentation] Failure Prediction of Logic Circuits for High Field Reliability2015
- Author(s)
  Seiji Kajihara
- Organizer
  IEEE Workshop on RTL and High Level Testing
- Place of Presentation
  Mumbai, India
- Year and Date
  2015-11-25
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K12004
[Presentation] Identification of High Power Consuming Areas with Gate Type and Logic Level Information2015
- Author(s)
  K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara
- Organizer
  IEEE European Test Symp.
- Place of Presentation
  Cluj-Napoca, Romania
- Year and Date
  2015-05-28
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K12003
[Presentation] Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch2015
- Author(s)
  K. Asada, X. Wen, S. Holst, K. Miyase, S. Kajihara, M. A. Kochte, E. Schneider, H.-J. Wunderlich, J. Qian
- Organizer
  IEEE Asian Test Symp.
- Place of Presentation
  Bombay, India
- Year and Date
  2015-11-24
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] デジタルモニタを用いたチップ内温度電圧変動の測定について2015
- Author(s)
  三宅庸資, 加藤隆明, 糸永卓矢, 佐藤康夫, 梶原誠司
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  村上市（新潟）
- Year and Date
  2015-12-18
- Data Source
  KAKENHI-PROJECT-15K12004
[Presentation] FPGAのオンチップ遅延測定における温度影響補正の検討2015
- Author(s)
  喜納猛, 三宅庸資, 佐藤康夫, 梶原誠司
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  長崎市
- Year and Date
  2015-12-03
- Data Source
  KAKENHI-PROJECT-15K12004
[Presentation] On Guaranteeing Capture Safety in At-Speed Scan Testing With Broadcast-Scan-Based Test Compression2013
- Author(s)
  K. Enokimoto, X. Wen, K. Miyase, J.-L. Huang, S. Kajihara, L.-T. Wang
- Organizer
  26th Intl. Conf. on VLSI Design
- Place of Presentation
  Pune, India
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST2013
- Author(s)
  A. Tomita, X. Wen, Y. Sato, S. Kajihara, P. Girard, M. Tehranipoor, L.-T. Wang
- Organizer
  IEEE Asian Test Symp.
- Place of Presentation
  Yilan, Taiwan
- Data Source
  KAKENHI-PROJECT-24650022
[Presentation] Controllability Analysis of Local Switching Activity for Layout Design2013
- Author(s)
  K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara
- Organizer
  Workshop on Design and Test Methodologies for Emerging Technologies
- Place of Presentation
  Avignon, France
- Data Source
  KAKENHI-PROJECT-24650022
[Presentation] Controllability Analysis of Local Switching Activity for Layout Design2013
- Author(s)
  K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara
- Organizer
  Workshop on Design and Test Methodologies for Emerging Technologies
- Place of Presentation
  Avignon, France
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] ロジック BIST のキャプチャ電力安全性に関する研究2013
- Author(s)
  冨田明宏, 温暁青, 宮瀬紘平, 梶原誠司
- Organizer
  第68回 FTC 研究会
- Place of Presentation
  秋田市
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST2013
- Author(s)
  A. Tomita, X. Wen, Y. Sato, S. Kajihara, P. Girard, M. Tehranipoor, L.-T. Wang
- Organizer
  IEEE Asian Test Symp.
- Place of Presentation
  Yilan, Taiwan
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] Search Space Reduction for Low-Power Test Generation2013
- Author(s)
  K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara
- Organizer
  IEEE Asian Test Symp.
- Place of Presentation
  Yilan, Taiwan
- Data Source
  KAKENHI-PROJECT-24650022
[Presentation] On Guaranteeing Capture Safety in At-Speed Scan Testing With Broadcast-Scan-Based Test Compression2013
- Author(s)
  K. Enokimoto, X. Wen, K. Miyase, J.-L. Huang, S. Kajihara, and L.-T. Wang
- Organizer
  Proc. 26th Intl. Conf. on VLSI Design
- Place of Presentation
  Pune, India
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] VLSI design and testing for enhanced systems dependability2013
- Author(s)
  Seiji Kajihara
- Organizer
  IEEE International Workshop on Reliability Aware System Design and Test
- Place of Presentation
  Pune, India
- Invited
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] VLSI design and testing for enhanced systems dependability2013
- Author(s)
  Seiji Kajihara, Shojiro Asai
- Organizer
  IEEE Int.Workshop on Reliability Aware System Design and Test (Invited talk)
- Place of Presentation
  Pune, India Jan
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] Search Space Reduction for Low-Power Test Generation2013
- Author(s)
  K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara
- Organizer
  IEEE Asian Test Symp.
- Place of Presentation
  Yilan, Taiwan
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] Failure Prediction of Logic Circuits for High Field Reliability2012
- Author(s)
  Seiji Kajihara
- Organizer
  Int. Workshop on Reliability Aware System Design and Test
- Place of Presentation
  Hyderabad, India
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] マルチサイクル BIST におけるスキャン出力の電力低減手法2012
- Author(s)
  王森レイ,佐藤康夫,梶原誠司,宮瀬紘平
- Organizer
  電子情報通信学会技術研究報告
- Place of Presentation
  福岡市
- Year and Date
  2012-11-28
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] New Test Partition Approach for Segmented Testing with Lower System Failure Rate2012
- Author(s)
  S.Wang, S.Kajihara, Y.Sato, K.Miyase, Xiaoqing Wen
- Organizer
  第66回FTC研究会
- Place of Presentation
  大分県ホテルソラージュ大分・日出
- Year and Date
  2012-01-19
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] ネットリストを用いたドントケアビット数の見積り手法に関する研究2012
- Author(s)
  宮瀬紘平, 梶原誠司, 温暁青
- Organizer
  電子情報通信学会技術研究報告
- Place of Presentation
  福岡市
- Year and Date
  2012-11-28
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] New Test Partition Approach for Rotating Test with Lower Rate2012
- Author(s)
  S.Wang, S.Kajihara, Y.Sato, K.Miyase, X.Wen
- Organizer
  FTC研究会
- Place of Presentation
  日本大分県
- Year and Date
  2012-01-19
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Estimation of the Amount of Don't-Care Bits in Test Vectors2012
- Author(s)
  K. Miyase, S. Kajihara, X. Wen
- Organizer
  IEEE Workshop on RTL and High Level Testing
- Place of Presentation
  Niigata, Japan
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] On Pinpoint Capture Power Management in At-Speed Scan Test Generation2012
- Author(s)
  X. Wen, Y. Nishida, K. Miyase, S. Kajihara, P. Girard, M. Tehranipoor, L.-T. Wang
- Organizer
  IEEE Int'l Test Conf.
- Place of Presentation
  Anaheim, USA
- Data Source
  KAKENHI-PROJECT-24650022
[Presentation] New Test Partition Approach for Segmented Testing with Lower System Failure Rate2012
- Author(s)
  Senling Wang, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen
- Organizer
  第66回 FTC 研究会
- Place of Presentation
  大分
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] 組込み自己テストによるフィールド高信頼化に2012
- Author(s)
  梶原誠司
- Organizer
  電子情報通信学会　デザインガイア2012
- Place of Presentation
  福岡市
- Invited
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] 組込み自己テストによるフィールド高信頼化について2012
- Author(s)
  梶原誠司
- Organizer
  電子情報通信学会デザインガイア 2012(招待講演)
- Place of Presentation
  福岡市
- Year and Date
  2012-11-26
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] 実速度スキャンテストにおける高品質なキャプチャ安全性保障型テスト生成について2012
- Author(s)
  西田優一郎, 温暁青, 工藤雅幸, 宮瀬紘平, 梶原誠司
- Organizer
  FTC研究会
- Place of Presentation
  日本大分県
- Year and Date
  2012-01-21
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] A Novel Capture-Safety Checking Method for Multi-Clock Designs and Accuracy Evaluation with Delay Capture Circuits2012
- Author(s)
  K. Miyase, M. Aso, R. Ootsuka, X. Wen, H. Furukawa, Y. Yamato, K, Enokimoto, S. Kajihara
- Organizer
  IEEE VLSI Test Symp.
- Place of Presentation
  Hawaii, USA
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Estimation of the Amount of Don' t-Care Bits in Test Vectors2012
- Author(s)
  K. Miyase, S. Kajihara, and X. Wen
- Organizer
  Proc. IEEE Workshop on RTL and High Level Testing
- Place of Presentation
  Niigata, Japan
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Failure Prediction of Logic Circuits for High Field Reliability2012
- Author(s)
  S.Kajihara
- Organizer
  International Workshop on Reliability Aware System Design and Test
- Place of Presentation
  Hyderabad, India(Invited talk)
- Year and Date
  2012-01-08
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] A Novel Capture-Safety Checking Method for Multi-Clock Designs and Accuracy Evaluation with Delay Capture Circuits2012
- Author(s)
  K. Miyase, M. Aso, R. Ootsuka, X. Wen, H. Furukawa, Y. Yamato, K, Enokimoto, and S. Kajihara
- Organizer
  Proc. IEEE VLSI Test Symp.
- Place of Presentation
  Hawaii, USA
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Additional Path Delay Fault Detection with Adaptive Test Data2011
- Author(s)
  K.Miyase, H.Tanaka, K.Enokimoto, X.Wen, S.Kajihara
- Organizer
  IEEE Workshop on RTL and High Level Testing
- Place of Presentation
  Jaipur, India
- Year and Date
  2011-11-26
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] A Pattern Partitioning Algorithm for Field Test2011
- Author(s)
  S.Wang, S.Kajihara, Y.Sato, Xiaoxin Fan, S.M.Reddy
- Organizer
  IEEE International Workshop on Reliability Aware System Design and Test
- Place of Presentation
  Chennai (India)
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] A Pattern Partitioning Algorithm for Field Test2011
- Author(s)
  Senling Wang, Seiji Kajihara, (他3名)
- Organizer
  IEEE Int. Workshop on Reliability Aware System Design and Test
- Place of Presentation
  Chennai (India)
- Year and Date
  2011-01-07
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] Genetic Algorithm Based Approach for Segmented Testing2011
- Author(s)
  X.Fan, S.M.Reddy, S.Wang, S.Kajihara, Y.Sato
- Organizer
  5th Workshop on Dependable and Secure Nanocomputing
- Place of Presentation
  Hong Kong, China
- Year and Date
  2011-06-27
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] SAT-based Capture-Power Reduction for At-Speed Broadcast-Scan-Based Test Compression Architectures2011
- Author(s)
  M.A.Kochte, K.Miyase, X.Wen, S.Kajihara, Y.Yamato, K.Enokimoto, H.-J.Wunderlich
- Organizer
  IEEE International Symposium on Low Power Electronics and Design
- Place of Presentation
  Fukuoka, Japan
- Year and Date
  2011-08-01
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] 実速度テストに対する品質考慮ドントケア判定2011
- Author(s)
  河野潤, 宮瀬紘平, 榎元和成, 大和勇太, 温暁青, 梶原誠司
- Organizer
  第64回FTC研究会
- Place of Presentation
  岐阜県恵那市
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] 実速度テストに対する品質考慮ドントケア判定2011
- Author(s)
  河野潤, 宮瀬紘平,榎元和成,大和勇太,温暁青, 梶原誠司
- Organizer
  第64回FTC研究会
- Place of Presentation
  恵那市
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] Additional Path Delay Fault Detection with Adaptive Test Data2011
- Author(s)
  K. Miyase, H. Tanaka, K. Enokimoto, X. Wen, and S. Kajihara
- Organizer
  Proc. IEEE Workshop on RTL and High Level Testing
- Place of Presentation
  Jaipur, India
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Effective Launch Power Reduction for Launch-Off-Shift Scheme with Adjacent-Probability-Based X-Filling2011
- Author(s)
  K. Miyase, U. Uchinodan, K. Enokimoto, Y. Yamato, X. Wen, S. Kajihara, F. Wu, L. Dilillo, A. Bosio, and P. Girard
- Organizer
  Proc. IEEE Asian Test Symp.
- Place of Presentation
  New Delhi, India
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Power-Aware Test Generation with Guaranteed Launch Safety for At-Speed Scan Testing2011
- Author(s)
  X.Wen, K.Enokimoto, K.Miyase, Y.Yamato, M.Kochte, S.Kajihara, P.Girard, M.Tehranipoor
- Organizer
  IEEE VLSI Test Symposium
- Place of Presentation
  Dana Point, USA
- Year and Date
  2011-05-03
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Effective Launch Power Reduction for Launch-Off-Shift Scheme with Adjacent-Probability-Based X-Filling2011
- Author(s)
  K.Miyase, U.Uchinodan, K.Enokimoto, Y.Yamato, X.Wen, S.Kajihara, F.Wu, L.Dilillo, A.Bosio, P.Girard
- Organizer
  IEEE Asian Test Symposium
- Place of Presentation
  New Delhi, India
- Year and Date
  2011-11-22
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] 3値テストパターンに対する遅延テスト品質計算とX割当について2010
- Author(s)
  奥慎治, 梶原誠司, 佐藤康夫, 宮瀬紘平, 温暁青
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  東京都
- Year and Date
  2010-02-15
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] フィールド高信頼化のためのVLSI劣化検知技術(DART)2010
- Author(s)
  佐藤康夫, 梶原誠司, 井上美智子, 米田友和, 大竹哲史, 藤原秀雄, 三浦幸也
- Organizer
  第63回FTC研究会
- Place of Presentation
  埼玉県秩父郡皆野町
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] Circuit failure prediction by field test (DART) with delay-shift measurement mechanism2010
- Author(s)
  Y.Sato, S.Kajihara, M.Inoue, T.Yoneda, S.Ohtake, H.Fujiwara, Y.Miura
- Organizer
  IEICE Integrated Circuits and Devices in Vietnam
- Place of Presentation
  Ho Chi Minh, (Vietnam)
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] A Path Selection Method for Delay Test Targeting Transistor Aging2010
- Author(s)
  M.Noda, S.Kajihara, Y.Sato, K.Miyase, X.Wen, Y.Miura
- Organizer
  IEEE International Workshop on Reliability Aware System Design and Test
- Place of Presentation
  Bangalore, India
- Year and Date
  2010-01-08
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] X-Identification of Transition Delay Fault Tests for Launch-off Shift Scheme2010
- Author(s)
  K.Miyase, F.Wu, L.Dilillo, A.Bosio, P.Girard, X.Wen, S.Kajihara
- Organizer
  IEEE Workshop on RTL and High Level Testing
- Place of Presentation
  Shanghai, China
- Year and Date
  2010-12-06
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] A Path Selection Method for Delay Test Targeting Transistor Aging2010
- Author(s)
  Mitsumasa Noda, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen, Yukiya Miura
- Organizer
  Digest of IEEE International Workshop on Reliability Aware System Design and Test
- Place of Presentation
  Bangalore, India
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] CAT(Critical-Area-Targeted) : A New Paradigm for Reducing Yield Loss Risk in At-Speed Scan Testing2010
- Author(s)
  X.Wen, K.Enokimoto, K.Miyase, S.Kajihara, M.Aso, H.Furukawa
- Organizer
  Symposium II(ISTC/CSTIC) : Metrology, Reliability and Testing
- Place of Presentation
  Shanghai, China
- Year and Date
  2010-03-19
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] フィールド高信頼化のための VLSI 劣化検知技術(DART)2010
- Author(s)
  佐藤康夫, 梶原誠司, (他 5 名)
- Organizer
  第63回FTC研究会資料
- Place of Presentation
  埼玉県皆野町
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] スキャンBISTにおけるマルチサイクルテストと部分観測方式の提案と評価2010
- Author(s)
  山口久登・松薗誠・佐藤康夫・梶原誠司
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  福岡市
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] 3 値テストパターンに対する遅延テスト品質計算と X 割当について2010
- Author(s)
  奥慎治, 梶原誠司, 佐藤康夫 ,宮瀬紘平, 温暁青
- Organizer
  電子情報通信学会技術研究報告
- Place of Presentation
  東京
- Year and Date
  2010-02-15
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] Circuit failure prediction by field test (DART) with delay-shift measurement mechanism2010
- Author(s)
  Y. Sato, S. Kajihara (他5名)
- Organizer
  IEICE 集積回路研究会
- Place of Presentation
  Ho Chi Minh, Vietnam
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] Low-Capture-Power Post-Processing Test Vectors for Test Compression Using SAT Solver2010
- Author(s)
  K K.Miyase, M.A.Kochte, X.Wen, S.Kajihara, H.-J.Wunderlich
- Organizer
  IEEE Workshop on Defect and Date Driven Testing
- Place of Presentation
  Austin, USA
- Year and Date
  2010-11-05
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] A Novel Scan Segmentation Design Method for Avoiding Shift Timing Failure in Scan Testing2010
- Author(s)
  Y.Yamato, X.Wen, M.A.Kochte, K.Miyase, S.Kajihara, L.-T.Wang
- Organizer
  IEEE International Test Conference
- Place of Presentation
  Anaheim, USA
- Year and Date
  2010-09-21
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] A Path Selection Method for Delay Test Targeting Transistor Aging2010
- Author(s)
  M.Noda, S.Kajihara, Y.Sato, K.Miyase, X.Wen, Y.Miura
- Organizer
  IEEE Int' 1 Workshop on Reliability Aware System Design and Test
- Place of Presentation
  Bangalore, India
- Year and Date
  2010-01-08
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] 部分X分解によるX故障モデルを用いた故障診断手法の高速化2010
- Author(s)
  宮瀬紘平, 中村優介, 大和勇太, 温暁青, 梶原誠司
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  東京都
- Year and Date
  2010-02-15
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] A Path Selection Method for Delay Test Targeting Transistor Aging2010
- Author(s)
  M. Noda, S. Kajihara, Y. Sato, K. Miyase, X. Wen, Y. Miura
- Organizer
  Digest of First IEEE Int'l Workshop on Reliability Aware System Design and Test
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] 部分X分解によるX故障モデルを用いた故障診断手法の高速化2010
- Author(s)
  宮瀬紘平, 中村優介, 大和勇太, 温暁青, 梶原誠司
- Organizer
  電子情報通信学会技術研究報告
- Place of Presentation
  東京
- Year and Date
  2010-02-15
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] フィールドテストにおける巡回テストとテスト集合印加順序について2010
- Author(s)
  広実一輝, 梶原誠司, 佐藤康夫, 宮瀬紘平, 温暁青
- Organizer
  第62回FTC研究会
- Place of Presentation
  岡山県総社市
- Year and Date
  2010-01-21
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] フィールドテストにおける巡回テストとテスト集合印加順序について2010
- Author(s)
  広実一輝, 梶原誠司, 佐藤康夫, 宮瀬紘平, 温暁青
- Organizer
  第62回FTC研究会
- Place of Presentation
  総社市
- Year and Date
  2010-01-21
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing2009
- Author(s)
  K. Enokimoto, X. Wen, Y. Yamato, K. Miyase, H. Sone, S. Kajihara, M. Aso, H. Furukawa
- Organizer
  Proc. IEEE Asian Test Symp.
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] On Calculation of Delay Range in Fault Simulation for Test Cubes2009
- Author(s)
  S. Oku, S. Kajihara, K. Miyase, X. Wen, Y. Sato
- Organizer
  Proc. Int'l Symp. on VLSI Design, Automation, and Test
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] On Calculation of Delay Range in Fault Simulation for Test Cubes2009
- Author(s)
  S.Oku, S.Kajihara, K.Miyase, X.Wen, Y.Sato
- Organizer
  Int' 1 Symp.on VLSI Design, Automation, and Test
- Place of Presentation
  Hsinchu, Taiwan
- Year and Date
  2009-04-29
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] ブロードキャストスキャン圧縮環境下における実速度テストに対するIR-Drop削減Post-ATPG手法2009
- Author(s)
  宮瀬紘平, 大和勇太, 埜田健治, 伊藤秀昭, 畠山一実, 相京隆, 温暁青, 梶原誠司
- Organizer
  第61回FTC研究会
- Place of Presentation
  三重県多気郡大台町
- Year and Date
  2009-07-18
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] A Novel Post-ATPG IR-Drop Reduction Scheme for At-Speed Scan Testing in Broadcast-Scan-Based Test Compression Environment2009
- Author(s)
  K.Miyase, K.Noda, H.Ito, K.Hatayama, T.Aikyo, Y.Yamato, X.Wen, S.Kajihara
- Organizer
  IEEE/ACM Int'1 Conf.on Computer Aided Design
- Place of Presentation
  San Jose, USA
- Year and Date
  2009-11-02
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] CAT : A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing2009
- Author(s)
  K.Enokimoto, X.Wen, Y.Yamato, K.Miyase, H.Sone, S.Kajihara, M.Aso, H.Furukawa
- Organizer
  IEEE Asian Test Symp.
- Place of Presentation
  Taichung, Taiwan
- Year and Date
  2009-11-24
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] On Calculation of Delay Range in Fault Simulation for Test Cubes2009
- Author(s)
  Y.Yamato, X.Wen, K.Miyase, H.Furukawa, S.Kajihara
- Organizer
  IEEE 15th Pacific Rim Int' 1 Symp.on Dependable Computing, Automation, and Test
- Place of Presentation
  Shanghai, China
- Year and Date
  2009-11-17
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] A Novel Post-ATPG IR-Drop Reduction Scheme for At-Speed Scan Testing in Broadcast-Scan-Based Test Compression Environment2009
- Author(s)
  K. Miyase, K. Noda, H. Ito, K. Hatayama, T. Aikyo, Y. Yamato, X. Wen, S. Kajihara
- Organizer
  Proc. IEEE/ACM Int'l Conf. on Computer Aided Design
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] 信号値遷移削減のためのドントケア判定率の最適化に関する研究2009
- Author(s)
  別府厳,宮瀬紘平,大和勇太,温暁青,梶原誠司
- Organizer
  電子情報通信学会技術研究報告
- Place of Presentation
  高知市
- Year and Date
  2009-10-04
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] 劣化検知テストにおけるパス選択について2009
- Author(s)
  野田光政, 梶原誠司, 佐藤康夫, 宮瀬紘平, 温暁青, 三浦幸也
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  高知市
- Year and Date
  2009-12-05
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] X-Identification According to Required Distribution for Industrial Circuits2009
- Author(s)
  I.Beppu, K.Miyase, Y.Yamato, X.Wen, S.Kajihara
- Organizer
  IEEE Workshop on RTL and High Level Testing
- Place of Presentation
  Hong Kong
- Year and Date
  2009-11-27
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] X-Identification According to Required Distribution for Industrial Circuits2009
- Author(s)
  I. Beppu, K. Miyase, Y. Yamato, X. Wen, S. Kajihara
- Organizer
  Proc. IEEE Workshop on RTL and High Level Testing
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] 信号値遷移削減のためのドントケア判定率の最適化に関する研究2009
- Author(s)
  別府厳, 宮瀬紘平, 大和勇太, 温暁青, 梶原誠司
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  高知市
- Year and Date
  2009-12-04
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] On Calculation of Delay Range in Fault Simulation for Test Cubes2009
- Author(s)
  Y. Yamato, X. Wen, K. Miyase, H. Furukawa, S. Kajihara
- Organizer
  Proc. IEEE 15th Pacific Rim Int'l Symp. on Dependable Computing, Automation, and Test
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] 劣化検知テストにおけるパス選択について2009
- Author(s)
  野田光政, 梶原誠司, 佐藤康夫, 宮瀬紘平, 温暁青, 三浦幸也
- Organizer
  電子情報通信学会技術研究報告
- Place of Presentation
  高知市
- Year and Date
  2009-10-05
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] Optimizing the Percentage of X-Bits to Reduce Switching Activity2009
- Author(s)
  I.Beppu, K.Miyase, Y.Yamato, X.Wen, S.Kajihara
- Organizer
  IEEE International Workshop on Defect and Data Driven Testing
- Place of Presentation
  Austin, TX, USA
- Year and Date
  2009-11-06
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] X-Identification According to Required Distribution for Industrial Circuits2009
- Author(s)
  Isao Beppu, Kohei Miyase, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara
- Organizer
  IEEE Workshop on RTL and High Level Testing
- Place of Presentation
  Hong, Kong
- Year and Date
  2009-10-27
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] Optimizing the Percentage of X-Bits to Reduce Switching Activity2009
- Author(s)
  Isao Beppu, Kohei Miyase, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara
- Organizer
  IEEE International Workshop on Defect and Data Driven Testing
- Place of Presentation
  USA
- Year and Date
  2009-10-06
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] A Capture- Safe Test Generation Scheme for At-Speed Scan Testing2008
- Author(s)
  X. Wen, K. Miyase, S. Kajihara, H. Furukawa, Y. Yamato, A. Takashima, K. Noda, H. Ito, K. Hatayama, T. Aikyo, K.K. Saluja
- Organizer
  Proc. IEEE European Test Symp.
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] Effective IR-Drop Reduction in At-Speed Scan Testing Using Distribution-Controlling X-Identification2008
- Author(s)
  K. Miyase, K. Noda, H. Ito, K. Hatayama, T. Aikyo, Y. Yamato, H. Furukawa, X. Wen, S. Kajihara
- Organizer
  IEEE/ACM Int'l Conf. on Computer Aided Design
- Place of Presentation
  San Jose, USA
- Year and Date
  2008-11-10
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] GA-Based X-Filling for Reducing Launch Switching Activity in At-Speed Scan Testing2008
- Author(s)
  Y. Yamato, X. Wen, K. Miyase, H. Furukawa, S. Kajihara
- Organizer
  Proc. IEEE Int'l Workshop on Defect Based Testing
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] Effective IR-Drop Reduction in At-Speed Scan Testing Using Distribution-Controlling X-Identification2008
- Author(s)
  K. Miyase, K. Noda, H. Ito, K. Hatayama, T. Aikyo, Y. Yamato, H. Furukawa, X. Wen, S. Kajihara
- Organizer
  Proc. IEEE/ACM Int'l Conf. on Computer Aided Design
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] GA-Based X-Filling for Reducing Launch Switching Activity in At-Speed Scan Testing2008
- Author(s)
  Y. Yamato, X. Wen, K. Miyase, H. Furukawa, S. Kajihara
- Organizer
  IEEE Workshop on Defect and Date Driven Testing (D3T)
- Place of Presentation
  Santa Clara, USA
- Year and Date
  2008-10-30
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] CTX: A Clock- Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing2008
- Author(s)
  H. Furukawa, X. Wen, K. Miyase, Yuta Yamato, S. Kajihara, Patrick Girard, L. -T. Wang, M. Teharanipoor
- Organizer
  Proc. IEEE Asian Test Symp.
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] CTX : A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing2008
- Author(s)
  H. Furukawa, X. Wen, K. Miyase, Yuta Yamato, S. Kajihara, Patrick Girard, L. -T. Wang, M. Teharanipoor
- Organizer
  IEEE Asian Test Symposium
- Place of Presentation
  Saporro, Japan
- Year and Date
  2008-11-27
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] A Method for Improving the Bridging Defect Coverage of a Transition Delay Test Set2007
- Author(s)
  K. Miyase, X. Wen, S. Kajihara, M. Haraguchi, H. Furukawa
- Organizer
  Proc. IEEE Int'l Workshop on Defect Based Testing
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing2007
- Author(s)
  X. Wen, K. Miyase, T. Suzuki, S. Kajihara, Y. Ohsumi, K.K. Saluja
- Organizer
  Proc. IEEE/ACM Design Automation Conf.
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] A Novel Scheme to Reduce Power Supply Noise for High-Quality At-Speed Scan Testing2007
- Author(s)
  X.Wen, K.Miyase, S.Kajihara, T.Suzuki, Y.Yamato, P.Girard, Y.Ohsumi, and L.-T.Wang
- Organizer
  Proc.IEEE Int'l Test Conf.
- Place of Presentation
  Santa Clara, USA
- Year and Date
  2007-10-25
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] Estimation of Delay Test Quality and Its Application to Test Generation2007
- Author(s)
  S.Kajihara, S.Morishima, M.Yamamoto, X.Wen, M.Fukunaga, K.Hatayama, and T.Aikyo
- Organizer
  IEEE/ACM Int'l Conf.on Computer-Aided Design
- Place of Presentation
  San Jose, USA
- Year and Date
  2007-11-06
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing2007
- Author(s)
  X.Wen, K.Miyase, T.Suzuki, S.Kajihara, Y.Ohsumi, K.K.Saluja
- Organizer
  IEEE/ACM Design Automation Conference
- Place of Presentation
  San Diego, USA
- Year and Date
  2007-06-06
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] A Novel Scheme to Reduce Power Supply Noise for High-Quality At-Speed Scan Testing2007
- Author(s)
  X. Wen, K. Miyase, S. Kajihara, T. Suzuki, Y. Yamato, P. Girard, Y. Ohsumi, L. -T. Wang
- Organizer
  Proc. IEEE Int'l Test Conf.
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] A Method for Improving the Bridging Defect Coverage of a Transition Delay Test Set2007
- Author(s)
  K.Miyase, X.Wen, S.Kajihara, M.Haraguchi, and H.Furukawa
- Organizer
  IEEE Int'l Workshop on Defect Based Testing
- Place of Presentation
  Santa Clara, USA
- Year and Date
  2007-10-26
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] Estimation of Delay Test Quality and Its Application to Test Generation2007
- Author(s)
  S. Kajihara, S. Morishima, M. Yamamoto, X. Wen, M. Fukunaga, K. Hatayama, T. Aikyo
- Organizer
  Proc. IEEE/ACM Int'l Conf. on Computer-Aided Design
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] Identification of High Power Consuming Areas with Gate Type and Logic Level Information
- Author(s)
  K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara
- Organizer
  IEEE European Test Symposium
- Place of Presentation
  Cluj-Napoca, Romania
- Year and Date
  2015-05-25 – 2015-05-29
- Data Source
  KAKENHI-PROJECT-24650022
[Presentation] Identification of High Power Consuming Areas with Gate Type and Logic Level Information
- Author(s)
  K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara
- Organizer
  IEEE European Test Symposium
- Place of Presentation
  Cluj-Napoca, Romania
- Year and Date
  2015-05-25 – 2015-05-29
- Data Source
  KAKENHI-PROJECT-25280016

1. WEN Xiaoqing (20250897)

# of Collaborated Projects: 10 results

# of Collaborated Products: 133 results
2. SASAO Tsutomu (20112013)

# of Collaborated Projects: 7 results

# of Collaborated Products: 0 results
3. MIYASE Kohei (30452824)

# of Collaborated Projects: 7 results

# of Collaborated Products: 89 results
4. IGUCHI Yukihiro (60201307)

# of Collaborated Projects: 4 results

# of Collaborated Products: 2 results
5. Holst Stefan (40710322)

# of Collaborated Projects: 4 results

# of Collaborated Products: 15 results
6. 大竹哲史 (20314528)

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
7. Tehranipoor M.

# of Collaborated Projects: 2 results

# of Collaborated Products: 1 results
8. Girard P.

# of Collaborated Projects: 2 results

# of Collaborated Products: 1 results
9. KODA Norio (10099864)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
10. 三宅庸資 (60793403)

# of Collaborated Projects: 1 results

# of Collaborated Products: 16 results
11. KINOSHITA Kozo

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
12. AIKYO Takashi

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
13. TAKAGI Noriaki

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
14. HAMADA Shuji

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
15. HADATE Koji

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
16. SATO Yasuo

# of Collaborated Projects: 1 results

# of Collaborated Products: 13 results
17. NAKAMURA Yoshiyuki

# of Collaborated Projects: 1 results

# of Collaborated Products: 3 results
18. Saluja K. K.

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
19. Keller B.

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
20. Varma P.

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
21. Chakravarty K.

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
22. Wunderlich H.-J.

# of Collaborated Projects: 1 results

# of Collaborated Products: 2 results
23. Wang L.-T.

# of Collaborated Projects: 1 results

# of Collaborated Products: 1 results
24. Jan M. E.

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results

KAJIHARA Seiji 梶原 誠司

梶原 誠司 カジハラ セイジ

Research Projects

Research Products

Co-Researchers

A study on concurrent error detection for functional safety of logic LSIsPrincipal Investigator

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Preventive safety for VLSIs Based on Adaptive Test during Field OperationPrincipal Investigator

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Reliability prediction using manufacturing test results of VLSIsPrincipal Investigator

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A study on high quality field test for VLSIsPrincipal Investigator

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Study on LSI testing for multiple fault modelsPrincipal Investigator

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KAJIHARA Seiji 梶原誠司

梶原誠司カジハラセイジ