ITO Hideo 伊藤秀男

Researcher Number	90042647
Other IDs
External Links
Affiliation (based on the past Project Information) *help	2007 – 2009: Chiba University, 大学院・融合科学研究科, 教授 1996 – 2003: 千葉大学, 工学部, 教授
Review Section/Research Field	Principal Investigator 電子デバイス・機器工学 / Electron device/Electronic equipment Except Principal Investigator Educational technology
Keywords	Principal Investigator FPGA / Error Recovery / Reconfiguration / Defect / 誤り回復 / 再構成 / 欠陥 / Fault Detection / Defect Tolerance / Programmable Chip … More / カバリッジ / SOC / マルチコンテキスト / 故障検出 / 欠陥救済 / プログラマブルチップ / Fault / Architecture / VLSI Chip / Fault Tolerance / コンカレント誤り検出 / 階層構成 / 多重系動作 / 2重バス / 故障検査 / 欠陥回避 / 2次キャッシュ / 故障 / アーキテクチャ / VLSIチップ / フォールトトレランス / スキャンFF / 2線式論理 / シグナルインテグリティ / テスト容易化 / 遅延故障 / テスト容易化設計 / スキャン設計 / ラッチ / VLSI / ソフトエラー / CAD / 回路設計 … More Except Principal Investigator Synchronized multimedia / Life long learning / World Wide Web / Authoring of teaching materials / Video-on-demand / Multimedia / Remote education / VOD / WWW / スライドショウ / 連続メディア / ビデオオンデマンド / 情報基盤設計 / モ-ルス符号 / 英語教材 / 電磁気学 / スライドショー / モールス符号 / 遠隔教材 / オーサリング / IP / TCP / 同期マルチメディア / 生涯学習 / 遠隔教育 / ビデオオンデマンド教材 / マルチメディア教材開発 Less

VLSI CIRCUIT DESIGNS with SOFT ERROR TOLERANCEPrincipal Investigator
- Principal Investigator
  
  ITO Hideo
- Project Period (FY)
  2007 – 2009
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  Chiba University
Design for Fault-Tolerant Programmable ChipsPrincipal Investigator
- Principal Investigator
  
  ITO Hideo
- Project Period (FY)
  2001 – 2003
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  電子デバイス・機器工学
- Research Institution
  Chiba University
Design for Fault Tolerant VLSI ChipsPrincipal Investigator
- Principal Investigator
  
  ITO Hideo
- Project Period (FY)
  1998 – 2000
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  電子デバイス・機器工学
- Research Institution
  Chiba University
Study on multimedia application to higher education
- Principal Investigator
  
  IKEDA Hiroaki
- Project Period (FY)
  1996 – 1998
- Research Category
  
  Grant-in-Aid for Scientific Research (A)
- Research Field
  
  Educational technology
- Research Institution
  Chiba University

All 2010 2009 2008 2007

All Journal Article Presentation Patent

[Journal Article] Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Path2009
- Author(s)
  Kentaroh Katoh, Kazuteru Namba, Hideo Ito
- Journal Title
  
  IEICE Trans. Inf. & Syst. E92-D
  
  Pages: 433-442
- NAID
  10026807952
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19560335
[Journal Article] Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability2009
- Author(s)
  Shuagyu Ruan, Kazuteru Namba, Hideo Ito
- Journal Title
  
  IEICE Trans.Inf. & Syst. E92-D
  
  Pages: 1534-1541
- NAID
  10026810480
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19560335
[Journal Article] Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability2009
- Author(s)
  Shuagyu Ruan, Kazuteru Namba, Hideo Ito
- Journal Title
  
  IEICE Trans.Inf.&Syst. Vol.E92-D, No.8
  
  Pages: 1534-1541
- NAID
  10026810480
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19560335
[Journal Article] Design for Delay Fault Testability of 2-Rail Logic Circuits2009
- Author(s)
  Kentaroh Katoh, Kazuteru Namba, Hideo Ito
- Journal Title
  
  IEICE Trans. Inf. & Syst. E92-D
  
  Pages: 336-341
- NAID
  10026807731
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19560335
[Journal Article] Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger2008
- Author(s)
  Yoichi Sasaki, Kazuteru Namba, Hideo Ito
- Journal Title
  
  J.Electronic Test.:Theory & Appl. Vol.24, No.1-3
  
  Pages: 11-19
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19560335
[Patent] 遅延故障テスト容易化耐ソフトエラーラッチ2007
- Inventor(s)
  池田卓史, 難波一輝, 伊藤秀男
- Industrial Property Rights Holder
  千葉大学
- Industrial Property Number
  2007-111043
- Filing Date
  2007-04-19
- Data Source
  KAKENHI-PROJECT-19560335
[Patent] 半導体集積回路2007
- Inventor(s)
  加藤健太郎, 難波一輝, 伊藤秀男
- Industrial Property Rights Holder
  国立大学法人千葉大学
- Industrial Property Number
  2007-233388
- Filing Date
  2007-09-07
- Data Source
  KAKENHI-PROJECT-19560335
[Patent] 半導体集積回路及び半導体集積回路の検査方法2007
- Inventor(s)
  加藤健太郎, 難波一輝, 伊藤秀男
- Industrial Property Rights Holder
  国立大学法人千葉大学
- Industrial Property Number
  2007-233346
- Filing Date
  2007-09-07
- Data Source
  KAKENHI-PROJECT-19560335
[Patent] 半導体集積回路2007
- Inventor(s)
  池田卓史, 難波一輝, 伊藤秀男
- Industrial Property Rights Holder
  国立大学法人千葉大学
- Industrial Property Number
  2007-111043
- Filing Date
  2007-04-19
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] 耐ソフトエラー性を有するRSフリップフロップ2010
- Author(s)
  中島健吾, 難波一輝, 伊藤秀男
- Organizer
  電子情報通信学会,機能集積情報システム研究会
- Place of Presentation
  京都
- Year and Date
  2010-03-05
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] ソフトエラー訂正機能を有するBILBOフリップフロップ2010
- Author(s)
  難波一輝, 伊藤秀男
- Organizer
  電子情報通信学会,ディペンダブルコンピューティング研究会
- Place of Presentation
  東京
- Year and Date
  2010-04-13
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] BILBO FF with soft error correcting capability2010
- Author(s)
  Kazuteru NAMBA, Hideo ITO
- Organizer
  電子情報通信学会, ディペンダブルコンピューティング研究会
- Place of Presentation
  東京
- Year and Date
  2010-04-13
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] 耐ソフトエラー性を有するRSフリップフロップ2010
- Author(s)
  中島健吾, 難波一輝, 伊藤秀男
- Organizer
  電子情報通信学会, 機能集積情報システム研究会
- Place of Presentation
  京都
- Year and Date
  2010-03-05
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] ラッチ内2重ノード反転ソフトエラーの耐性設計2009
- Author(s)
  坂田雅俊, 難波一輝, 伊藤秀男
- Organizer
  電子情報通信学会,機能集積情報システム研究会
- Place of Presentation
  東京
- Year and Date
  2009-10-16
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] Testing of Switch Bloacks in Three-Dimensional FPGA2009
- Author(s)
  Takumi Hoshi, Kazuteru Namba, Hideo Ito
- Organizer
  2009 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT2009)
- Place of Presentation
  Chicago
- Year and Date
  2009-10-03
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] ラッチ内2重ノード反転ソフトエラーの耐性設計2009
- Author(s)
  坂田雅俊, 難波一輝, 伊藤秀男
- Organizer
  電子情報通信学会, 機能集積情報システム研究会
- Place of Presentation
  東京
- Year and Date
  2009-10-16
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] 遅延故障テスト容易化SHEラッチにおけるエンハンスドスキャンテスト2008
- Author(s)
  難波一輝, 伊藤秀男
- Organizer
  電子情報通信学会, 機能集積情報システム研究会
- Place of Presentation
  奈良市
- Year and Date
  2008-10-31
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] SEU/SET対策FFを用いた遅延故障テスト容易化スキャン構造2008
- Author(s)
  池田卓史, 難波一輝, 伊藤秀男
- Organizer
  2008年電子情報通信学会総合大会
- Place of Presentation
  北九州市
- Year and Date
  2008-03-18
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] ソフトエラーラッチの調査と分類2008
- Author(s)
  坂田雅俊, 難波一輝, 伊藤秀男
- Organizer
  電子情報通信学会, 機能集積情報システム研究会
- Place of Presentation
  筑波市
- Year and Date
  2008-06-27
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] Delay Fault Testability on Two-Rail Logic Circuits2008
- Author(s)
  Kazuteru Namba, Hideo Ito
- Organizer
  23^<rd> IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT2008)
- Place of Presentation
  Boston
- Year and Date
  2008-10-02
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] Soft Error Hardened FF Capable of Detecting Wide Error Pulse2008
- Author(s)
  Shuangyou Ruan, Kazuteru Namba, Hideo Ito
- Organizer
  23^<rd> IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT2008)
- Place of Presentation
  Boston
- Year and Date
  2008-10-02
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] 幅の広いエラーパルス検出機能を有する耐ソフトエラーFF2008
- Author(s)
  阮双玉, 難波一輝, 伊藤秀男
- Organizer
  電子情報通信学会, ディペンダブルコンピューティング研究会
- Place of Presentation
  東京
- Year and Date
  2008-04-23
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] ソフトエラーラッチの検出不可能な固定故障の影響2008
- Author(s)
  中島健吾, 難波一輝, 伊藤秀男
- Organizer
  電子情報通信学会, ディペンダブルコンピューティング研究会
- Place of Presentation
  東京
- Year and Date
  2008-04-23
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] Path Delay Fault Test Set for Two-Rail Logic Circuits2008
- Author(s)
  Kazuteru Namba, Hideo Ito
- Organizer
  2008 14^<th> IEEE Pacific Rim International Symposium on Dependable Computing (PRDC2008)
- Place of Presentation
  Taipei
- Year and Date
  2008-12-15
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] 耐ソフトエラーラッチの検出不可能な固定故障の影響2008
- Author(s)
  中島健吾, 難波一輝, 伊藤秀男
- Organizer
  電子情報通信学会, ディペンダブルコンピューティング研究会
- Place of Presentation
  東京
- Year and Date
  2008-04-23
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] Design for Delay Fault Testing of 2-Rail Logic Circuits2008
- Author(s)
  Kentaroh Katoh, Kazuteru Namba, Hideo Ito
- Organizer
  Indonesia-Japan Joint Scientific Symposium 2008
- Place of Presentation
  Chiba
- Year and Date
  2008-09-10
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] 2線式論理回路に対するパス遅延故障テスト集合2008
- Author(s)
  難波一輝, 伊藤秀男
- Organizer
  電子情報通信学会, 機能集積情報システム研究会
- Place of Presentation
  千葉市
- Year and Date
  2008-03-07
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] 二線式論理を用いたFPGAのソフトエラーに対するフォールトセキュア性2008
- Author(s)
  三浦健宏, 難波一輝, 伊藤秀男
- Organizer
  電子情報通信学会, ディペンダブルコンピューティング研究会
- Place of Presentation
  東京
- Year and Date
  2008-02-08
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing2007
- Author(s)
  Takashi Ikeda, Kazuteru Namba, Hideo Ito
- Organizer
  22^<nd> IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT2007)
- Place of Presentation
  Rome
- Year and Date
  2007-09-27
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] 遅延故障テスト容易化ソフトエラーラッチの設計2007
- Author(s)
  池田卓史, 難波一輝, 伊藤秀男
- Organizer
  電子情報通信学会, ディペンダブルコンピューティング研究会
- Place of Presentation
  東京
- Year and Date
  2007-04-20
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] 2線式論理回路における遅延故障テスト2007
- Author(s)
  難波一輝, 伊藤秀男
- Organizer
  電子情報通信学会, 機能集積情報システム
- Place of Presentation
  神戸
- Year and Date
  2007-10-26
- Data Source
  KAKENHI-PROJECT-19560335
[Presentation] Soft Error Hardened Latch Scheme for Enhanced Sean Based Delay Fault Testing2007
- Author(s)
  Takashi Ikeda, Kazuteru Namba, and Hideo Ito
- Organizer
  22th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems(DFT2007)
- Place of Presentation
  Rome
- Year and Date
  2007-09-27
- Data Source
  KAKENHI-PROJECT-19560335

1. NAMBA Kazuteru (60359594)

# of Collaborated Projects: 2 results

# of Collaborated Products: 28 results
2. IKEDA Hiroaki (00009276)

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
3. KITAKAMI Masato (20282832)

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
4. HIGAKI Yasuhiko (30173131)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
5. HASHIMOTO Kenya (90134353)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
6. KATO Hideo (80009711)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
7. OHMAMEUDA Toshiaki (60272340)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
8. KANEKO Keiichi (20194904)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
9. 八代健一郎 (00125965)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results

ITO Hideo 伊藤 秀男

Research Projects

Research Products

Co-Researchers

VLSI CIRCUIT DESIGNS with SOFT ERROR TOLERANCEPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Design for Fault-Tolerant Programmable ChipsPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Design for Fault Tolerant VLSI ChipsPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Study on multimedia application to higher education

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

[Journal Article] Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Path2009

Author(s)

Journal Title

NAID

Data Source

[Journal Article] Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability2009

Author(s)

Journal Title

NAID

Data Source

[Journal Article] Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability2009

Author(s)

Journal Title

NAID

Data Source

[Journal Article] Design for Delay Fault Testability of 2-Rail Logic Circuits2009

Author(s)

Journal Title

NAID

Data Source

[Journal Article] Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger2008

Author(s)

Journal Title

Data Source

[Patent] 遅延故障テスト容易化耐ソフトエラーラッチ2007

Inventor(s)

Industrial Property Rights Holder

Industrial Property Number

Filing Date

Data Source

[Patent] 半導体集積回路2007

Inventor(s)

Industrial Property Rights Holder

Industrial Property Number

Filing Date

Data Source

[Patent] 半導体集積回路及び半導体集積回路の検査方法2007

Inventor(s)

Industrial Property Rights Holder

Industrial Property Number

Filing Date

Data Source

[Patent] 半導体集積回路2007

Inventor(s)

Industrial Property Rights Holder

Industrial Property Number

Filing Date

Data Source

[Presentation] 耐ソフトエラー性を有するRSフリップフロップ2010

Author(s)

Organizer

Place of Presentation

ITO Hideo 伊藤秀男