YOSHIMURA Masayoshi 吉村正義

… Alternative Names

吉村正義ヨシムラマサヨシ

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Researcher Number	90452820
Other IDs
Affiliation (Current)	2025: 京都産業大学, 情報理工学部, 教授
Affiliation (based on the past Project Information) *help	2023: 京都産業大学, 情報理工学部, 教授 2018 – 2022: 京都産業大学, 情報理工学部, 准教授 2014 – 2017: 京都産業大学, コンピュータ理工学部, 准教授 2013: 九州大学, システム情報科学研究科(研究院, 助教 2010: Kyushu University, 大学院・システム情報科学研究院, 助教 2008 – 2010: Kyushu University, システム情報科学研究院, 助教
Review Section/Research Field	Principal Investigator Basic Section 60040:Computer system-related / Computer system / Computer system/Network Except Principal Investigator Computer system/Network / Basic Section 60040:Computer system-related
Keywords	Principal Investigator トロイ回路 / IPコア / ハードウェアトロイ回路 / LSI / 安全 / テスト容易化設計 / 論理暗号化 / 電子透かし / 知的財産権保護 / 論理ロック … More / IPコア流用検知 / 等価性検証 / 到達不能状態 / 内部状態 / 入力系列生成 / モンテカルロツリーサーチ / SATソルバー / ホワイトボックス / ブラックボックス / 応答圧縮回路 / ベンチマーク回路 / 挿入箇所探索アルゴリズム / トロイ検出用回路 / 情報の保護 / 回路構造情報 / 論理的回路分割 / パタン生成器 / 応答圧縮器 / トロイ検査用回路 / 情報量 / 情報漏洩 / 製造検査 / 設計手法 / 動作合成 / 製造検査容易性 / スキャン設計 / 秘密情報 / テストパタン生成 / 製造テスト / 暗号LSI / LSI設計技術 / 信頼性 / ディペンダブル・コンピューティング / 安全性 / システムLSI / ディペンダブル・コンピユーフィング / システム / 暗号・認証等 / ディペンダブルコンピューティング / 設計自動化 / VLSI設計技術 … More Except Principal Investigator セキュリティ / LSI設計 / ＳＡＴ / ハードウェアセキュリティ / 論理合成 / SAT(充足可能性判定問題) / SAT / 論理暗号化 / テストパタン生成 / システムレベル検証 / システムLSI / 悪意ある攻撃 / 人為的な誤り / LSI設計フロー / ディペンダブル / 電子マネー / ICカード / 社会情報基盤 / LSIテスト / LSIアーキテクチャ / ディペンダブルLSI Less

Design technology for detecting IP core piracyPrincipal Investigator
- Principal Investigator
  
  吉村正義
- Project Period (FY)
  2021 – 2024
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Kyoto Sangyo University
Developing robust algorithms for logic encryption protecting against piracy of logic IP
- Principal Investigator
  
  Matsunaga Yusuke
- Project Period (FY)
  2018 – 2020
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Kyushu University
Research on LSI design methods to identify Trojan circuits in IP coresPrincipal Investigator
- Principal Investigator
  
  Yoshimura Masayoshi
- Project Period (FY)
  2018 – 2022
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Kyoto Sangyo University
Study on LSI design technology to detect Trojan circuit inserted during manufacturing processPrincipal Investigator
- Principal Investigator
  
  YOSHIMURA Masayoshi
- Project Period (FY)
  2015 – 2017
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system
- Research Institution
  Kyoto Sangyo University
Study on LSI design methods for security and testabilityPrincipal Investigator
- Principal Investigator
  
  YOSHIMURA Masayoshi
- Project Period (FY)
  2013 – 2014
- Research Category
  
  Grant-in-Aid for Challenging Exploratory Research
- Research Field
  
  Computer system
- Research Institution
  Kyoto Sangyo University
  Kyushu University
Model abstraction for accelerating TLM verification and test pattern generation
- Principal Investigator
  
  MATSUNAGA Yusuke
- Project Period (FY)
  2008 – 2010
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Kyushu University
A study of LSI design method with balance security and testabilityPrincipal Investigator
- Principal Investigator
  
  YOSHIMURA Masayoshi
- Project Period (FY)
  2008 – 2010
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Kyushu University
Research on Design Methodology of Dependable LSI Loading Value and Trust
- Principal Investigator
  
  YASUURA Hiroto
- Project Period (FY)
  2007 – 2009
- Research Category
  
  Grant-in-Aid for Scientific Research (A)
- Research Field
  
  Computer system/Network
- Research Institution
  Kyushu University

[Journal Article] CRLock: A SAT and FALL Attacks Resistant Logic Locking Method for Controller at Register Transfer Level2024
- Author(s)
  YOSHIMURA Masayoshi、TSUJIKAWA Atsuya、HOSOKAWA Toshinori
- Journal Title
  
  IEICE Trans. Fundamentals
  
  Volume: E107.A Issue: 3 Pages: 583-591
- DOI
  10.1587/transfun.2023VLP0018
- ISSN
  0916-8508, 1745-1337
- Year and Date
  2024-03-01
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21K11817
[Journal Article] A Test Register Assignment Method Based on Controller Augmentation to Reduce the Number of Test Patterns2018
- Author(s)
  Toshinori Hosokawa, Hiroshi Yamazaki, Shun Takeda, Masayoshi Yoshimura
- Journal Title
  
  2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)
  
  Volume: 24 Pages: 228-231
- DOI
  10.1109/iolts.2018.8474097
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18K11228
[Journal Article] A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification2018
- Author(s)
  Toshinori Hosokawa, Morito Niseki, Masayoshi Yoshimura, Hiroshi Yamazaki, Masayuki Arai, Hiroyuki Yotsuyanagi, Masaki Hashizume
- Journal Title
  
  2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)
  
  Volume: 24 Pages: 43-46
- DOI
  10.1109/iolts.2018.8474268
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18K11228
[Journal Article] A Capture Safe Static Test Compaction Method Based on Don't Cares2018
- Author(s)
  Sayuri Ochi, Hiroshi Yamazaki, Toshinori Hosokawa, Masayoshi Yoshimura
- Journal Title
  
  2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)
  
  Volume: 24 Pages: 195-200
- DOI
  10.1109/iolts.2018.8474080
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18K11228
[Journal Article] A Don't Care Filling Method for Low Capture Power based on Correlation of FF Transitions Using SAT2017
- Author(s)
  Masayoshi YOSHIMURA, Yoshiyasu TAKAHASHI, Hiroshi YAMAZAKI, Toshinori HOSOKAWA
- Journal Title
  
  IEICE Trans. Fundamentals
  
  Volume: E100.A Issue: 12 Pages: 2824-2833
- DOI
  10.1587/transfun.E100.A.2824
- NAID
  130006236532
- ISSN
  0916-8508, 1745-1337
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-15K00086
[Journal Article] A Test Compaction Oriented Don't Care Identification Method Based on X-bit Distribution2013
- Author(s)
  Hiroshi Yamazaki, Motohiro Wakazono, Toshinori Hosokawa, and Masayoshi Yoshimura
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: E96.D Issue: 9 Pages: 1994-2002
- DOI
  10.1587/transinf.E96.D.1994
- NAID
  130003370988
- ISSN
  0916-8532, 1745-1361
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-25540020
[Journal Article] Efficient Fault Simulation Algorithms for Analyzing Soft Error Propagation in Sequential Circuits2013
- Author(s)
  Taiga Takata, Masayoshi Yoshimura, and Yusuke Matsunaga
- Journal Title
  
  IPSJ Transactions on System LSI Design Methodology
  
  Volume: 6 Issue: 0 Pages: 127-134
- DOI
  10.2197/ipsjtsldm.6.127
- NAID
  130003369396
- ISSN
  1882-6687
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-25540020
[Journal Article] マルチサイクルキャプチャテストを用いたフルスキャン設計回路の縮退故障テスト生成2008
- Author(s)
  大森悠翔, 小河宏志, 細川利典, 吉村正義, 山崎浩二
- Journal Title
  
  電子情報通信学会技術研究報告 DC2007-71 107(482)
  
  Pages: 19-24
- NAID
  110006935635
- Data Source
  KAKENHI-PROJECT-19200004
[Journal Article] Nハミング距離テストパターン圧縮に基づくテストパターン数削減指向テスト.ポイント挿入法2008
- Author(s)
  齊藤善洋, 湯本仁高, 細川利典, 吉村正義
- Journal Title
  
  第58回FTC研究会 (in press)
- Data Source
  KAKENHI-PROJECT-19200004
[Journal Article] マルチサイクルキャプチャテストを用いたフルスキャン設計回路のテスト生成2008
- Author(s)
  大森悠翔, 小河宏志, 細川利典, 吉村正義, 山崎浩二
- Journal Title
  
  第58回FTC研究会 (in press)
- Data Source
  KAKENHI-PROJECT-19200004
[Journal Article] スキャンパス攻撃を考慮した暗号LSIのテスタビリティ評価2008
- Author(s)
  伊藤侑磨, 吉村正義, 安浦寛人
- Journal Title
  
  電子情報通信学会技術研究報告DC2007-76 107(482)
  
  Pages: 57-62
- NAID
  110006935641
- Data Source
  KAKENHI-PROJECT-19200004
[Journal Article] 非順序式バックトラック手法を用いたテストパタン生成における矛盾の解析2007
- Author(s)
  吉村正義, 松永裕介
- Journal Title
  
  DAシンポジウム2007 2007(7)
  
  Pages: 211-214
- Data Source
  KAKENHI-PROJECT-19200004
[Presentation] An Evaluation of a Testability Measure for State Assignment to Estimate Transition Fault Coverage for Controllers2023
- Author(s)
  Toshinori Hosokawa; Kyohei Iizuka; Masayoshi Yoshimura
- Organizer
  2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-21K11817
[Presentation] A Block Partitioning Method for Region Exhaustive Test to Reduce the Number of Test Patterns and Improve Gate Exhaustive Fault Coverage2023
- Author(s)
  Momona Mizota; Toshinori Hosokawa; Masayoshi Yoshimura; Masayuki Arai
- Organizer
  2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-21K11817
[Presentation] An Evaluation of Estimated Field Random Testability for Data Paths at Register Transfer Level Using Status Signal Sequences Based on k-Consecutive State Transitions for Field Testing2023
- Author(s)
  Yudai Toyooka; Haruki Watanabe; Toshinori Hosokawa; Masayoshi Yoshimura
- Organizer
  2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-21K11817
[Presentation] CRLock: A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level2022
- Author(s)
  Masayoshi Yoshimura, Atsuya Tsujikawa, Hiroshi Yamazaki, and Toshinori Hosokawa
- Organizer
  2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] CRLock: A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level2022
- Author(s)
  Masayoshi Yoshimura, Atsuya Tsujikawa, Hiroshi Yamazaki, and Toshinori Hosokawa
- Organizer
  2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-21K11817
[Presentation] 論理故障テスト並列化のための制御信号のドントケア割当て法2022
- Author(s)
  徐　浩豊, 細川利典, 山崎紘史, 新井雅之, 吉村正義
- Organizer
  ETNET2022
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] 無効状態を含んだコントローラの遷移故障検出率向上指向状態割当て法2022
- Author(s)
  飯塚恭平, 細川利典, 山崎紘史, 吉村正義
- Organizer
  ディペンダブルコンピューティング研究会
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] レジスタ転送レベルにおける非スキャンベースフィールドテスタビリティに基づく制御信号のドントケア割当て法2021
- Author(s)
  飯塚恭平・細川利典・山崎紘史・吉村正義
- Organizer
  ディペンダブルコンピューティング研究会
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level2021
- Author(s)
  Atsuya Tsujikawa, Masayoshi Yoshimura and Toshinori Hosokawa
- Organizer
  IEEE The Workshop on RTL and High Level Testing 2021
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-21K11817
[Presentation] 低消費電力指向多重目標故障テスト生成法2021
- Author(s)
  三浦　怜, 細川利典, 山崎紘史, 吉村正義, 新井雅之
- Organizer
  第6回 Winter Workshop on Safety
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] An Additional State Transition Insertion Method to Improve Transition Fault Coverage for Controllers2021
- Author(s)
  Kyohei Iizuka, Toshinori Hosokawa, Hiroshi Yamazaki and Masayoshi Yoshimura
- Organizer
  IEEE The Workshop on RTL and High Level Testing 2021
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] RTLにおけるSFLL-hdに基づいた論理暗号化手法2021
- Author(s)
  野口葉平, 吉村正義, 辻川敦也, 細川利典
- Organizer
  ディペンダブルコンピューティング研究会
- Data Source
  KAKENHI-PROJECT-21K11817
[Presentation] RTLハードウェア要素のテストスケジューリング情報を用いた多重目標故障テスト生成法2021
- Author(s)
  浅見竜輝・細川利典・山崎紘史・吉村正義・新井雅之
- Organizer
  ディペンダブルコンピューティング研究会
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] レジスタ転送レベルにおけるアンチSATに基づく論理暗号化法2021
- Author(s)
  辻川敦也・細川利典・吉村正義
- Organizer
  ETNET2021
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] コントローラの遷移故障検出率向上のためのコントローラ拡大法2021
- Author(s)
  飯塚恭平・細川利典・山崎紘史・吉村正義
- Organizer
  ETNET2021
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] レジスタ転送レベルにおけるSAT攻撃とFALL攻撃に耐性のある論理暗号化手法2021
- Author(s)
  辻川敦也, 細川利典, 吉村正義
- Organizer
  第6回 Winter Workshop on Safety
- Data Source
  KAKENHI-PROJECT-21K11817
[Presentation] A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the Number of Test Patterns Using Partial MaxSAT2020
- Author(s)
  Ryuki Asami, Toshinori Hosokawa, Masayoshi Yoshimura and Masayuki Arai
- Organizer
  2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] A Low Capture Power Oriented X-Identification-Filling Co-Optimization Method2020
- Author(s)
  Toshinori HOSOKAWA, Kenichiro MISAWA, Hiroshi YAMAZAKI, Masayoshi YOSHIMURA, Masayuki ARAI
- Organizer
  2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] テストパターン数削減のためのゲート網羅故障の多重目標故障テスト生成法2020
- Author(s)
  浅見竜輝・細川利典・吉村正義・新井雅之
- Organizer
  SWoPP2020
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] 機能等価な有限状態機械生成に基づく面積削減指向コントローラ拡大法2020
- Author(s)
  辻川敦也・細川利典・吉村正義
- Organizer
  SWoPP2020
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] A State Assignment Method to Improve Transition Fault Coverage for Controllers2019
- Author(s)
  Masayoshi Yoshimura, Yuki Takeuchi, Hiroshi Yamazaki and Toshinori Hosokawa
- Organizer
  2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] An efficient SAT-attack algorithm against logic encryption2019
- Author(s)
  Yusuke Matsunaga, Masayoshi Yoshimura
- Organizer
  IOLTS
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11219
[Presentation] 論理暗号化に対する効率的なSAT攻撃アルゴリズムの評価2019
- Author(s)
  松永　裕介，　吉村　正義
- Organizer
  電子情報通信学会VLD研究会
- Data Source
  KAKENHI-PROJECT-18K11219
[Presentation] An Efficient SAT-Attack Algorithm Against Logic Encryption2019
- Author(s)
  Yusuke Matsunaga and Masayoshi Yoshimura
- Organizer
  IOLTS2019
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11219
[Presentation] A Don't Care Identification-Filling Co-Optimization Method for Low Capture Power Testing Using Partial MaxSAT2019
- Author(s)
  Kenichiro Misawa, Toshinori Hosokawa, Hiroshi Yamazaki, Masayoshi Yoshimura, and Masayuki Arai
- Organizer
  The 20th Workshop on RTL and High-Level Testing (WRTLT’19)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] 論理暗号化に対するSAT攻撃アルゴリズムの高速化2019
- Author(s)
  松永　裕介，　吉村　正義
- Organizer
  FTC研究会
- Data Source
  KAKENHI-PROJECT-18K11219
[Presentation] A Controller Augmentation Method to Improve Transition Fault Coverage for RTL Data-Paths2019
- Author(s)
  Yuki Takeuchi, Toshinori Hosokawa, Hiroshi Yamazaki, and Masayoshi Yoshimura
- Organizer
  2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] A State Assignment Method to Improve Transition Fault Coverage for Controllers2019
- Author(s)
  Toshinori Hosokawa, Hiroshi Yamazaki, Kenichiro Misawa, Masayoshi Yoshimura, Yuki Hirama, and Masavuki Arai
- Organizer
  2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] コントローラ拡大を用いた遷移故障テストパターン数削減のための演算器のテストレジスタ割当て法2018
- Author(s)
  竹内勇希, 武田俊, 細川利典, 山崎紘史, 吉村正義
- Organizer
  ディペンダブルコンピューティング研究会
- Data Source
  KAKENHI-PROJECT-15K00086
[Presentation] コントローラの遷移故障検出率向上のための状態割当て手法2018
- Author(s)
  吉村正義・竹内勇希・細川利典・山崎紘史
- Organizer
  ディペンダブルコンピューティング研究会
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] A design for testability method to improve transition fault coverage using controller augmentation at register transfer level2018
- Author(s)
  Yuki Takeuchi, Toshinori Hosokawa, Hiroshi Yamazaki , Masayoshi Yoshimura
- Organizer
  The Nineteenth Workshop on RTL and High Level Testing
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] A Secure Design Method to Detect for Trojan Circuit inserted in Manufacturing Process2018
- Author(s)
  Yoshinobu Okuda, Masayoshi Yoshimura, Kohei Ohyama, and Toshinori Hosokawa
- Organizer
  DUHDe 2018 ― 5th Workshop on Design Automation for Understanding Hardware Designs
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K00086
[Presentation] レジスタ転送レベルにおけるコントローラ拡大を用いた遷移故障検出率向上のためのテスト容易化設計2018
- Author(s)
  竹内勇希、細川利典、山崎紘史、吉村正義
- Organizer
  DAシンポジウム2018
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] 論理暗号化に対するSAT攻撃の効率的なアルゴリズムについて2018
- Author(s)
  松永　裕介，　吉村　正義
- Organizer
  電子情報通信学会VLD研究会（デザインガイア）
- Data Source
  KAKENHI-PROJECT-18K11219
[Presentation] A Test Register Assignment Method to Reduce the Number of Test Patterns Using Controller Augmentation2018
- Author(s)
  Shun Takeda, Toshinori Hosokawa, Hiroshi Yamazaki, and Masayoshi Yoshimura
- Organizer
  DUHDe 2018 ― 5th Workshop on Design Automation for Understanding Hardware Designs
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K00086
[Presentation] キャプチャセーフテストベクトルの故障伝搬経路を模倣した低消費電力指向ドントケア判定法2018
- Author(s)
  三澤健一郎・細川利典・山崎紘史・吉村正義
- Organizer
  ディペンダブルコンピューティング研究会
- Data Source
  KAKENHI-PROJECT-18K11228
[Presentation] A Hardware Trojan Circuit Detection Method Using Activation Sequence Generations2017
- Author(s)
  Masayoshi Yoshimura(Kyoto Sangyo University), Tomohiro Bouyashiki, and Toshinori Hosokawa(Nihon University)
- Organizer
  The 22nd IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2017)
- Place of Presentation
  Christchurch, New Zealand
- Year and Date
  2017-01-22
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K00086
[Presentation] Controller augmentation and test point insertion at RTL for concurrent operational unit testing2017
- Author(s)
  Toshinori Hosokawa, Shun Takeda, Hiroshi Yamazaki, and Masayoshi Yoshimura
- Organizer
  2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K00086
[Presentation] A Low Power Oriented Static Test Compaction Method Based on Don't Care Bits2017
- Author(s)
  Sayuri Ochi, Hiroshi Yamazaki, Toshinori Hosokawa, Masayoshi Yoshimura
- Organizer
  IEEE The Eighteenth Workshop on RTLT and High Level Testing 2017
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K00086
[Presentation] 到達不能状態を用いたSATベース順序回路のテスト不能故障判定法2017
- Author(s)
  二関森人・細川利典（日大）・吉村正義（京都産大）・新井雅之（日大）・四柳浩之・橋爪正樹（徳島大）
- Organizer
  ディペンダブルコンピューティング研究会
- Place of Presentation
  東京都・機械振興会館
- Year and Date
  2017-02-21
- Data Source
  KAKENHI-PROJECT-15K00086
[Presentation] 製造過程でのトロイ回路混入を検知する設計手法2017
- Author(s)
  奥田良宣, 吉村正義, 大山浩平
- Organizer
  デザインガイア2017
- Data Source
  KAKENHI-PROJECT-15K00086
[Presentation] コントローラ拡大を用いたレジスタ転送レベルにおけるテストパターン数削減のためのハードウェア要素のテストレジスタ割当て法2017
- Author(s)
  武田俊, 細川利典, 山崎紘史, 吉村正義
- Organizer
  デザインガイア2017
- Data Source
  KAKENHI-PROJECT-15K00086
[Presentation] トロイ回路を検知する回路の挿入箇所探索手法2017
- Author(s)
  奥田良宣，吉村正義（京都産大）
- Organizer
  第9回LSIテストセミナー
- Place of Presentation
  福岡市・筑紫会館
- Year and Date
  2017-03-09
- Data Source
  KAKENHI-PROJECT-15K00086
[Presentation] ドントケアを用いたキャプチャセーフテスト集合の静的テスト圧縮法2017
- Author(s)
  越智小百合, 山崎紘史, 細川利典, 吉村正義
- Organizer
  DAシンポジウム2017
- Data Source
  KAKENHI-PROJECT-15K00086
[Presentation] IPコアの論理暗号化法の復号化鍵数の評価2017
- Author(s)
  橋立英実, 細川利典, 吉村正義
- Organizer
  デザインガイア2017
- Data Source
  KAKENHI-PROJECT-15K00086
[Presentation] フリップフロップ組合せの状態正当化による到達不能状態を用いた順序回路のテスト不能故障判定法2017
- Author(s)
  二関森人, 細川利典, 吉村正義, 山崎紘史, 新井雅之, 四柳浩之, 橋爪正樹
- Organizer
  DAシンポジウム2017
- Data Source
  KAKENHI-PROJECT-15K00086
[Presentation] A Sequentially Untestable Fault Identification Method Based on State Cube Justification2017
- Author(s)
  Morito Niseki, Toshinori Hosokawa, Hiroshi Yamazaki, Masayuki Arai, Masayoshi Yoshimura, Hiroyuki Yotsuyanagi and Masaki Hashizume
- Organizer
  IEEE The Eighteenth Workshop on RTLT and High Level Testing 2017
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K00086
[Presentation] トロイ回路を検知する回路の考察2016
- Author(s)
  大山浩平, 吉村正義
- Organizer
  第8回LSIテストセミナー
- Place of Presentation
  電気ビル共創館(福岡県福岡市)
- Year and Date
  2016-03-02
- Data Source
  KAKENHI-PROJECT-15K00086
[Presentation] A Design for Testability Method at RTL for Concurrent Operational Unit Testing2016
- Author(s)
  Shun Takeda, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon University) and Masayoshi Yoshimura (Kyoto Sangyo University)
- Organizer
  IEEE The Seventeenth Workshop on RTL and High Level Testing
- Place of Presentation
  Aki Grand Hotel, Hiroshima, Japan
- Year and Date
  2016-11-24
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K00086
[Presentation] A Don’t Care Filling Method to Reduce Capture Power based on Correlation of FF Transitions2015
- Author(s)
  Masayoshi Yoshimura, Yoshiyasu Takahashi, Hiroshi Yamazaki and Toshinori Hosokawa
- Organizer
  24th IEEE Asian Test Symposium 2015
- Place of Presentation
  Indian Institute of Technology Bombay, Bombay, India
- Year and Date
  2015-11-23
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K00086
[Presentation] 静的テスト圧縮のための多重目標故障テスト生成を用いたMバイNアルゴリズム2015
- Author(s)
  原侑也, 山崎紘史, 細川利典, 吉村正義
- Organizer
  デザインガイア2015
- Place of Presentation
  長崎県勤労福祉会館(長崎県長崎市)
- Year and Date
  2015-12-03
- Data Source
  KAKENHI-PROJECT-15K00086
[Presentation] BASTにおけるスキャンスライスに基づくテストデータ削減法2015
- Author(s)
  錦織誠, 山崎紘史, 細川利典, 新井雅之, 吉村正義
- Organizer
  ディペンダブルコンピューティング研究会
- Place of Presentation
  機械振興会館, 東京都
- Year and Date
  2015-06-16
- Data Source
  KAKENHI-PROJECT-15K00086
[Presentation] VLSI設計工程時における未遷移信号線情報に基づいたトロイ回路検出法2015
- Author(s)
  坊屋鋪知拓，細川利典，吉村正義
- Organizer
  DAシンポジウム2015
- Place of Presentation
  山代温泉　ゆのくに天祥(石川県加賀市)
- Year and Date
  2015-08-28
- Data Source
  KAKENHI-PROJECT-15K00086
[Presentation] A Sequence Generation Method to detect Hardware Trojan Circuits2015
- Author(s)
  Masayoshi Yoshimura, Tomohiro Bouyashiki and Toshinori Hosokawa
- Organizer
  16th IEEE Workshop on RTL and High Level Testing 2015
- Place of Presentation
  Indian Institute of Technology Bombay, Bombay, India
- Year and Date
  2015-11-25
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K00086
[Presentation] スキャンベース攻撃を考慮した暗号LSIのテスト手法2015
- Author(s)
  吉村正義, 西間木淳, 細川利典
- Organizer
  ディペンダブルコンピューティング研究会
- Place of Presentation
  機械振興会館，東京
- Year and Date
  2015-02-12
- Data Source
  KAKENHI-PROJECT-25540020
[Presentation] A Multi Cycle Capture Test Generation Method for Low Capture Power Dissipation2015
- Author(s)
  Hiroshi Yamazaki, Jun Nishimaki, Toshinori Hosokawa and Masayoshi Yoshimura
- Organizer
  Designing with Uncertainty - Opportunities & Challenges
- Place of Presentation
  Grenoble, France
- Year and Date
  2015-03-13
- Data Source
  KAKENHI-PROJECT-25540020
[Presentation] BASTにおけるシフトデータ量削減法2014
- Author(s)
  田中まりか・山崎紘史・細川利典（日大）・吉村正義（九大）・新井雅之（日大）
- Organizer
  ディペンダブルコンピューティング研究会
- Place of Presentation
  東京・機械振興会館
- Data Source
  KAKENHI-PROJECT-25540020
[Presentation] マルチサイクルキャプチャテスト生成を用いた低消費電力指向遷移故障テスト生成法2014
- Author(s)
  山崎紘史・川連裕斗・西間木　淳・平井淳士・細川利典（日大）・吉村正義（九大）・山崎浩二（明大）
- Organizer
  ディペンダブルコンピューティング研究会
- Place of Presentation
  東京・機械振興会館
- Data Source
  KAKENHI-PROJECT-25540020
[Presentation] SATを用いた低キャプチャ電力指向ドントケア割当て法2014
- Author(s)
  高橋慶安・山崎紘史・細川利典（日大）・吉村正義（九大）
- Organizer
  ディペンダブルコンピューティング研究会
- Place of Presentation
  東京・機械振興会館
- Data Source
  KAKENHI-PROJECT-25540020
[Presentation] A Smart Trojan Circuit and Smart Attack Method in AES Encryption Circuits2013
- Author(s)
  Masayoshi Yoshimura, Amy Ogita and Toshinori Hosokawa
- Organizer
  16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems
- Place of Presentation
  New York City, NY, USA
- Data Source
  KAKENHI-PROJECT-25540020
[Presentation] BASTにおけるテストデータ量削減のためのインバータブロック構成法2013
- Author(s)
  田中まりか・山崎紘史・細川利典（日大）・吉村正義（九大）・新井雅之（日大）・中尾教伸（読売理工医療福祉専門学校）
- Organizer
  デザインガイア2013
- Place of Presentation
  鹿児島県文化センター
- Data Source
  KAKENHI-PROJECT-25540020
[Presentation] An SER Analysis Method for Sequential Circuits2011
- Author(s)
  Masayoshi Yoshimura, et al
- Organizer
  7th Workshop on Silicon Errors in Logic-System Effects
- Place of Presentation
  アメリカ
- Year and Date
  2011-03-30
- Data Source
  KAKENHI-PROJECT-20700050
[Presentation] 順序回路のソフトエラー耐性評価手法の高速化2010
- Author(s)
  吉村正義, et al
- Organizer
  DAシンポジウム2010
- Place of Presentation
  ホテル日航豊橋(愛知県)
- Year and Date
  2010-09-03
- Data Source
  KAKENHI-PROJECT-20700050
[Presentation] An estimation of encryption LSI testability against scan-based attack2010
- Author(s)
  Masayoshi Yoshimura, et al
- Organizer
  International Symposium on Communications and Information Technologies 2010
- Place of Presentation
  明治大学(東京都)
- Year and Date
  2010-10-28
- Data Source
  KAKENHI-PROJECT-20700050
[Presentation] TMR based Error Correction Method Considering Trade-offs between Soft Error Tolerance and Area2010
- Author(s)
  Shoji Harada, Masayoshi Yoshimura, Yusuke Matsunaga
- Organizer
  International Workshop on Logic and Synthesis
- Place of Presentation
  米国カリフォルニア州
- Year and Date
  2010-06-18
- Data Source
  KAKENHI-PROJECT-20300020
[Presentation] An estimati on of encryption LSI testability ag ainst scan-based attack2010
- Author(s)
  Masayoshi Yoshimura
- Organizer
  An estima tion of encryption LSI testability a gainst scan-based attack
- Place of Presentation
  Tokyo, Japan.
- Year and Date
  2010-10-28
- Data Source
  KAKENHI-PROJECT-20700050
[Presentation] Evaluation of Transition Untestable Faults Using a Multi-Cycle Capture Test Generation Method2010
- Author(s)
  Masayoshi Yoshimura, et al
- Organizer
  13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
- Place of Presentation
  オーストリア
- Year and Date
  2010-04-14
- Data Source
  KAKENHI-PROJECT-20700050
[Presentation] ディペンダブルVLSI設計技術への挑戦2009
- Author(s)
  松永裕介, 安浦寛人, 馬場謙介, 吉村正義, 佐藤寿倫, 杉原真
- Organizer
  電子情報通信学会全国大会
- Place of Presentation
  愛媛大学(愛媛県松山市)
- Year and Date
  2009-03-18
- Data Source
  KAKENHI-PROJECT-19200004
[Presentation] A Test Generation Method for Datapath Circuits Using Functional Time Expansion Models2008
- Author(s)
  Kazuya Sugiki, Toshinori Hosokawa, Masayoshi Yoshimura
- Organizer
  The 9th Workshop on RTL and High Level Testing
- Place of Presentation
  Sapporo, Japan
- Year and Date
  2008-11-28
- Data Source
  KAKENHI-PROJECT-19200004
[Presentation] Design For Testability Methods against Scan based Attacks2008
- Author(s)
  Masayoshi YOSHIMURA
- Organizer
  Joint Seminar on Advanced LSI Test Technology
- Place of Presentation
  Fukuoka, Japan.
- Year and Date
  2008-12-01
- Data Source
  KAKENHI-PROJECT-20700050
[Presentation] Design For Testability Methods against Scan based Attacks2008
- Author(s)
  Masayoshi YOSHIMURA
- Organizer
  Joint Seminar on Advanced LSI Test Technology
- Place of Presentation
  Fukuoka, Japan
- Year and Date
  2008-11-01
- Data Source
  KAKENHI-PROJECT-20700050
[Presentation] A Bit Flipping Reduction Method for Pseudo Random Patterns Using Don't Care Identification on BAST Architecture2008
- Author(s)
  Ling Ling Wan, Motohiro Wakazono, Toshinori Hosokawa, Masayoshi Yoshimura
- Organizer
  The 9th Workshop on RTL and High Level Testing
- Place of Presentation
  Sapporo, Japan
- Year and Date
  2008-11-28
- Data Source
  KAKENHI-PROJECT-19200004
[Presentation] スキャンパス攻撃を考慮した暗号LSIのテスタビリティ評価2008
- Author(s)
  伊藤侑磨, 吉村正義, 安浦寛人
- Organizer
  ディペンダブルコンピューティング研究会
- Place of Presentation
  機械振興会館(東京)
- Year and Date
  2008-02-08
- Data Source
  KAKENHI-PROJECT-19200004

1. MATSUNAGA Yusuke (00336059)

# of Collaborated Projects: 3 results

# of Collaborated Products: 8 results
2. BABA Kensuke (70380681)

# of Collaborated Projects: 2 results

# of Collaborated Products: 1 results
3. 細川利典 (40373005)

# of Collaborated Projects: 2 results

# of Collaborated Products: 31 results
4. YASUURA Hiroto (80135540)

# of Collaborated Projects: 1 results

# of Collaborated Products: 3 results
5. SATO Toshinori (00322298)

# of Collaborated Projects: 1 results

# of Collaborated Products: 1 results
6. INOUE Sozo (90346825)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
7. IKEDA Daisuke (00294992)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
8. ISHIDA Koji (90467879)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
9. UDDIN Mohammad Mesbah (70543338)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
10. INENAGA Shunsuke (60448404)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results

YOSHIMURA Masayoshi 吉村 正義

吉村 正義 ヨシムラ マサヨシ

Research Projects

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Co-Researchers

Design technology for detecting IP core piracyPrincipal Investigator

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Developing robust algorithms for logic encryption protecting against piracy of logic IP

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Research on LSI design methods to identify Trojan circuits in IP coresPrincipal Investigator

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Study on LSI design technology to detect Trojan circuit inserted during manufacturing processPrincipal Investigator

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Study on LSI design methods for security and testabilityPrincipal Investigator

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Model abstraction for accelerating TLM verification and test pattern generation

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A study of LSI design method with balance security and testabilityPrincipal Investigator

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Research on Design Methodology of Dependable LSI Loading Value and Trust

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[Journal Article] CRLock: A SAT and FALL Attacks Resistant Logic Locking Method for Controller at Register Transfer Level2024

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[Journal Article] A Test Register Assignment Method Based on Controller Augmentation to Reduce the Number of Test Patterns2018

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[Journal Article] A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification2018

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[Journal Article] A Capture Safe Static Test Compaction Method Based on Don't Cares2018

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[Journal Article] A Don&apos;t Care Filling Method for Low Capture Power based on Correlation of FF Transitions Using SAT2017

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YOSHIMURA Masayoshi 吉村正義

吉村正義ヨシムラマサヨシ

[Journal Article] A Don't Care Filling Method for Low Capture Power based on Correlation of FF Transitions Using SAT2017

[Journal Article] スキャンパス攻撃を考慮した暗号LSIのテスタビリティ評価2008