Kito Nobutaka 鬼頭信貴

… Alternative Names

KITO Nobutaka 鬼頭信貴

Less

Researcher Number	90630997
Other IDs	https://orcid.org/0000-0003-2894-8947
Affiliation (Current)	2024: 中京大学, 工学部, 准教授
Affiliation (based on the past Project Information) *help	2021 – 2022: 中京大学, 工学部, 准教授 2013 – 2020: 中京大学, 工学部, 講師
Review Section/Research Field	Principal Investigator Basic Section 60040:Computer system-related / Computer system
Keywords	Principal Investigator 単一磁束量子回路 / 設計自動化 / 超伝導 / 算術演算回路 / 超伝導回路 / 論理設計 / RSFQ回路 / テクノロジマッピング / パルス論理 / 超伝導ディジタル回路 … More / SFQ回路 / 自動配置配線 / 配線長 / 自動配置 / 自動配線 / レイアウト設計 / 配線遅延 / 超伝導単一磁束量子回路 / LSIのテスト / 浮動小数点 / テスト容易 / 高信頼 / 加算回路 / 乗算回路 / オンライン誤り検出 / VLSIのテスト Less

超伝導単一磁束量子回路向け新機軸算術演算回路とその設計自動化の探求Principal Investigator
- Principal Investigator
  
  鬼頭信貴
- Project Period (FY)
  2022 – 2024
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Chukyo University
Study on design methods for superconducting digital circuit devices utilizing pulse logicPrincipal Investigator
- Principal Investigator
  
  Kito Nobutaka
- Project Period (FY)
  2019 – 2021
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Chukyo University
Research on automatic layout methods considering wire delay for superconductive digital circuitsPrincipal Investigator
- Principal Investigator
  
  Kito Nobutaka
- Project Period (FY)
  2016 – 2018
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Computer system
- Research Institution
  Chukyo University
Research on easily self-testable arithmetic circuits with online error detection capabilityPrincipal Investigator
- Principal Investigator
  
  KITO Nobutaka
- Project Period (FY)
  2013 – 2015
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Computer system
- Research Institution
  Chukyo University

All 2023 2022 2021 2020 2019 2018 2017 2016 2015 2014 2013

All Journal Article Presentation

[Journal Article] Technology Mapping With Clockless Gates for Logic Stage Reduction of RSFQ Logic Circuits2023
- Author(s)
  Kito Nobutaka、Kawaguchi Takahiro、Takagi Kazuyoshi、Takagi Naofumi
- Journal Title
  
  IEEE Transactions on Applied Superconductivity
  
  Volume: 33 Issue: 5 Pages: 1-5
- DOI
  10.1109/tasc.2023.3245049
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22K11961
[Journal Article] Logic-Depth-Aware Technology Mapping Method for RSFQ Logic Circuits With Special RSFQ Gates2022
- Author(s)
  KITO, Nobutaka、TAKAGI, Kazuyoshi、TAKAGI, Naofumi
- Journal Title
  
  IEEE Transactions on Applied Superconductivity
  
  Volume: 32 Issue: 4 Pages: 1-5
- DOI
  10.1109/tasc.2021.3129719
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19K11888, KAKENHI-PROJECT-18H05211
[Journal Article] An RSFQ flexible-precision multiplier utilizing bit-level processing2021
- Author(s)
  KITO, Nobutaka、TAKAGI, Kazuyoshi
- Journal Title
  
  Journal of Physics: Conference Series
  
  Volume: 1975 Issue: 1 Pages: 012025-012025
- DOI
  10.1088/1742-6596/1975/1/012025
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-19K11888
[Journal Article] A Timing Fault Model and an Efficient Timing Fault Simulation Method for Rapid Single-Flux-Quantum Logic Circuits2021
- Author(s)
  NAKAMURA, Shogo、TAKAGI, Kazuyoshi、KITO, Nobutaka、TAKAGI, Naofumi
- Journal Title
  
  Journal of Physics: Conference Series
  
  Volume: 1975 Issue: 1 Pages: 012026-012026
- DOI
  10.1088/1742-6596/1975/1/012026
- Peer Reviewed / Open Access / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19K11888, KAKENHI-PROJECT-18H05211
[Journal Article] Conversion Method of Netlists Consisting of Conventional Logic Gates to RSFQ Logic Circuits Utilizing Special RSFQ Gates2020
- Author(s)
  Kito Nobutaka、Takagi Kazuyoshi、Takagi Naofumi
- Journal Title
  
  IEEE Transactions on Applied Superconductivity
  
  Volume: 30 Issue: 7 Pages: 1-6
- DOI
  10.1109/tasc.2020.3012474
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19K11888, KAKENHI-PROJECT-18H05211
[Journal Article] Logic simulation tool for RSFQ circuits accepting arrivals of multiple pulses in a clock period2020
- Author(s)
  Kito Nobutaka、Udatsu Shohei、Takagi Kazuyoshi
- Journal Title
  
  Journal of Physics: Conference Series
  
  Volume: 1590 Issue: 1 Pages: 012041-012041
- DOI
  10.1088/1742-6596/1590/1/012041
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-19K11888, KAKENHI-PROJECT-18K11213
[Journal Article] Logic Simulation Tool for RSFQ Circuits Accepting Arrivals of Multiple Pulses in a Clock Period2020
- Author(s)
  Nobutaka Kito, Shohei Udatsu, and Kazuyoshi Takagi
- Journal Title
  
  Journal of Physics: Conference Series
  
  Volume: －
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-19K11888
[Journal Article] Rapid Single-Flux-Quantum Truncated Multiplier Based on Bit-Level Processing2019
- Author(s)
  Nobutaka Kito、Ryota Odaka、Kazuyoshi Takagi
- Journal Title
  
  IEICE Transactions on Electronics
  
  Volume: E102-C
- NAID
  130007671355
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-16K16029
[Journal Article] A Fast Wire-Routing Method and an Automatic Layout Tool for RSFQ Digital Circuits Considering Wire-Length Matching2018
- Author(s)
  Kito Nobutaka、Takagi Kazuyoshi、Takagi Naofumi
- Journal Title
  
  IEEE Transactions on Applied Superconductivity
  
  Volume: 28 Issue: 4 Pages: 1-5
- DOI
  10.1109/tasc.2018.2793203
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-15K00075, KAKENHI-PROJECT-16K16029
[Journal Article] Low-Overhead Fault-Secure Parallel Prefix Adder by Carry-Bit Duplication2013
- Author(s)
  Nobutaka Kito, Naofumi Takagi
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: E96.D Issue: 9 Pages: 1962-1970
- DOI
  10.1587/transinf.E96.D.1962
- NAID
  130003370984
- ISSN
  0916-8532, 1745-1361
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-24300019, KAKENHI-PROJECT-25730033
[Presentation] Accuracy Improvement of Polynomial Computing RSFQ Circuits Based on Stochastic Computing by Partial Duplication2022
- Author(s)
  Moeka Tsuji, Nobutaka Kito
- Organizer
  35th International Symposium on Superconductivity (ISS2022)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-22K11961
[Presentation] Technology mapping with clockless gates for logic stage reduction of RSFQ logic circuits2022
- Author(s)
  Nobutaka Kito, Takahiro Kawaguchi, Kazuyoshi Takagi, Naofumi Takagi
- Organizer
  Applied Superconductivity Conference 2022 (ASC 2022)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-22K11961
[Presentation] 部分多重化によるStochastic Computingに基づく多項式演算 RSFQ 回路の精度向上2022
- Author(s)
  辻　萌佳, 鬼頭信貴
- Organizer
  電子情報通信学会ソサイエティ大会
- Data Source
  KAKENHI-PROJECT-22K11961
[Presentation] RSFQ回路のラッチ機能を活用したコンパクトな多項式計算Stochastic Computing回路の設計手法2021
- Author(s)
  和田航輝、鬼頭信貴
- Organizer
  2021年電子情報通信ソサイエティ大会
- Data Source
  KAKENHI-PROJECT-19K11888
[Presentation] RSFQ Stochastic Computing 回路のための再収斂経路を考慮した演算スケジューリング手法2021
- Author(s)
  鬼頭信貴
- Organizer
  電子情報通信学会 2021年総合大会
- Data Source
  KAKENHI-PROJECT-19K11888
[Presentation] Compact Stochastic Computing Circuits Using the Latching Function of RSFQ Circuits for Computing Polynomials2021
- Author(s)
  WADA, Koki、KITO, Nobutaka
- Organizer
  34th International Symposium on Superconductivity (ISS2021)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19K11888
[Presentation] Logic-depth-aware technology mapping method for RSFQ logic circuits with special RSFQ gates2021
- Author(s)
  KITO, Nobutaka、TAKAGI, Kazuyoshi、TAKAGI, Naofumi
- Organizer
  15th European Conference on Applied Superconductivity (EUCAS2021)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19K11888
[Presentation] ビットレベル処理を用いたRSFQ可変精度行列乗算器の検討2020
- Author(s)
  鬼頭信貴, 高木一義
- Organizer
  電子情報通信学会 2020年総合大会
- Data Source
  KAKENHI-PROJECT-19K11888
[Presentation] An RSFQ Flexible-Precision Multiplier Utilizing Bit-Level Processing2020
- Author(s)
  Nobutaka Kito and Kazuyoshi Takagi
- Organizer
  33rd International Symposium on Superconductivity (ISS2020)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19K11888
[Presentation] Rapid Single-Flux-Quantum Matrix Multiplication Circuit Utilizing Bit-Level Processing2019
- Author(s)
  Nobutaka Kito, Takuya Kumagai, and Kazuyoshi Takagi
- Organizer
  22nd Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2019)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19K11888
[Presentation] Logic Simulation Tool for RSFQ Circuits Accepting Arrivals of Multiple Pulses in a Clock Period2019
- Author(s)
  Nobutaka Kito, Shohei Udatsu, and Kazuyoshi Takagi
- Organizer
  32nd International Symposium on Superconductivity (ISS2019)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19K11888
[Presentation] Test Pattern Generation for Timing Faults in Rapid Single-Flux-Quantum Circuits2019
- Author(s)
  Kazuyoshi Takagi, Mikihiro Ono, Nobutaka Kito, and Naofumi Takagi
- Organizer
  22nd Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2019)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19K11888
[Presentation] Conversion Method of Netlists Consisting of Conventional Logic Gates to RSFQ Logic Circuits Using the Characteristics of Pulse Logic2019
- Author(s)
  Nobutaka Kito, Kazuyoshi Takagi, and Naofumi Takagi
- Organizer
  17th International Superconductive Electronics Conference (ISEC 2019)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19K11888
[Presentation] クロック周期内での複数パルス出現を考慮したRSFQ回路シミュレーション2019
- Author(s)
  宇田津祥平, 鬼頭信貴
- Organizer
  2019年電子情報通信ソサイエティ大会
- Data Source
  KAKENHI-PROJECT-19K11888
[Presentation] Stochastic Computing に基づく単一磁束量子乗算器の検討2018
- Author(s)
  小高良太, 鬼頭信貴
- Organizer
  電気・電子・情報関係学会東海支部連合大会
- Data Source
  KAKENHI-PROJECT-16K16029
[Presentation] Designs of Component Circuits for Stochastic Computing Using Rapid Single Flux Quantum Circuits2018
- Author(s)
  Nobutaka Kito, Yurie Koketsu, and Kazuyoshi Takagi
- Organizer
  21st Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2018)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16K16029
[Presentation] パルス論理の性質を活用した論理ゲートネットリストのRSFQディジタル回路向け変換2018
- Author(s)
  鬼頭信貴, 高木一義, 高木直史
- Organizer
  2018年電子情報通信ソサイエティ大会
- Data Source
  KAKENHI-PROJECT-16K16029
[Presentation] A fast wire-routing method and an automatic layout tool for RSFQ digital circuits considering wire-length matching2017
- Author(s)
  Nobutaka Kito, Kazuyoshi Takagi, and Naofumi Takagi
- Organizer
  13th European Conference on Applied Superconductivity (EUCAS2017)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16K16029
[Presentation] 配線長マッチングを考慮した自動配置によるRSFQ回路のレイアウト面積削減2017
- Author(s)
  鬼頭信貴, 高木一義, 高木直史
- Organizer
  電子情報通信学会 2017年総合大会
- Place of Presentation
  名城大学天白キャンパス(名古屋市天白区)
- Year and Date
  2017-03-22
- Data Source
  KAKENHI-PROJECT-16K16029
[Presentation] 単一磁束量子回路を用いたStochastic Computing 実現のためのStochastic Number Generatorの設計2017
- Author(s)
  纐纈百合絵, 鬼頭信貴
- Organizer
  電気・電子・情報関係学会東海支部連合大会
- Data Source
  KAKENHI-PROJECT-16K16029
[Presentation] Development of CAD Tools for SFQ Logic Circuits and Design of Data-path Circuits for SFQ Bit-slice Processors2017
- Author(s)
  Naofumi Takagi, Kazuyoshi Takagi, and Nobutaka Kito
- Organizer
  10th Superconducting SFQ VLSI Workshop (SSV 2017)
- Place of Presentation
  名古屋大学東山キャンパス(名古屋市千種区)
- Year and Date
  2017-02-20
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16K16029
[Presentation] Fast Length-Matching Routing for Rapid Single Flux Quantum Circuits2016
- Author(s)
  Nobutaka Kito, Kazuyoshi Takagi, and Naofumi Takagi
- Organizer
  20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2016)
- Place of Presentation
  京都リサーチパーク(京都市下京区)
- Year and Date
  2016-10-24
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16K16029
[Presentation] 単一磁束量子論理回路の設計検証のための論理シミュレーションツールの拡張2016
- Author(s)
  松本弦篤, 鬼頭信貴
- Organizer
  平成28年度電気・電子・情報関係学会東海支部連合大会
- Place of Presentation
  豊田工業高等専門学校(愛知県豊田市)
- Year and Date
  2016-09-12
- Data Source
  KAKENHI-PROJECT-16K16029
[Presentation] Extension of a Logic Simulation System for Simulation-Based Verification of RSFQ Logic Circuits2016
- Author(s)
  Nobutaka Kito, Gentoku Matsumoto, Kazuyoshi Takagi, and Naofumi Takagi
- Organizer
  9th Superconducting SFQ VLSI Workshop (SSV 2016)
- Place of Presentation
  横浜国立大学(横浜市保土ケ谷区)
- Year and Date
  2016-08-02
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16K16029
[Presentation] SFQディジタル回路のための配線長マッチングを考慮した高速配線法2016
- Author(s)
  鬼頭信貴, 高木一義, 高木直史
- Organizer
  電子情報通信学会 2016年電子情報通信ソサイエティ大会
- Place of Presentation
  北海道大学(札幌市北区)
- Year and Date
  2016-09-20
- Data Source
  KAKENHI-PROJECT-16K16029
[Presentation] オンライン誤り検出可能な3オペランド複素数乗算回路2015
- Author(s)
  鬼頭信貴, 吉田孝洋
- Organizer
  電子情報通信学会 2015年総合大会
- Place of Presentation
  草津市
- Year and Date
  2015-03-12
- Data Source
  KAKENHI-PROJECT-25730033
[Presentation] 部分二重化を用いたオンライン誤り検出可能な浮動小数点乗算器の設計と評価2015
- Author(s)
  鬼頭信貴, 秋元一志, 高木直史
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  奄美市
- Year and Date
  2015-03-07
- Data Source
  KAKENHI-PROJECT-25730033
[Presentation] テスト容易でオンライン誤り検出可能な桁上げ選択加算器2015
- Author(s)
  鬼頭信貴
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  長崎市
- Year and Date
  2015-12-03
- Data Source
  KAKENHI-PROJECT-25730033
[Presentation] 部分二重化を用いた微小誤りを許容するオンライン誤り検出可能な浮動小数点乗算器2014
- Author(s)
  鬼頭信貴, 秋元一志, 高木直史
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  東京都
- Year and Date
  2014-06-20
- Data Source
  KAKENHI-PROJECT-25730033
[Presentation] 剰余検査を用いたオンライン誤り検出可能な浮動小数点乗算器2013
- Author(s)
  山口大樹, 鬼頭信貴, 高木直史
- Organizer
  第69回FTC研究会
- Place of Presentation
  かんぽの宿湯田（山口県山口市）
- Data Source
  KAKENHI-PROJECT-25730033
[Presentation] 剰余検査によるオンライン誤り検出可能な浮動小数点乗算器2013
- Author(s)
  山口大樹, 鬼頭信貴, 高木直史
- Organizer
  DAシンポジウム2013
- Place of Presentation
  下呂温泉水明館（岐阜県下呂市）
- Data Source
  KAKENHI-PROJECT-25730033

1. 高木一義

# of Collaborated Projects: 0 results

# of Collaborated Products: 1 results

Kito Nobutaka 鬼頭 信貴

KITO Nobutaka 鬼頭 信貴

Research Projects

Research Products

Co-Researchers

超伝導単一磁束量子回路向け新機軸算術演算回路とその設計自動化の探求Principal Investigator

Principal Investigator

Project Period (FY)

Research Category

Review Section

Research Institution

Study on design methods for superconducting digital circuit devices utilizing pulse logicPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Review Section

Research Institution

Research on automatic layout methods considering wire delay for superconductive digital circuitsPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Research on easily self-testable arithmetic circuits with online error detection capabilityPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

[Journal Article] Technology Mapping With Clockless Gates for Logic Stage Reduction of RSFQ Logic Circuits2023

Author(s)

Journal Title

DOI

Data Source

[Journal Article] Logic-Depth-Aware Technology Mapping Method for RSFQ Logic Circuits With Special RSFQ Gates2022

Author(s)

Journal Title

DOI

Data Source

[Journal Article] An RSFQ flexible-precision multiplier utilizing bit-level processing2021

Author(s)

Journal Title

DOI

Data Source

[Journal Article] A Timing Fault Model and an Efficient Timing Fault Simulation Method for Rapid Single-Flux-Quantum Logic Circuits2021

Author(s)

Journal Title

DOI

Data Source

[Journal Article] Conversion Method of Netlists Consisting of Conventional Logic Gates to RSFQ Logic Circuits Utilizing Special RSFQ Gates2020

Author(s)

Journal Title

DOI

Data Source

[Journal Article] Logic simulation tool for RSFQ circuits accepting arrivals of multiple pulses in a clock period2020

Author(s)

Journal Title

DOI

Data Source

[Journal Article] Logic Simulation Tool for RSFQ Circuits Accepting Arrivals of Multiple Pulses in a Clock Period2020

Author(s)

Journal Title

Data Source

[Journal Article] Rapid Single-Flux-Quantum Truncated Multiplier Based on Bit-Level Processing2019

Author(s)

Journal Title

NAID

Data Source

[Journal Article] A Fast Wire-Routing Method and an Automatic Layout Tool for RSFQ Digital Circuits Considering Wire-Length Matching2018

Author(s)

Journal Title

DOI

Data Source

[Journal Article] Low-Overhead Fault-Secure Parallel Prefix Adder by Carry-Bit Duplication2013

Author(s)

Journal Title

DOI

NAID

ISSN

Language

Kito Nobutaka 鬼頭信貴

KITO Nobutaka 鬼頭信貴

[Presentation] 部分多重化によるStochastic Computingに基づく多項式演算 RSFQ 回路の精度向上2022