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KAJITANI Yoji  梶谷 洋司

ORCIDConnect your ORCID iD *help
Researcher Number 00016536
Affiliation (based on the past Project Information) *help 1995: Tokyo Inst.of Tech., Faculty of Engrg., Professor, 工学部, 教授
1994: 北陸先端科学技術大学院大学, 情報科学研究所, 教授
1993: 北陸先端科学技術大学院大学, 情報科学研究科, 教授
Review Section/Research Field
Principal Investigator
System engineering
Keywords
Principal Investigator
VLSI CAD / synchronous circuit / layout / routing / floor plan / delay / logic circuit / placement / 組み合せアルゴリズム / FPGA … More / 矩形限定 / パス遅延 / フロアプラン / テクノロジマッピング / VLSI / 同期式回路 / レイアウト / 設計システム / フロアブラシ / 遅延 / 論理回路 / 配置配線 Less
  • Research Projects

    (1 results)
  • Co-Researchers

    (2 People)
  •  Development of Delay Performance Driven Logic Circuit Design SystemPrincipal Investigator

    • Principal Investigator
      KAJITANI Yoji
    • Project Period (FY)
      1993 – 1995
    • Research Category
      Grant-in-Aid for General Scientific Research (B)
    • Research Field
      System engineering
    • Research Institution
      TOKYO INSTITUTE OF TECHNOLOGY
      Japan Advanced Institute of Science and Technology
  • 1.  TAKAHASHI Atushi (30236260)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 2.  FUJIYOSHI Kunihiro (80242569)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results

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