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SUGIMOTO Yasuhiro  杉本 泰博

ORCIDConnect your ORCID iD *help
Researcher Number 00245987
Other IDs
Affiliation (based on the past Project Information) *help 2009 – 2011: Chuo University, 理工学部, 教授
2006 – 2007: 中央大学, 理工学部, 教授
Review Section/Research Field
Principal Investigator
Electron device/Electronic equipment
Keywords
Principal Investigator
CMOS LSI / 集積回路 / 90nm era / A-to-D converter / Low power consumption / Current-mode circuit / 低電圧 / 90nmCMOSプロセス / 電流モードA / 90n世代 … More / D変換器 / A / 低消費電力 / 電流モード回路 / エネルギー効率化 / IC / 高周波フィルタ / 線形化 / 正帰還 / 電子デバイス Less
  • Research Projects

    (2 results)
  • Research Products

    (18 results)
  •  A research to realize a low-voltage analog circuit with a wide signal dynamic range by utilizing the positive feedbackPrincipal Investigator

    • Principal Investigator
      SUGIMOTO Yasuhiro
    • Project Period (FY)
      2009 – 2011
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Research Field
      Electron device/Electronic equipment
    • Research Institution
      Chuo University
  •  A research of low-voltage analog circuit techniques in the 90 nm CMOS eraPrincipal Investigator

    • Principal Investigator
      SUGIMOTO Yasuhiro
    • Project Period (FY)
      2006 – 2007
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Research Field
      Electron device/Electronic equipment
    • Research Institution
      Chuo University

All 2012 2011 2010 2008 2007

All Journal Article Presentation Patent

  • [Journal Article] Linearity and Intrinsic Gain Enhancement Techniques using Positive Feedbacks to Realize a 1.2-V, 200-MHz,+10.3-dBm of IIP3 and 7th-order LPF in a 65-nm CMOS2011

    • Author(s)
      Y. Sugimoto
    • Journal Title

      The 37th European Solid-State Circuits Conference

      Pages: 95-98

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-21560363
  • [Journal Article] A Current-Mode Circuit with a Linearized Input V/I Conversion Scheme and the Realization of a 2V/2.5V Operational, 100 MS/s, MOS SHA2008

    • Author(s)
      Y., Sugimoto, D., Haigh
    • Journal Title

      IEEE Trans. On Circuits and Systems-I : Regular Papers (in printing)

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-18560346
  • [Journal Article] A Current-Mode Circuit with a Linearized Input V/I Conversion Scheme and the Realization of a 2V/2.5V Operational, 100MS/s, MOS SHA2008

    • Author(s)
      Y.Sugimoto and D.Haigh
    • Journal Title

      IEEE Trans. On Circuits and Systems-I: Regular Papers (未定)

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18560346
  • [Journal Article] A Current-Mode Circuit with a Linearized Input V/I Conversion Scheme and the Realization of a 2V/2.5V Operational,100MS/s,MOS SHA2008

    • Author(s)
      Y.Sugimoto and D.Haigh
    • Journal Title

      IEEE Trans.On Circuits and Systems-I:Regular Papers (未定)(in printing)

    • Description
      「研究成果報告書概要(和文)」より
    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18560346
  • [Journal Article] A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture2007

    • Author(s)
      H.Sakurai, S.Tanaka, and Y.Sugimoto
    • Journal Title

      IEICE Trans. Fundamentals E90-A,no.10

    • NAID

      110007540903

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18560346
  • [Journal Article] A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture2007

    • Author(s)
      H.Sakurai, S.Tanaka and Y.Sugimoto
    • Journal Title

      IEICE Trans.Fundamentals E90-A,no.10

      Pages: 2272-2279

    • NAID

      110007540903

    • Description
      「研究成果報告書概要(和文)」より
    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18560346
  • [Journal Article] A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture2007

    • Author(s)
      H., Sakurai, S., Tanaka, Y., Sugimoto
    • Journal Title

      IEICE Trans. Fundamentals E-90A, no. 10

      Pages: 2272-2279

    • NAID

      110007540903

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-18560346
  • [Patent] 信号入力回路、および信号増幅回路2008

    • Inventor(s)
      杉本泰博
    • Industrial Property Rights Holder
      学校法人中央大学
    • Filing Date
      2008-08-07
    • Data Source
      KAKENHI-PROJECT-21560363
  • [Presentation] GHz帯CMOS LC-VCOにおける位相雑音の低減手法に関する研究2012

    • Author(s)
      高橋俊市, 杉本泰博
    • Organizer
      第26回エレクトロニクス実装学会春季講演大会
    • Place of Presentation
      中央大学(東京)
    • Year and Date
      2012-03-08
    • Data Source
      KAKENHI-PROJECT-21560363
  • [Presentation] 1.5 V動作、サイクリック型、電流モードAD変換器の設計2012

    • Author(s)
      太田昌伸, 家室雅季, 杉本泰博
    • Organizer
      2012年電子情報通信学会総合大会
    • Place of Presentation
      大阪
    • Year and Date
      2012-03-21
    • Data Source
      KAKENHI-PROJECT-21560363
  • [Presentation] 1.5V動作、サイクリック型、電流モードAD変換器の設計2012

    • Author(s)
      太田昌伸、家室雅季、杉本泰博
    • Organizer
      電子情報通信学会総合大会
    • Place of Presentation
      岡山大学(岡山)
    • Year and Date
      2012-03-21
    • Data Source
      KAKENHI-PROJECT-21560363
  • [Presentation] パイプラインアーキテクチャを適用した,1.5V動作,サイクリック型電流モードAD変換器回路の研究2011

    • Author(s)
      家室雅季、太田昌伸、杉本泰博
    • Organizer
      電子情報通信学会技術報告
    • Place of Presentation
      大阪
    • Year and Date
      2011-12-15
    • Data Source
      KAKENHI-PROJECT-21560363
  • [Presentation] パイプラインアーキテクチャを適用した1.5V動作,サイクリック型電流モードAD変換器回路の研究2011

    • Author(s)
      家室雅季, 太田昌伸, 杉本泰博
    • Organizer
      電子情報通信学会技術研究報告
    • Place of Presentation
      大阪
    • Year and Date
      2011-12-15
    • Data Source
      KAKENHI-PROJECT-21560363
  • [Presentation] Linearity and Intrinsic Gain Enhancement Techniques using Positive Feedbacks to Realize a 1.2-V, 200-MHz, +10.3-dBm of IIP3 and 7th-order LPF in a 65-nm CMOS2011

    • Author(s)
      Y.Sugimoto
    • Organizer
      The 37th European Solid-State Circuits Conference
    • Place of Presentation
      Helsinki, Finland
    • Year and Date
      2011-09-13
    • Data Source
      KAKENHI-PROJECT-21560363
  • [Presentation] 正帰還補償を用いて線形性を向上したGmアンプの設計手法とそのフィルタ設計への応用2010

    • Author(s)
      下山佑介, 杉本泰博
    • Organizer
      電子情報通信学会技術研究報告
    • Place of Presentation
      大阪
    • Year and Date
      2010-07-23
    • Data Source
      KAKENHI-PROJECT-21560363
  • [Presentation] 正帰還補償を用いて線形性を向上したGmアンプの設計手法とそのフィルタ設計への応用2010

    • Author(s)
      下山佑介, 杉本泰博
    • Organizer
      電子情報通信学会技術研究報告ICD-2010-33
    • Place of Presentation
      大阪
    • Data Source
      KAKENHI-PROJECT-21560363
  • [Presentation] A Current-mode ADC with Current Exchanging and Averaging Capabilities by Switching the Currents and Calculating Data in the Digital Domain2007

    • Author(s)
      N.Yoshii, K.Mizutani and Y.Sugimoto
    • Organizer
      IEEE Custom Integrated Circuits Conference
    • Place of Presentation
      San Francisco
    • Year and Date
      2007-09-17
    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-18560346
  • [Presentation] A Current-mode ADC with Current Exchanging and Averaging Capabilities by Switching the Currents and Calculating Data in the Digital Domain2007

    • Author(s)
      N., Yoshii, K., Mizutani, Y., Sugimoto
    • Organizer
      IEEE Custom Integrated Circuits Conference
    • Place of Presentation
      San Francisco, U. S. A
    • Year and Date
      2007-09-17
    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-18560346

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