NAKATAKE SHIGETOSHI 中武繁寿

… Alternative Names

中武繁寿ナカタケシゲトシ

NAKATAKE Shigetoshi 中武繁寿

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Researcher Number	10282831
Other IDs
External Links
Affiliation (Current)	2025: 北九州市立大学, 国際環境工学部, 教授
Affiliation (based on the past Project Information) *help	2017 – 2021: 北九州市立大学, 国際環境工学部, 教授 2012 – 2014: 北九州市立大学, 国際環境工学部, 教授 2007 – 2010: The University of Kitakyushu, 国際環境工学部, 准教授 2005 – 2006: 北九州市立大学, 国際環境工学部, 助教授 2001: 北九州市立大学, 国際環境工学部, 助教授 … More 2000: 北九州市立大学, 国際環境工学部, 講師 1999: 北九州大学, 国際環境工学部設置準備室, 講師 1998: 東京工業大学, 工学部, 助手 Less
Review Section/Research Field	Principal Investigator Computer system/Network / System engineering / Basic Section 60040:Computer system-related / Electron device/Electronic equipment Except Principal Investigator Science education
Keywords	Principal Investigator アナログLSI / 集積回路 / 2次元パッキング / 配置設計 / フロアプラン / システムLSI / VLSI設計 / 生体センシング / アナログ・パーセプトロン / アナログ再構成システム … More / 低電力ニューラルネットネットワーク回路 / 低電力ニューラルネットワーク回路 / DACベース乗算器 / アナログ・パーセプトロン回路 / 機械学習 / アナログ・デジタル混在回路 / ニューラルネットワーク / パーセプトロン回路 / 機械学習ハードウェア / センサノード / 計装オペアンプ / 低電力オペアンプ / アナログIC評価 / 低電力アナログ / 環境センサー / 環境発電IC / アナログIC / ADC / レイアウト / オペアンプ / 製造性シミュレーション / 統計的シミュレーション / 計装アンプ / センサー / ADコンバータ回路 / コンパレータ回路 / 変動・ばらつき解析 / 差動増幅回路 / 基板バイアス効果 / プログラマブルアナログ回路 / アナログ集積回路 / FPAA / プログラマブルLSI / 電子デバイス / 回路とシステム / レイアウト自動設計 / アダプティブ・ポーティング / アナログレイアウト / シーケンス・ペア / マイグレーション / IP再利用設計 / IPポーティング / アナログIP / コモンセントロイド / センサ融合型アナログIP / アナログ制約生成 / コンパクション / ポーティング / レイアウト設計 / 配置制約 / クロック木合成 / 分割 / SEQ-PAIR / タイミング設計 / ビィルディング・ブロック / VLSI配置設計 / 階層制約 / 階層設計 / タイミング / 配線領域見積り / 配置配線同時設計 / 設計再利用 / BSG / モジュールジェネレーション / 配置 / VLSIレイアウト設計 / チャネル配線 / 多角形パッキング / リーフセル設計 … More Except Principal Investigator 反転授業 / CMOS / アナログLSI / 演算増幅器 / 工学教育 / アナログ集積回路 Less

Analog-Digital Mixed Signal Reconfigurable System for Machine Learning to Analog SignalPrincipal Investigator
- Principal Investigator
  
  NAKATAKE SHIGETOSHI
- Project Period (FY)
  2018 – 2020
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  The University of Kitakyushu
A novel education system for analog LSI designers
- Principal Investigator
  
  Shimizu Akio
- Project Period (FY)
  2017 – 2021
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Science education
- Research Institution
  Ariake National College of Technology
Study on diverse evaluation technology of ultra-fine, ultra-low-power analog LSIs for environmental sensorsPrincipal Investigator
- Principal Investigator
  
  NAKATAKE Shigetoshi
- Project Period (FY)
  2012 – 2014
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  The University of Kitakyushu
Environmental Adaptive Programmable Analog LSIPrincipal Investigator
- Principal Investigator
  
  NAKATAKE SHIGETOSHI
- Project Period (FY)
  2008 – 2010
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system/Network
- Research Institution
  The University of Kitakyushu
センサ融合型アナログIPのアダプティブ・ポーティングに関する研究Principal Investigator
- Principal Investigator
  
  中武繁寿
- Project Period (FY)
  2005 – 2007
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Computer system/Network
- Research Institution
  The University of Kitakyushu
システムLSI設計を支援するブロックレベルタイミング制御方式に関する研究Principal Investigator
- Principal Investigator
  
  中武繁寿
- Project Period (FY)
  1999 – 2001
- Research Category
  
  Grant-in-Aid for Encouragement of Young Scientists (A)
- Research Field
  
  System engineering
- Research Institution
  The University of Kitakyushu
システムVLSIのためのユニバーサルフロアプラナの実用化Principal Investigator
- Principal Investigator
  
  中武繁寿
- Project Period (FY)
  1998 – 1999
- Research Category
  
  Grant-in-Aid for Encouragement of Young Scientists (A)
- Research Field
  
  System engineering
- Research Institution
  The University of Kitakyushu
  Tokyo Institute of Technology

All 2021 2020 2019 2018 2015 2014 2013 2012 2011 2010 2009 2008 2007 2006 Other

All Journal Article Presentation

[Journal Article] Approximate Decomposition of Multi-output LUTs under Acceptable Error Tolerance2021
- Author(s)
  Xuechen Zang, Shigetoshi Nakatake, Hiroyuki Kozutsumi, Mitsunori Katsu, Shoichi Sekiguch
- Journal Title
  
  Proceedings of SASIMI2021
  
  Volume: 1 Pages: 137-141
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18K11223
[Journal Article] An Analog CMOS Implementation for Multi-layer Perceptron With ReLU Activation2020
- Author(s)
  Chao Geng, Qingji Sun, Shigetoshi Nakatake
- Journal Title
  
  Proceedings of MOCAST2020
  
  Volume: 1 Pages: 1-6
- DOI
  10.1109/mocast49295.2020.9200299
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18K11223
[Journal Article] A Fully Synthesizable, 0.3V, 10nW Rail-to-rail Dynamic Voltage Comparator2020
- Author(s)
  Xuncheng Zou, Shigetoshi Nakatake
- Journal Title
  
  Proceedings of MWSCAS2020
  
  Volume: 1 Pages: 199-202
- DOI
  10.1109/mwscas48704.2020.9184498
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18K11223
[Journal Article] Implementation of Analog Perceptron as an Essential Element of Configurable Neural Networks2020
- Author(s)
  Chao Geng, Qingji Sun, Shigetoshi Nakatake
- Journal Title
  
  Sensors
  
  Volume: 20 Issue: 15 Pages: 4222-4222
- DOI
  10.3390/s20154222
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-18K11223
[Journal Article] Density Optimization for Analog Layout Based on Transistor-Array. IEICE Transactions2019
- Author(s)
  Chao Geng, Bo Liu, Shigetoshi Nakatake
- Journal Title
  
  IEICE Transactions on Fundamentals
  
  Volume: 102-A(12) Pages: 1720-1730
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18K11223
[Journal Article] On-chip resistance configuration by subthreshold MOSFET-array for ultra weak current sensing2019
- Author(s)
  Xinghuai Zhang, Shigetoshi Nakatake
- Journal Title
  
  Proceedings of IEEE APCCAS2019
  
  Volume: 1 Pages: 261-264
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18K11223
[Journal Article] An Impedance Measurement of Intravesical Urine Volume Appropriate to Seated Posture2019
- Author(s)
  Ryosuke Sakai, Shigetoshi Nakatake
- Journal Title
  
  Proceedings of IEEE APCCAS2019
  
  Volume: 1 Pages: 385-388
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18K11223
[Journal Article] A Low Voltage Stochastic Flash ADC without Comparator2019
- Author(s)
  Xuncheng Zou, Shigetoshi Nakatake
- Journal Title
  
  IEICE Transactions on Fundamentals
  
  Volume: 102-A(7) Pages: 886-893
- NAID
  130007670857
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18K11223
[Journal Article] Routable and Matched Layout Styles for Analog Module Generation2018
- Author(s)
  Bo Liu, Gong Chen, Bo Yang, Shigetoshi Nakatake
- Journal Title
  
  ACM Transactions on Design Automation of Electronic Systems
  
  Volume: 23(4)
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11223
[Journal Article] Analog perceptron circuit with DAC-based multiplier2018
- Author(s)
  Yoritaka Ishiguchi, Daishi Isogai, Takuma Osawa, Shigetoshi Nakatake
- Journal Title
  
  Integration
  
  Volume: 63 Pages: 240-247
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11223
[Journal Article] Low Voltage CMOS Current Mode Reference Circuit without Operational Amplifiers2018
- Author(s)
  Kenya Kondo, Koichi Tanno, Hiroki Tamura, Shigetoshi Nakatake
- Journal Title
  
  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
  
  Volume: 101-A (5) Pages: 748-754
- NAID
  130006729412
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11223
[Journal Article] A Novel Retargeting Methodology in Computer Aided Design of Nano-watt CMOS Reference Circuit based on Advanced Compact MOSFET Model2015
- Author(s)
  Gong Chen, Qing Dong, Shigetoshi Nakatake, Zhangcai Huang, Yasuaki Inoue
- Journal Title
  
  Journal of Computational Information Systems
  
  Volume: to appear
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-24560411
[Journal Article] Layout Dependent Effect-aware Leakage Current Reduction and Its Application to Low-power SAR-ADC2015
- Author(s)
  Gong Chen, Yu Zhang, Qing Dong, Mingyu Li, Shigetoshi Nakatake
- Journal Title
  
  IEICE Transaction on Fundamentals of ECCS
  
  Volume: to appear
- NAID
  130005085790
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-24560411
[Journal Article] New Sparse Design Framework for Broadband Power Amplifier Behavioral Modeling and Digital Predistortion2014
- Author(s)
  Mingyu Li, Chuan Li, Gong Chen, Yu Zhang, Qing Dong, Shigetoshi Nakatake
- Journal Title
  
  IEEJ Transaction on Electrical and Electronic Engineering
  
  Volume: Vol.9, No.5 Pages: 532-541
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-24560411
[Journal Article] Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming2013
- Author(s)
  Yu ZHANG, Gong CHEN, Bo YANG, Jing LI, Qing DONG, Ming-Yu LI, Shigetoshi NAKATAKE
- Journal Title
  
  IEICE Transaction on Fundamentals of ECCS
  
  Volume: Vol. E96-A No.12 Pages: 2487-2498
- NAID
  130003385301
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-24560411
[Journal Article] Structured Analog Circuit and Layout Design with Transistor Array2013
- Author(s)
  Bo YANG, Qing DONG, Jing LI, Shigetoshi NAKATAKE
- Journal Title
  
  IEICE Transaction on Fundamentals of ECCS
  
  Volume: E96-A, No.12 Pages: 2475-2486
- NAID
  130003385300
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-24560411
[Journal Article] A retargeting methodology of nano-watt CMOS reference circuit based on advanced compact MOSFET model.2012
- Author(s)
  Gong Chen, Bo Yang, Shigetoshi Nakatake, Zhangcai Huang, Yasuaki Inoue
- Journal Title
  
  Proc. of IEEE International Symposium on Circuits and Systems
  
  Volume: 1
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-24560411
[Journal Article] Structured Analog Circuit Design and MOS Transistor Deoomposition for High Accuracy Applications2010
- Author(s)
  楊波、董青、李静、中武繁寿
- Journal Title
  
  Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
  
  Pages: 721-728
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20500055
[Journal Article] Structured Analog Circuit Design and MOS Transistor Decomposition for High Accuracy Applications2010
- Author(s)
  楊波、董青、李静、中武繁寿
- Journal Title
  
  Proc. of IEEE/ACM International Conference on Computer-Aided Design
  
  Pages: 721-726
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20500055
[Journal Article] Current-Driven Linear Laygut of MOSFET with Diffusion-Sharing2010
- Author(s)
  藤村徹、楊波、董青、中武繁寿
- Journal Title
  
  Proceedings of IEEJ International Analog VLSI Workshop (AVLSI)
  
  Pages: 255-230
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20500055
[Journal Article] Current-Driven Linear Layout of MOSFET with Diffusion-Sharing2010
- Author(s)
  藤村徹、楊波、董青、中武繁寿
- Journal Title
  
  Proc. of IEEJ International Analog VLSI Workshop
  
  Pages: 225-230
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20500055
[Journal Article] D-A Converter Based Variation Analysis for Analog Layout Design2010
- Author(s)
  B.Liu, T.Fujimura, B.Yang, S.Nakatake
- Journal Title
  
  Proc.of IEEE/ACM ASP-DAC, 2010.
  
  Pages: 843-848
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20500055
[Journal Article] Regularity-Oriented Analog Placement with Conditional Deisgn Rules2010
- Author(s)
  中武繁寿、川北真裕、伊藤隆夫、小島雅宏、小島典子、泉健二、幅崎唯之
- Journal Title
  
  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E93-A, No.12
  
  Pages: 2389-2398
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20500055
[Journal Article] Regularity-Oriented Analog Placement with Diffusion Sharing and Well Island Generation2010
- Author(s)
  中武繁寿, 川北真裕, 伊藤隆夫, 小島雅宏, 小島典子, 泉健二, 幅崎唯之
- Journal Title
  
  Proc. of IEEE/ACM Asia South Pacific Design Automation Conference
  
  Pages: 305-311
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20500055
[Journal Article] Regularity-Oriented Analog Placement with Diffusion Sharing and Well Island Generation2010
- Author(s)
  S.Nakatake, M.Kawakita, T.Ito, Masahiro Kojima, Michiko Kojima, K.Izumi, T.Habasaki
- Journal Title
  
  Proc.of IEEE/ACM ASP-DAC, 2010
  
  Pages: 305-311
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20500055
[Journal Article] Regularity-Oriented Analog Placement with Conditional Deisgn Rules2010
- Author(s)
  中武繁寿、川北真裕、伊藤隆夫、小島雅宏、小島典子、泉健二、幅崎唯之
- Journal Title
  
  IEICE transactions on Fundamentals of Electronics, Communications and Computer Sciences
  
  Volume: E93-A, No.12 Pages: 2389-2398
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20500055
[Journal Article] D-A Converter Based Variation Analysis for Analog Layout Design2010
- Author(s)
  B. Liu, T.Fujimura, B.Yang, S.Nakatake
- Journal Title
  
  Proc. of IEEE/ACM Asia South Pacific Design Automation Conference
  
  Pages: 843-848
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20500055
[Journal Article] Structured Placement with Topological Regularity Evaluation2009
- Author(s)
  Q.Dong, S.Nakatake
- Journal Title
  
  ISPJ Transaction on System LSI Design Methodology Vol.2
  
  Pages: 222-238
- NAID
  110009598038
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20500055
[Journal Article] Structured Placement with Topological Regularity Evaluation2009
- Author(s)
  Qing Dong, Shigetoshi Nakatake
- Journal Title
  
  IPSJ Transaction on System LSI Design Methodology (掲載予定)
- NAID
  110009598038
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20500055
[Journal Article] Structured Placement with Topological Regularity Evaluation2009
- Author(s)
  董青, 中武繁寿
- Journal Title
  
  IPSJ Transaction on System LSI Design Methodology
  
  Pages: 1-7
- NAID
  110009598038
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20500055
[Journal Article] STI Stress Aware Placement Optimization Based on Geometric Programming2009
- Author(s)
  J.Li, B.Yang, X.Hu, Q.Dong, S.Nakatake
- Journal Title
  
  Proc. of ACM Great Lake Symposium on VLSI
  
  Pages: 209-214
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20500055
[Journal Article] STI Stress Aware Placement Optimization Based on Geometric Programming2009
- Author(s)
  J.Li, B.Yang, X.Hu, Q.Dong, S.Nakatake
- Journal Title
  
  Proc.of ACM GLSVLSI'09
  
  Pages: 209-214
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20500055
[Journal Article] Constraint-Free Analog Placement with Topological Symmetry Structure2008
- Author(s)
  Qing Dong, Shigetoshi Nakatake
- Journal Title
  
  Proc. of IEEE/ACM Asia-South Pacific Conference
  
  Pages: 186-191
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17700075
[Journal Article] Transistor-Level Programmable MOS Analog IC with Body Biasing2008
- Author(s)
  Toru Fujimura, Shigetoshi Nakatake
- Journal Title
  
  Proc. of International Symposium on Circuits and Systems
  
  Pages: 153-156
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20500055
[Journal Article] Transistor-Level Programmable MOS Analog IC with Body Biasing2008
- Author(s)
  藤村徹, 中武繁寿
- Journal Title
  
  Proc. of IEEE International Symposium on Circuits and Systems
  
  Pages: 153-156
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20500055
[Journal Article] Symmetry-Oriented Structured Placement for Analog Layouts2007
- Author(s)
  Qing Dong, Shigetoshi Nakatake
- Journal Title
  
  第20回回路とシステム軽井沢ワークショップ論文集
  
  Pages: 313-318
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17700075
[Journal Article] Structured Placement with Topological Regularity Evaluation2007
- Author(s)
  Shigetoshi Nakatake
- Journal Title
  
  Proc. of IEEE Asia South Pacific Design Automation Conference 2006
  
  Pages: 215-220
- NAID
  110009598038
- Data Source
  KAKENHI-PROJECT-17700075
[Journal Article] Adaptive Porting of Analog IPs with Reusable Conservative Properties2006
- Author(s)
  T.Nojima, S.Nakatake, T.Fujimura, K.Okazaki, Y.Kajitani, N.Ono
- Journal Title
  
  IEEE Computer Society Annual Symposium on VLSI 2006
  
  Pages: 18-23
- Data Source
  KAKENHI-PROJECT-17700075
[Journal Article] Formulating the Empirical Strategies in Module Generation of Analog MOS Layout2006
- Author(s)
  T.Yan, T.Nojima, S.Nakatake
- Journal Title
  
  IEEE Computer Society Annual Symposium on VLSI 2006
  
  Pages: 44-49
- Data Source
  KAKENHI-PROJECT-17700075
[Presentation] An Intravesical Urine Volume Sensor Robust to Body Posture and Movement2019
- Author(s)
  Ryousuke Sakai, Shigetoshi Nakatake
- Organizer
  SASIMI201
- Data Source
  KAKENHI-PROJECT-18K11223
[Presentation] Ultra Low Current Measurement with On-chip High Resistance of MOSFET Array2019
- Author(s)
  Xinghuai Zhang, Daishi Isogai, Takaaki Shirakawa, Shigetoshi Nakatake
- Organizer
  SASIMI2019
- Data Source
  KAKENHI-PROJECT-18K11223
[Presentation] Approximate Function Configuration by Neural Network on Memory-array Unit2019
- Author(s)
  Xuechen Zang, Shigetoshi Nakatake, Hiroyuki Kozutsumi, Mitsunori Katsu, Shoichi Sekiguchi
- Organizer
  SASIMI2019
- Data Source
  KAKENHI-PROJECT-18K11223
[Presentation] アナデジ混在パーセプトロン回路におけるDAC型乗算回路に関する検討2019
- Author(s)
  野口仁一郎・中武繁寿
- Organizer
  電子情報通信学会コンピュータシステム研究会
- Data Source
  KAKENHI-PROJECT-18K11223
[Presentation] 汎用論理スイッチを伴うPLA再構成デコーダの設計とポストレイアウトシミュレーション検証2019
- Author(s)
  石川大暉・八尋信之・中武繁寿
- Organizer
  電子情報通信学会コンピュータシステム研究会
- Data Source
  KAKENHI-PROJECT-18K11223
[Presentation] OpenSource Multi-functional Memory Unit andApplication to Approximate Computing2019
- Author(s)
  Shigetoshi Nakatake
- Organizer
  IEEE HPEC2019
- Data Source
  KAKENHI-PROJECT-18K11223
[Presentation] Approximate Computing in Memory with PLA-based Reconfigurable Decoder2018
- Author(s)
  Nobuyuki Yahiro and Shigetoshi Nakatake
- Organizer
  Workshop on Hardware and Algorithms for Learning On-a-chip (HALO) 2018
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11223
[Presentation] Analog Neural Circuit with DAC-based Perceptron2018
- Author(s)
  Yoritaka Ishiguchi and Shigetoshi Nakatake
- Organizer
  Workshop on Hardware and Algorithms for Learning On-a-chip (HALO) 2018
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11223
[Presentation] Clock Skew Post-silicon Tuning by Multilevel Delay Locked Loop2014
- Author(s)
  Daijiro Murooka, Yu Zhang, Qing Dong and Shigetoshi Nakatake
- Organizer
  IEEE/ACM Workshop on Variability Modeling and Characterization
- Place of Presentation
  San Jose, CA, USA
- Year and Date
  2014-11-06
- Data Source
  KAKENHI-PROJECT-24560411
[Presentation] Layout-dependent Manufacturability Evaluation of Instrumentation Amplifier2014
- Author(s)
  T. Hirata, R. Nishino, S. Nakatake, M. Shimoyama, M. Miyagawa, K. Tanno, A. Yamada
- Organizer
  IEEE/ACM Workshop on Variability Modeling and Characterization
- Place of Presentation
  San Jose, CA. USA
- Year and Date
  2014-11-06
- Data Source
  KAKENHI-PROJECT-24560411
[Presentation] Wideband Digital Predistorter Design Using Subspace Pursuit-Based Volterra Model2013
- Author(s)
  Mingyu Li, Yu Zhang, Gong Chen, Qing Dong, Shigetoshi Nakatake
- Organizer
  The 2013 International Conference on Integrated Circuits, Design, and Verification
- Place of Presentation
  Ho Chi Minh
- Data Source
  KAKENHI-PROJECT-24560411
[Presentation] Practicality on Placement Given by Optimality of Packing2013
- Author(s)
  中武繁寿
- Organizer
  ACM International Symposium on Physical Design
- Place of Presentation
  米国・ネバダ州・ステートライン
- Invited
- Data Source
  KAKENHI-PROJECT-24560411
[Presentation] Performance-driven SRAM Macro Design with Parameterized Cell Considering Layout-dependent Effects2013
- Author(s)
  Yu Zhang, Gong Chen, Qing Dong, Mingyu Li, Shigetoshi Nakatake
- Organizer
  21st IFIP/IEEE International Conference on Very Large Scale Integration
- Place of Presentation
  Istanbul
- Data Source
  KAKENHI-PROJECT-24560411
[Presentation] A 9-bit 50MSps SAR ADC with Pre-charge VCM-based Double Input Range Algorithm2013
- Author(s)
  Gong Chen, Yu Zhang, Qing Dong, Shigetoshi Nakatake, Bo Yang, Jing Li
- Organizer
  ACM Great Lake Synposium on VLSI 2013
- Place of Presentation
  Paris
- Data Source
  KAKENHI-PROJECT-24560411
[Presentation] A Delay-Locked Loop with Multi-Level Channel Length Decomposed Programming Delay Elements2013
- Author(s)
  Zhang Yu, Gong Chen, Mingyu Li, Qing Dong, Shigetoshi Nakatake
- Organizer
  The 2013 International Conference on Integrated Circuits, Design, and Verification
- Place of Presentation
  Ho Chi Minh
- Data Source
  KAKENHI-PROJECT-24560411
[Presentation] Routability-driven Common-Centroid Capacitor Array Generation with Signal Coupling Constraints2013
- Author(s)
  Gong Chen, Jing Li, Bo Yang, Qing Dong, Shigetoshi Nakatake
- Organizer
  The 2013 International Conference on Integrated Circuits, Design, and Verification
- Place of Presentation
  Ho Chi Minh
- Data Source
  KAKENHI-PROJECT-24560411
[Presentation] High Routability and Low Ratio Mimatch Driven Common-Centroid Capacitor Array Generation2012
- Author(s)
  中武繁寿
- Organizer
  IEEE Variability, Characterization and Modeling 2012
- Place of Presentation
  米国・カリフォルニア州・サンノゼ
- Data Source
  KAKENHI-PROJECT-24560411
[Presentation] トランジスタ・アレイ方式に基づくアナログレイアウトの高速プロトタイプ技術2012
- Author(s)
  中武繁寿
- Organizer
  電気学会電子回路研究会
- Place of Presentation
  東京理科大学
- Data Source
  KAKENHI-PROJECT-24560411
[Presentation] アナログ集積回路における容量の実現及び評価手法に関する一考察2011
- Author(s)
  越智敦、島津怜英、藤村徹、中武繁寿
- Organizer
  電子情報通信学会、VLSI設計技術研究会
- Place of Presentation
  沖縄
- Data Source
  KAKENHI-PROJECT-20500055
[Presentation] MOSトランジスタの耐ばらつきチャネル分割に関する考察2010
- Author(s)
  劉博、越智敦、中武繁寿
- Organizer
  電子情報通信学会VLSI設計技術研究会
- Place of Presentation
  沖縄
- Data Source
  KAKENHI-PROJECT-20500055
[Presentation] レイアウト構造を意識したばらつきモデル化及びそのオペアンプ設計における検証2010
- Author(s)
  篠原宏太、日高美穂子、董青、李静、中武繁寿
- Organizer
  電子情報通信学会、VLSI設計技術研究会
- Place of Presentation
  北見工大
- Data Source
  KAKENHI-PROJECT-20500055
[Presentation] MOSトランジスタの耐ばらつきチャネル分割に関する考察2010
- Author(s)
  劉博、越智敦、中武繁寿
- Organizer
  電子情報通信学会
- Place of Presentation
  VLSI設計技術研究会、沖縄
- Data Source
  KAKENHI-PROJECT-20500055
[Presentation] 構造化アナログレイアウト方式及び低電力設計向けトランジスタ・チャネル分割に関する解析2010
- Author(s)
  楊波、董青、李静、中武繁寿
- Organizer
  電子情報通信学会、VLSI設計技術研究会
- Place of Presentation
  九州大学
- Data Source
  KAKENHI-PROJECT-20500055
[Presentation] MOSトランジスタ特性の距離/空間ばらつきにおけるレイアウト構造依存性の解析2009
- Author(s)
  佐土平裕一、中武繁寿
- Organizer
  電子情報通信学会
- Place of Presentation
  デザインガイア、高知
- Data Source
  KAKENHI-PROJECT-20500055
[Presentation] MOSトランジスタ特性の距離/空間ばらつきにおけるレイアウト構造依存性の解析2009
- Author(s)
  佐土平裕一、中武繁寿
- Organizer
  電子情報通信学会デザインガイア
- Place of Presentation
  高知
- Data Source
  KAKENHI-PROJECT-20500055
[Presentation] トランジスタ・アレイ方式に基づくオペアンプのレイアウト設計およびその評価2009
- Author(s)
  川添亜里沙、藤村徹、中武繁寿
- Organizer
  電子情報通信学会
- Place of Presentation
  デザインガイア、高知
- Data Source
  KAKENHI-PROJECT-20500055
[Presentation] トランジスタ・アレイ方式に基づくオペアンプのレイアウト設計およびその評価2009
- Author(s)
  川添亜里沙、藤村徹、中武繁寿
- Organizer
  電子情報通信学会デザインガイア
- Place of Presentation
  高知
- Data Source
  KAKENHI-PROJECT-20500055
[Presentation] MOSアナログモジュール生成手法の提案2008
- Author(s)
  藤井謙雄、松尾健彦、藤村徹、楊波、中武繁寿
- Organizer
  電子情報通信学会 VLSI設計技術研究会技術報告書
- Place of Presentation
  沖縄県男女共同参画センター
- Year and Date
  2008-03-05
- Data Source
  KAKENHI-PROJECT-17700075
[Presentation] ソフトモジュールを含むアナログフロアプラン手法の提案2008
- Author(s)
  村田健太朗、佐々木一也、董青、李静、中武繁寿
- Organizer
  電子情報通信学会 VLSI設計技術研究会技術報告書
- Place of Presentation
  沖縄県男女共同参画センター
- Year and Date
  2008-03-05
- Data Source
  KAKENHI-PROJECT-17700075
[Presentation] Oxygen Sensor Module with Majority Sensing for Monitoring Wide Area at Disaster
- Author(s)
  Ryuta Nishino, Tatsuya Yamada, Qing Dong, Shigetoshi Nakatake
- Organizer
  19th Workshop on Synthesis And System Integration of Mixed Information Technologies
- Place of Presentation
  Yilian, Taiwan
- Year and Date
  2015-03-16 – 2015-03-17
- Data Source
  KAKENHI-PROJECT-24560411
[Presentation] A Study on Visualization of Auscultation-Based Blood Pressure Measurement
- Author(s)
  Yusuke Katsuki, Mingyu Li, Qing Dong, Shigetoshi Nakatake
- Organizer
  19th Workshop on Synthesis And System Integration of Mixed Information Technologies
- Place of Presentation
  Yilian, Taiwan
- Year and Date
  2015-03-16 – 2015-03-17
- Data Source
  KAKENHI-PROJECT-24560411

1. Shimizu Akio (90609885)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
2. 石川洋平 (50435476)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
3. 深井澄夫 (30189906)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
4. 淡野公一 (50260740)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results

NAKATAKE SHIGETOSHI 中武 繁寿

中武 繁寿 ナカタケ シゲトシ

NAKATAKE Shigetoshi 中武 繁寿

Research Projects

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Co-Researchers

Analog-Digital Mixed Signal Reconfigurable System for Machine Learning to Analog SignalPrincipal Investigator

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A novel education system for analog LSI designers

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Study on diverse evaluation technology of ultra-fine, ultra-low-power analog LSIs for environmental sensorsPrincipal Investigator

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Environmental Adaptive Programmable Analog LSIPrincipal Investigator

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センサ融合型アナログIPのアダプティブ・ポーティングに関する研究Principal Investigator

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システムLSI設計を支援するブロックレベルタイミング制御方式に関する研究Principal Investigator

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システムVLSIのためのユニバーサルフロアプラナの実用化Principal Investigator

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[Journal Article] Approximate Decomposition of Multi-output LUTs under Acceptable Error Tolerance2021

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[Journal Article] An Analog CMOS Implementation for Multi-layer Perceptron With ReLU Activation2020

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[Journal Article] A Fully Synthesizable, 0.3V, 10nW Rail-to-rail Dynamic Voltage Comparator2020

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DOI

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[Journal Article] Implementation of Analog Perceptron as an Essential Element of Configurable Neural Networks2020

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[Journal Article] Density Optimization for Analog Layout Based on Transistor-Array. IEICE Transactions2019

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[Journal Article] On-chip resistance configuration by subthreshold MOSFET-array for ultra weak current sensing2019

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[Journal Article] An Impedance Measurement of Intravesical Urine Volume Appropriate to Seated Posture2019

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[Journal Article] A Low Voltage Stochastic Flash ADC without Comparator2019

NAKATAKE SHIGETOSHI 中武繁寿

中武繁寿ナカタケシゲトシ

NAKATAKE Shigetoshi 中武繁寿