OHCHI Akira 大智輝

Researcher Number	10514458
Other IDs
Affiliation (based on the past Project Information) *help	2008 – 2009: Waseda University, 理工学術院, 助手
Review Section/Research Field	Principal Investigator Computer system/Network
Keywords	Principal Investigator 配線遅延 / 設計自動化 / フロアプラン / 高位合成

Research Projects
(1 results)
Research Products
(7 results)

Floorplan-aware High-level SynthesisPrincipal Investigator
- Principal Investigator
  
  OHCHI Akira
- Project Period (FY)
  2008 – 2009
- Research Category
  
  Grant-in-Aid for Young Scientists (Start-up)
- Research Field
  
  Computer system/Network
- Research Institution
  Waseda University

All 2010 2009 2008

All Journal Article Presentation

[Journal Article] Floorplan-aware high-level synthesis for generalized distributed-register architectures2009
- Author(s)
  A. Ohchi, N. Togawa, M. Yanagisawa, T. Ohtsuki
- Journal Title
  
  IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences vol.E92-A,no.12
  
  Pages: 3169-3179
- NAID
  10026861628
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20800052
[Journal Article] Floorplan-aware high-level synthesis for generalized distributed-register architectures2009
- Author(s)
  A.Ohchi, N.Togawa, M.Yanagisawa, T.Ohtsuki
- Journal Title
  
  IEICE Trans.on Fundamentals of Electronics, Communications and Computer Sciences vol.E92-A, no.12
  
  Pages: 3169-3179
- NAID
  10026861628
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20800052
[Journal Article] Floorplan-driven high-level synthesis for distributed/shared-register architectures2008
- Author(s)
  A. Ohchi, S. Kohara, N. Togawa, M. Yanagisawa, T. Ohtsuki
- Journal Title
  
  IPSJ Trans. on SLDM vol.1
  
  Pages: 78-90
- NAID
  130002073183
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20800052
[Presentation] Floorplan-driven High-level Synthesis for GDR Architectures2010
- Author(s)
  大智輝
- Organizer
  IEEE ASP-DAC 2010(Poster session)
- Place of Presentation
  Taipei
- Data Source
  KAKENHI-PROJECT-20800052
[Presentation] Floorplan-driven High-level Synthesis for GDR Architectures2010
- Author(s)
  A. Ohchi, N. Togawa, M. Yanagisawa, T. Ohtsuki
- Organizer
  IEEE ASP-DAC 2010
- Place of Presentation
  Taipei
- Data Source
  KAKENHI-PROJECT-20800052
[Presentation] 一般化レジスタ分散アーキテクチャを対象としたフロアプラン指向高位合成手法2009
- Author(s)
  大智輝, 戸川望, 柳澤政生, 大附辰夫
- Organizer
  第22回回路とシステム軽井沢ワークショップ
- Place of Presentation
  軽井沢
- Data Source
  KAKENHI-PROJECT-20800052
[Presentation] High-level synthesis algorithms with floorplaning for distributed/shared-register architectures2008
- Author(s)
  A. Ohchi, N. Togawa, M. Yanagisawa, T. Ohtsuki
- Organizer
  IEEE ICCAD 2008
- Place of Presentation
  San Jose
- Data Source
  KAKENHI-PROJECT-20800052

OHCHI Akira 大智 輝

Research Projects

Research Products

Floorplan-aware High-level SynthesisPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

[Journal Article] Floorplan-aware high-level synthesis for generalized distributed-register architectures2009

Author(s)

Journal Title

NAID

Data Source

[Journal Article] Floorplan-aware high-level synthesis for generalized distributed-register architectures2009

Author(s)

Journal Title

NAID

Data Source

[Journal Article] Floorplan-driven high-level synthesis for distributed/shared-register architectures2008

Author(s)

Journal Title

NAID

Data Source

[Presentation] Floorplan-driven High-level Synthesis for GDR Architectures2010

Author(s)

Organizer

Place of Presentation

Data Source

[Presentation] Floorplan-driven High-level Synthesis for GDR Architectures2010

Author(s)

Organizer

Place of Presentation

Data Source

[Presentation] 一般化レジスタ分散アーキテクチャを対象としたフロアプラン指向高位合成手法2009

Author(s)

Organizer

Place of Presentation

Data Source

[Presentation] High-level synthesis algorithms with floorplaning for distributed/shared-register architectures2008

Author(s)

Organizer

Place of Presentation

Data Source

OHCHI Akira 大智輝