YAJIMA Shuzo 矢島脩三

… Alternative Names

矢島修三ヤジマシユウゾウ

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Researcher Number	20025901
External Links
Affiliation (based on the past Project Information) *help	1998 – 1999: Kansai University, Professor, 総合情報学部, 教授 1995 – 1996: 京都大学, 工学研究科, 教授 1987 – 1994: Professor, Faculty of Engineering, Kyoto University, 工学部, 教授 1986: Faculty of Engineering,Kyoto University, 工学部, 教授 1985: 京都大学, 工, 教授
Review Section/Research Field	Principal Investigator 計算機工学 / 計算機科学 / 情報工学
Keywords	Principal Investigator 論理設計検証 / 時相論理 / 論理関数処理 / 二分決定グラフ / Logic Design Verification / Binary Decision Diagram / Logic Simulation / 論理シミュレーション / Hardware Algorithm / 算術演算回路 … More / ハードウェアアルゴリズム / ハードウェア設計言語 / 論理シミュレータ / 高水準ハードウェア記述 / Formal Verification / Temporal Logic / 仕様記述 / モデルチェッキング / 形式的設計検証 / temporal logic / 論理設計支援 / 順序回路 / Boolean Function Manipulation / Boolean Function / 計算複雑さ / 論理関数 / Logic Design / Symbolic Simulation / Timing Verification / 論理設計 / 記号シミュレ-ション / 論理シミュレ-ション / タイミング検証 / Redundant Coding / Test Generation / Fault Simulation / On-Line Error Detection / Fault-Tolerant Design / Arithmetic Circuits / 故障シミュレーション / 冗長符号化 / テスト生成 / 故障シミュレ-ション / オンライン誤り検出 / 耐故障設計 / ハ-ドウェアアルゴリズム / Workstation / Specification Desctiption / Vector Processof / 代数的仕様記述 / 正則時相論理 / マルチスクリーン / ワークステーション / ベクトルプロセッサ / Unification / Residue Number Representation / Arithmetic Operation / VLSI; Redundant Binary Representation / Redundant Representation / 単一化操作 / 剰余数表示法 / 冗長2進表現 / 超LSI / 冗長表現 / Hardware Design Language / Vector Processor / Logic Simulator / High-Level Hardware Description / グラフィクス・ワークステーション / 形式的仕様記述 / ベクトル計算機 / binary decision diagram / logic function manipulation / model checking / First-order Predicate logic / Function level design / Formal design verification / 算術演算回路検証 / 機能レベル検証 / 三分決定グラフ / 二分モーメントグラフ / 調理関数処理 / マイクロプロセッサ / 第一階述語論理 / 機能レベル設計 / Model Checking / Formal Specification / Logic Function Manipulation / 形式的論理設計検証 / 論理開数処理 / 形式的検証 / Combinatorial Problem / Content Addressable Memory / Computational Complexity / Prallel Algorithm / Computer Aided Logic Design / 組合せ問題 / 内容アドレスメモリ / 並列アルゴリズム / computer-aided logic design / state assignment / logic function optimization / sequential circuits / logic design verification / logic synthesis / 状態割当て / 論理関数簡単化 / 論理合成 / Computational complexity / computer Aided Design / 計算機援用設計 / Hazard / Asynchronous Sequential Circuit / 論立設計検証 / ハザ-ド / 非同期式順序回路 … More Except Principal Investigator Distributed Processing / Cooperative Processing / Computer Network / Environment Integration / Media Integration / Information Base / Multimedia / Database / マルチメデア / 分散処理 / 協調処理 / コンピュータネットワーク / 環境統合 / メディア統合 / 情報ベース / マルチメディア / データベース Less

Research Projects
(11 results)
Co-Researchers
(17 People)

Advanced Database Systems for Integration of Media and User Environments
- Principal Investigator
  
  KANBAYASHI Yohiko
- Project Period (FY)
  1996 – 1999
- Research Category
  
  Grant-in-Aid for Scientific Research on Priority Areas (A)
- Research Institution
  Kyoto University
Research on Development of Formal Logic Design Verifier for MicroprocessorsPrincipal Investigator
- Principal Investigator
  
  YAJIMA Shuzo
- Project Period (FY)
  1995 – 1996
- Research Category
  
  Grant-in-Aid for Scientific Research (A)
- Research Field
  
  計算機科学
- Research Institution
  KYOTO UNIVERSITY
Basic Research on High-Speed Boolean Function ManipulatorPrincipal Investigator
- Principal Investigator
  
  YAJIMA Shuzo
- Project Period (FY)
  1993 – 1994
- Research Category
  
  Grant-in-Aid for General Scientific Research (B)
- Research Field
  
  計算機科学
- Research Institution
  KYOTO UNIVERSITY
Research on Formal Verifier of Logic Design Based on Temporal LogicPrincipal Investigator
- Principal Investigator
  
  YAJIMA Shuzo
- Project Period (FY)
  1993 – 1994
- Research Category
  
  Grant-in-Aid for Developmental Scientific Research (B)
- Research Field
  
  計算機科学
- Research Institution
  KYOTO UNIVERSITY
Research on Development of Logic Synthesizer and Design Verifier for Sequential Circuits Based on Boolean Function ManipulationPrincipal Investigator
- Principal Investigator
  
  YAJIMA Shuzo
- Project Period (FY)
  1991 – 1992
- Research Category
  
  Grant-in-Aid for Developmental Scientific Research (B)
- Research Field
  
  情報工学
- Research Institution
  KYOTO UNIVERSITY
Research on Efficient Manipulation of Boolean Functions Using Shared Binary Decision Diagrams and Its Application to Computer Aided Logic DesignPrincipal Investigator
- Principal Investigator
  
  YAJIMA Shuzo
- Project Period (FY)
  1990 – 1991
- Research Category
  
  Grant-in-Aid for General Scientific Research (B)
- Research Field
  
  情報工学
- Research Institution
  Kyoto University
Research on Development of a Logic Design Verification System Based on Time-Symbolic SimulationPrincipal Investigator
- Principal Investigator
  
  YAJIMA Shuzo
- Project Period (FY)
  1989 – 1990
- Research Category
  
  Grant-in-Aid for Developmental Scientific Research (B).
- Research Field
  
  計算機工学
- Research Institution
  Kyoto University
Researches on the Design of Highly Reliable High-Speed Arithmetic Circuits with Redundant CodingPrincipal Investigator
- Principal Investigator
  
  YAJIMA Shuzo
- Project Period (FY)
  1988 – 1989
- Research Category
  
  Grant-in-Aid for General Scientific Research (B)
- Research Field
  
  計算機工学
- Research Institution
  KYOTO UNIVERSITY
Research on Development of High-Speed Logic Simulators Using a Vector Processor and Logic Design Verification SystemsPrincipal Investigator
- Principal Investigator
  
  YAJIMA Shuzo
- Project Period (FY)
  1986 – 1987
- Research Category
  
  Grant-in-Aid for Developmental Scientific Research
- Research Field
  
  計算機工学
- Research Institution
  Kyoto University
Research on Design of VLSI Oriented Hardware Algorithms Using Redundant RepresentationPrincipal Investigator
- Principal Investigator
  
  YAJIMA Shuzo
- Project Period (FY)
  1985 – 1986
- Research Category
  
  Grant-in-Aid for General Scientific Research (B)
- Research Field
  
  計算機工学
- Research Institution
  Kyoto University
Developmental Research on Interactive Logic Simulator-Verifier with High-Level Hardware DescriptionPrincipal Investigator
- Principal Investigator
  
  YAJIMA Shuzo
- Project Period (FY)
  1984 – 1985
- Research Category
  
  Grant-in-Aid for Developmental Scientific Research
- Research Field
  
  計算機工学
- Research Institution
  Kyoto University

1. OGINO Hiroyuki (40144323)

# of Collaborated Projects: 9 results

# of Collaborated Products: 0 results
2. TAKAGI Naofumi (10171422)

# of Collaborated Projects: 8 results

# of Collaborated Products: 0 results
3. HIRAISHI Hiromi (40093299)

# of Collaborated Projects: 8 results

# of Collaborated Products: 0 results
4. TAKENAGA Yasuhiko (20236491)

# of Collaborated Projects: 5 results

# of Collaborated Products: 0 results
5. ISHIURA Nagisa (60193265)

# of Collaborated Projects: 4 results

# of Collaborated Products: 0 results
6. HAMAGUCHI Kiyoharu (80238055)

# of Collaborated Projects: 4 results

# of Collaborated Products: 0 results
7. IWAMA Kazuo (50131272)

# of Collaborated Projects: 3 results

# of Collaborated Products: 0 results
8. KAWAKUBO Kazuo (10186067)

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
9. YASUURA Hiroto (80135540)

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
10. YASUOKA Kouichi (20230211)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
11. KANBAYASHI Yohiko (00026311)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
12. DOI Norihisa (50051553)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
13. TAKAGI Tosihisa (30110836)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
14. OHNO Yutaka (60026185)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
15. FUJIWARA Yuzuru (40110473)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
16. 長尾真 (30025960)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
17. 國井利泰 (50013743)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results

YAJIMA Shuzo 矢島 脩三

矢島 修三 ヤジマ シユウゾウ

Research Projects

Co-Researchers

Advanced Database Systems for Integration of Media and User Environments

Principal Investigator

Project Period (FY)

Research Category

Research Institution

Research on Development of Formal Logic Design Verifier for MicroprocessorsPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Basic Research on High-Speed Boolean Function ManipulatorPrincipal Investigator

Principal Investigator

Project Period (FY)

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Research Institution

Research on Formal Verifier of Logic Design Based on Temporal LogicPrincipal Investigator

Principal Investigator

Project Period (FY)

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Research on Development of Logic Synthesizer and Design Verifier for Sequential Circuits Based on Boolean Function ManipulationPrincipal Investigator

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Research on Efficient Manipulation of Boolean Functions Using Shared Binary Decision Diagrams and Its Application to Computer Aided Logic DesignPrincipal Investigator

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Research on Development of a Logic Design Verification System Based on Time-Symbolic SimulationPrincipal Investigator

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Research Institution

Researches on the Design of Highly Reliable High-Speed Arithmetic Circuits with Redundant CodingPrincipal Investigator

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Research on Development of High-Speed Logic Simulators Using a Vector Processor and Logic Design Verification SystemsPrincipal Investigator

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Research on Design of VLSI Oriented Hardware Algorithms Using Redundant RepresentationPrincipal Investigator

Principal Investigator

Project Period (FY)

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Research Field

Research Institution

Developmental Research on Interactive Logic Simulator-Verifier with High-Level Hardware DescriptionPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

YAJIMA Shuzo 矢島脩三

矢島修三ヤジマシユウゾウ