Wen Xiaoqing 温暁青

… Alternative Names

WEN Xiaoqing 温暁青

温暁青オンギョウセイ

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Researcher Number	20250897
Other IDs
External Links
Affiliation (Current)	2025: 九州工業大学, 大学院情報工学研究院, 教授
Affiliation (based on the past Project Information) *help	2013 – 2024: 九州工業大学, 大学院情報工学研究院, 教授 2012: 九州工業大学, 情報工学研究院, 教授 2012: 九州工業大学, 情報工程学院, 教授 2008 – 2011: Kyushu Institute of Technology, 大学院・情報工学研究院, 教授 2007: Kyushu Institute of Technology, 大学院・情報工学研究科, 教授 … More 2006: Kyushu Institute of Technology, Graduate School of Computer Science and Systems Engineering, Associate Professor, 大学院情報工学研究科, 助教授 2004 – 2006: 九州工業大学, 情報工学研究科, 助教授 1995: 秋田大学, 鉱山学部, 講師 Less
Review Section/Research Field	Principal Investigator Computer system/Network / Computer system / Basic Section 60040:Computer system-related / 計算機科学 Except Principal Investigator Computer system/Network
Keywords	Principal Investigator LSIテスト / IR-Drop / 低電力テスト / 高信頼化 / シフトエラー / シフト電力 / LSI回路 / 誤テスト / テスト電力 / スキャンテスト … More / 高品質化 / 活性化パス / 微小遅延故障 / 遅延テスト / テスト電力調整 / テスト生成 / 欠陥検出設計 / 欠陥影響最小化設計 / 欠陥影響定量化 / 欠陥 / 耐ソフトエラー記憶素子 / ディペンダブル・コンピュー / ディペンダブル・コンピュータ / グルーピング / テストクロック / シフトタイミング / ディペンダブル・コンピューティング / 電子デバイス・機器 / 計算機システム / クロックパス / パス遅延 / 信号値遷移 / 誤テスト回避 / テスト電力制御 / クロック / IR Drop / Low Power Test / Scan Design / LSI Test / IRドロップ / 低消費電力テスト / スキャン設計 / マスク回路 / 入力遷移 / テスト電力安全性 / テストデータ変更 / クロックストレッチ / IR-Dop / キャプチャ電力 / テストデータ / テスト品質 / 最適電力テスト / クロックスキュー / スキャンテスト電力 / 等価故障解析 / 故障モデル / 故障診断 / テスト集合の最小化 / テスト容易化設計 / 電流テスト / VLSIのテスト … More Except Principal Investigator 計算機システム / 論理回路 / システムオンチップ / ディペンダブル・コンピューティング / fault simulation / dependability / delay fault / bridging fault / fault diagnosis / test pattern generation / logic circuit / design and test of LSIs / N回検出テスト / X故障モデル / テスト生成 / 故障シミュレーション / ディペンダビリティ / 遅延故障 / ブリッジ故障 / 故障診断 / テストパターン生成 / LSIの設計とテスト / (1)ディペンダブル・コンピューティング / VLSIの設計とテスト / 高信頼設計 / VLSI の設計とテスト Less

Research on Defect-Aware Soft-Error Mitigation for Reliable LSIsPrincipal Investigator
- Principal Investigator
  
  温暁青
- Project Period (FY)
  2021 – 2024
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Kyushu Institute of Technology
Shift-Power-Safe Scan Test Methodology for High-Quality Low-Power LSI CircuitsPrincipal Investigator
- Principal Investigator
  
  Wen Xiaoqing
- Project Period (FY)
  2017 – 2020
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system
- Research Institution
  Kyushu Institute of Technology
Research on High-Quality Test Method for Avoiding False Testing of Next-Generation Low-Power LSIsPrincipal Investigator
- Principal Investigator
  
  Wen Xiaoqing
- Project Period (FY)
  2015 – 2017
- Research Category
  
  Grant-in-Aid for Challenging Exploratory Research
- Research Field
  
  Computer system
- Research Institution
  Kyushu Institute of Technology
Research on Extra-Low-Power Self-Test for LSI Circuits in Implantable Medical DevicesPrincipal Investigator
- Principal Investigator
  
  WEN XIAOQING
- Project Period (FY)
  2013 – 2017
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system
- Research Institution
  Kyushu Institute of Technology
Research on Logic Switching Activity Balanced Test for High-Quality Low-Cost LSIsPrincipal Investigator
- Principal Investigator
  
  WEN Xiaoqing
- Project Period (FY)
  2012 – 2014
- Research Category
  
  Grant-in-Aid for Challenging Exploratory Research
- Research Field
  
  Computer system/Network
- Research Institution
  Kyushu Institute of Technology
Power Adjustment Testing for Next-Generation Low-Power LSI CircuitsPrincipal Investigator
- Principal Investigator
  
  WEN Xiaoqing
- Project Period (FY)
  2010 – 2012
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Kyushu Institute of Technology
A study on high quality field test for VLSIs
- Principal Investigator
  
  KAJIHARA Seiji
- Project Period (FY)
  2009 – 2012
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Kyushu Institute of Technology
Research on Advanced VLSI Test for Avoiding Signal DegradationPrincipal Investigator
- Principal Investigator
  
  WEN Xiaoqing
- Project Period (FY)
  2007 – 2009
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system/Network
- Research Institution
  Kyushu Institute of Technology
Research on False Test Avoidance for LSI Yield ImprovementPrincipal Investigator
- Principal Investigator
  
  WEN Xiaoqing
- Project Period (FY)
  2005 – 2006
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system/Network
- Research Institution
  Kyushu Institute of Technology
Study on LSI testing for multiple fault models
- Principal Investigator
  
  KAJIHARA Seiji
- Project Period (FY)
  2004 – 2006
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system/Network
- Research Institution
  Kyushu Institute of Technology
VLSIの電流テスト容易化設計と電流波形による故障検出に関する研究Principal Investigator
- Principal Investigator
  
  温暁青
- Project Period (FY)
  1995
- Research Category
  
  Grant-in-Aid for Encouragement of Young Scientists (A)
- Research Field
  
  計算機科学
- Research Institution
  Akita University

[Book] Chapter 9 "Low-Power Testing for 2D/3D Devices and Systems" in Design of 3D Integrated Circuits and Systems2014
- Author(s)
  X. Lin, X. Wen, D. Xiang
- Total Pages
  43
- Publisher
  CRC Press
- Data Source
  KAKENHI-PROJECT-24650022
[Book] はかる×わかる半導体-入門編2013
- Author(s)
  浅田邦博(監修),温暁青,梶原誠司, (他5名)
- Publisher
  日経 BPコンサルティング
- Data Source
  KAKENHI-PROJECT-21300015
[Book] Part IV Circuit Testing, Chapter 20: Low-Power Testing for Low-Power LSI Circuits, Advanced Circuits for Emerging Technologies2012
- Author(s)
  X. Wen and Y. Zorian, John Wiley & Sons
- Publisher
  New Jersey
- Data Source
  KAKENHI-PROJECT-22300017
[Book] Part IV Circuit Testing, Chapter 20: Low-Power Testing for Low-Power LSI Circuits, in Advanced Circuits for Emerging Technologies2012
- Author(s)
  X. Wen, Y. Zorian
- Total Pages
  18
- Publisher
  Part IV Circuit Testing, Chapter 20: Low-Power Testing for Low-Power LSI Circuits
- Data Source
  KAKENHI-PROJECT-22300017
[Book] Power-Aware Testing and Test Strategies for Low Power Devices2009
- Author(s)
  X. Wen, S. Wang
- Publisher
  Springer
- Data Source
  KAKENHI-PROJECT-19500047
[Book] Power-Aware Testing and Test Strategies for Low Power Devices(Chapter 3 : Low-Power Test Generation)2009
- Author(s)
  X.Wen, S.Wang
- Total Pages
  51
- Publisher
  Springer(New York, USA)
- Data Source
  KAKENHI-PROJECT-19500047
[Book] Advanced SOC Test Architectures-Towards Nanometer Designs2007
- Author(s)
  P. Girard, X. Wen, N. A. Touba
- Publisher
  Elsevier Science
- Data Source
  KAKENHI-PROJECT-19500047
[Book] Advanced SOC Test Architectures - Towards Nanometer Designs (Chapter 7: Low-Power Testing)2007
- Author(s)
  L.-T. Wang, C. Stroud, N. A. Touba (Chapter 7: P. Girard, X.Wen, N. A. Touba)
- Publisher
  Elsevier Science (Massachusetts, USA)
- Data Source
  KAKENHI-PROJECT-19500047
[Journal Article] GPU-Accelerated Estimation and Targeted Reduction of Peak IR-Drop during Scan Chain Shifting2023
- Author(s)
  S. Shi, S. Holst, and X. Wen
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: E106.D Issue: 10 Pages: 1694-1704
- DOI
  10.1587/transinf.2023EDP7011
- ISSN
  0916-8532, 1745-1361
- Year and Date
  2023-10-01
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23K21653
[Journal Article] A Highly Robust and Low Power Flip-Flop Cell with Complete Double-Node-Upset Tolerance for Aerospace Applications2023
- Author(s)
  A. Yan, Y. He, Z. Li, J. Cui, T. Ni, Z. Huang, P. Girard, and X. Wen
- Journal Title
  
  IEEE Design & Test
  
  Volume: 40 Issue: 4 Pages: 34-41
- DOI
  10.1109/mdat.2023.3267747
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21653
[Journal Article] LDAVPM: A Latch Design and Algorithm-based Verification Protected against Multiple-Node-Upsets in Harsh Radiation Environments2023
- Author(s)
  A. Yan, Z. Li, Z. Zhou, J. Cui, Z. Huang, T. Ni, P. Girard, and X. Wen
- Journal Title
  
  IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
  
  Volume: 42 Issue: 6 Pages: 2069-2073
- DOI
  10.1109/tcad.2022.3213212
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21653
[Journal Article] Evaluation and Test of Production Defects in Hardened Latches2022
- Author(s)
  R. Ma, S. Holst, X. Wen, A. Yan, and H. Xu
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: E105.D Issue: 5 Pages: 996-1009
- DOI
  10.1587/transinf.2021EDP7216
- ISSN
  0916-8532, 1745-1361
- Year and Date
  2022-05-01
- Language
  English
- Peer Reviewed / Open Access / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21653
[Journal Article] Probability of Switching activity to Locate Hotspots in Logic Circuits2021
- Author(s)
  Y. Zhang, S. Holst, X. Wen, K. Miyase, S. Kajihara, J. Qian
- Journal Title
  
  IEICE Trans. on Inf. & Syst.
  
  Volume: E104-D
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Journal Article] Non-intrusive Online Distributed Pulse Shrinking Based Interconnect Testing in 2.5D IC2020
- Author(s)
  T. Ni, H. Chang, T. Song, Q. Xu, Z. Huang, H. Liang, A. Yan, X. Wen
- Journal Title
  
  IEEE Trans. on Circuits and Systems II: Express Briefs
  
  Volume: 67 Issue: 11 Pages: 2657-2661
- DOI
  10.1109/tcsii.2019.2962824
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Journal Article] LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Fault2020
- Author(s)
  T. Ni, Y. Yao, H. Chang, L. Lu, H. Liang, A. Yan, Z. Huang, X. Wen
- Journal Title
  
  IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
  
  Volume: 39 Issue: 10 Pages: 2938-2951
- DOI
  10.1109/tcad.2019.2946243
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Journal Article] A Novel TDMA-Based Fault Tolerance Technique for the TSVs in 3D-ICs Using Honeycomb Topology2020
- Author(s)
  Ni Tianming、Yang Zhao、Chang Hao、Zhang Xiaoqiang、Lu Lin、Yan Aibin、Huang Zhengfeng、Wen Xiaoqing
- Journal Title
  
  IEEE Transactions on Emerging Topics in Computing
  
  Volume: Early Access Issue: 2 Pages: 724-734
- DOI
  10.1109/tetc.2020.2969237
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Journal Article] A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application2019
- Author(s)
  A. Yan, K. Yang, Z. Huang, J. Zhang, J. Cui, X. Fang, M. Yi, X. Wen
- Journal Title
  
  IEEE Transactions on Circuits and Systems II: Express Briefs
  
  Volume: 66 Issue: 2 Pages: 287-291
- DOI
  10.1109/tcsii.2018.2849028
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Journal Article] Novel Double-Node-Upset-Tolerant Memory Cell Designs through Radiation-Hardening-by-Design and Layout2019
- Author(s)
  A. Yan, Z. Wu, J. Guo, J. Song, X. Wen
- Journal Title
  
  IEEE Transactions on Reliability
  
  Volume: 68 Issue: 1 Pages: 354-363
- DOI
  10.1109/tr.2018.2876243
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Journal Article] A Method to Detect Bit Flips in a Soft-Error Resilient TCAM2017
- Author(s)
  Syafalni Infall、Sasao Tsutomu、Wen Xiaoqing
- Journal Title
  
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  
  Volume: 37-8 Issue: 6 Pages: 1-1
- DOI
  10.1109/tcad.2017.2748019
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17K00086, KAKENHI-PROJECT-26330072, KAKENHI-PROJECT-17H01716
[Journal Article] A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips2017
- Author(s)
  T. Kato, S. Wang, Y. Sato, S. Kajihara, X. Wen
- Journal Title
  
  IEEE Trans. on Emerging Topics in Computing
  
  Volume: PP Issue: 3 Pages: 1-1
- DOI
  10.1109/tetc.2017.2767070
- NAID
  120007006783
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-15K12003, KAKENHI-PROJECT-15K12004
[Journal Article] Test Pattern Modification for Average IR-Drop Reduction2016
- Author(s)
  W.-S. Ding, H.-Y. Hsieh, C.-Y. Han, James C.-M. Li, X. Wen
- Journal Title
  
  IEEE Trans. on VLSI Systems
  
  Volume: 24 Issue: 1 Pages: 38-49
- DOI
  10.1109/tvlsi.2015.2391291
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280016
[Journal Article] Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation2016
- Author(s)
  F. Li, X. Wen, K. Miyase, S. Holst, S. Kajihara
- Journal Title
  
  IEICE Trans. Fundamentals
  
  Volume: E99.A Issue: 12 Pages: 2310-2319
- DOI
  10.1587/transfun.E99.A.2310
- NAID
  130005170516
- ISSN
  0916-8508, 1745-1337
- Language
  English
- Peer Reviewed / Acknowledgement Compliant / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280016, KAKENHI-PROJECT-15K12003, KAKENHI-PROJECT-15K12004
[Journal Article] Thermal-Aware Small-Delay Defect Testing in Integarted Circuits for Mitigating Overkill2016
- Author(s)
  D. Xiang, K. Shen, B. B. Bhattacharya, X. Wen, X. Lin
- Journal Title
  
  EEE Trans. on Computer-Aided Design
  
  Volume: 35 Issue: 3 Pages: 499-512
- DOI
  10.1109/tcad.2015.2474365
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280016
[Journal Article] Test Pattern Modification for Average IR-Drop Reduction2015
- Author(s)
  W.-S. Ding, H.-Y. Hsieh, C.-Y. Han, James C.-M. Li, X. Wen
- Journal Title
  
  IEEE Trans. on VLSI Systems
  
  Volume: 未定
- Data Source
  KAKENHI-PROJECT-25280016
[Journal Article] Test Pattern Modification for Average IR-Drop Reduction2015
- Author(s)
  W.-S. Ding, H.-Y. Hsieh, C.-Y. Han, James C.-M. Li, X. Wen
- Journal Title
  
  IEEE Transactions on VLSI Systems
  
  Volume: 未定
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-24650022
[Journal Article] On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST2014
- Author(s)
  A. Tomita, X. Wen, Y. Sato, S. Kajihara, P. Girard, M. Tehranipoor, L.-T. Wang,
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: E97.D Issue: 10 Pages: 2706-2718
- DOI
  10.1587/transinf.2014EDP7039
- NAID
  130004696754
- ISSN
  0916-8532, 1745-1361
- Language
  English
- Peer Reviewed / Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-24650022, KAKENHI-PROJECT-25280016
[Journal Article] LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing2013
- Author(s)
  Y. Yamato, X. Wen, M. A. Kochte, K. Miyase, S. Kajihara, L.-T. Wang
- Journal Title
  
  IEEE Design & Test of Computers
  
  Volume: Vol. 30, No. 4 Issue: 4 Pages: 60-70
- DOI
  10.1109/mdt.2012.2221152
- NAID
  120005895737
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-24650022, KAKENHI-PROJECT-25280016
[Journal Article] A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing2013
- Author(s)
  K. Miyase, R. Sakai, X. Wen, Xiaoqing, M. Aso, H. Furukawa, Y. Yamato, S. Kajihara
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: E96.D Issue: 9 Pages: 2003-2011
- DOI
  10.1587/transinf.E96.D.2003
- NAID
  130003370989
- ISSN
  0916-8532, 1745-1361
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-24650022, KAKENHI-PROJECT-25280016
[Journal Article] Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains2012
- Author(s)
  S. Wu, L.-T. Wang, X. Wen, Z. Jiang, W.-B. Jone, M. S. Hsiao, L. Tan, Y. Zhang, C.-M. Li, J.-L. Huang
- Journal Title
  
  ACM Transactions on Design Automation of Electronic Systems
  
  Volume: Vol. 17, Iss. 4 Issue: 4 Pages: 1-16
- DOI
  10.1145/2348839.2348852
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22300017
[Journal Article] Fault Detection with Optimum March Test Algorithm2012
- Author(s)
  N.A. Zakaria, W.Z.W. Hasan, I.A. Halin, R.M. Sidek, X. Wen
- Journal Title
  
  Journal of Theoretical and Applied Information Technology
  
  Volume: Vol. 47, No. 1 Pages: 18-27
- DOI
  10.1109/isms.2012.88
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-24650022
[Journal Article] Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of TDF Patterns2012
- Author(s)
  H. Salmani, W. Zhao, M. Tehranipoor, S. Chacravarty, P. Girard, and X. Wen
- Journal Title
  
  ASP Journal of Lower Power Electronics
  
  Volume: Vol. 8, No. 2 Pages: 248-258
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22300017
[Journal Article] Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains2012
- Author(s)
  S. Wu, L. -T. Wang, X. Wen, Z. Jiang, W. -B. Jone, M. S. Hsiao, L. Tan, Y. Zhang, C. -M. Li, and J. -L. Huang
- Journal Title
  
  ACM Transactions on Design Automation of Electronic Systems
  
  Volume: Vol. 17, Issue 4, Article No. 48
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22300017
[Journal Article] A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing2011
- Author(s)
  Y.Yamato, X.Wen, R.Miyase, H.Furukawa, S.Kajihara
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: E94-D Issue: 4 Pages: 833-840
- DOI
  10.1587/transinf.E94.D.833
- NAID
  10029506602
- ISSN
  0916-8532, 1745-1361
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22300017
[Journal Article] Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing2011
- Author(s)
  K.Miyase, K.Noda, H.Ito, K.Hatayama, T.Aikyo, Y.Yamato, H.Furukawa, X.Wen, S.Kaiihara
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: E94.D Issue: 6 Pages: 1216-1226
- DOI
  10.1587/transinf.E94.D.1216
- NAID
  10029805011
- ISSN
  0916-8532, 1745-1361
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22300017
[Journal Article] Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing2011
- Author(s)
  K. Miyase, K. Noda, H. Ito, K. Hatayama, T. Aikyo, Y. Yamato, H. Furukawa, X. Wen, and S. Kajihara
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: Vol. E94-D, No. 6 Pages: 1216-1226
- NAID
  10029805011
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22300017
[Journal Article] On Delay Test Quality for Test Cubes2010
- Author(s)
  S. Oku, S. Kajihara, Y. Sato, K. Miyase, X. Wen
- Journal Title
  
  IPSJ Transactions on System LSI Design Methodology
  
  Volume: 3 Pages: 283-291
- DOI
  10.2197/ipsjtsldm.3.283
- NAID
  110009599095
- ISSN
  1882-6687
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] On Estimation of NBTI-Induced Delay Degradation2010
- Author(s)
  M.Noda, S.Kajihara, Y.Sato, K.Miyase, X.Wen, Y.Miura
- Journal Title
  
  Proc.of 5th IEEE European Test Symposium
  
  Pages: 107-111
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for LOS and LOC Schemes2010
- Author(s)
  F.Wu, L..Dilillo, A.Bosio, P.Girard, S.Pravossoudovitch, A.Virazel, M.Tehranipoor, X.Wen, N.Ahmed
- Journal Title
  
  ASP Journal of Lower Power Electronics
  
  Volume: 6 Pages: 359-374
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22300017
[Journal Article] A Study of Capture-Safe Test Generation Flow for At-Speed Testing2010
- Author(s)
  K.Miyase, X.Wen, S.Kajihara, Y.Yamato, A.Takashima, H.Furukawa, K.Noda, N.Ito, K.Hatayama, T.Aikyo, K.Saluja
- Journal Title
  
  IEICE Trans.Inf.& Syst.
  
  Volume: E93-A Pages: 1309-1318
- NAID
  10027367482
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22300017
[Journal Article] High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme2010
- Author(s)
  Kohei Miyase, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara, (他3名)
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: E93-D Issue: 1 Pages: 2-9
- DOI
  10.1587/transinf.E93.D.2
- NAID
  10026812940
- ISSN
  0916-8532, 1745-1361
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] A Study of Capture-Safe Test Generation Flow for At-Speed Testing2010
- Author(s)
  K. Miyase, X. Wen, S. Ka j ihara, Y. Yamato, A. Takashima, H. Furukawa, K. Noda, H. Ito, K. Hatayama, T. Aikyo, and K. K. Saluja
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: Vol. E93-A, No. 7 Pages: 1309-1318
- NAID
  10027367482
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22300017
[Journal Article] On Test Pattern Compaction with Multi-Cycle and Multi-Observation Scan Test2010
- Author(s)
  Seiji Kajihara, Makoto Matsuzono, Hisato Yamaguchi, Yasuo Sato, Kohei Miyase, Xiaoqing Wen
- Journal Title
  
  Int. Symp. on Communications and Information Technologies
  
  Pages: 723-726
- DOI
  10.1109/iscit.2010.5665084
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] On Delay Test Quality for Test Cubes2010
- Author(s)
  S.Oku, S.Kajihara, Y.Sato, K.Miyase, X.Wen
- Journal Title
  
  IPSJ Transactions on System LSI Design Methodology
  
  Volume: Vol.3 Pages: 283-291
- NAID
  130000418476
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] On Test Pattern Compaction with Multi-Cycle and Multi-Observation Scan Test2010
- Author(s)
  S.Kajihara, M.Matsuzono, H.Yamaguchi, Y.Sato, K.Miyase, X.Wen
- Journal Title
  
  Proc.of 10th International Symposium on Communications and Information Technologies
  
  Pages: 723-726
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] High Launch Switching Activity Reduction in At-Speed Scan Testing using CTX : A Clock-Gating-Based Test Relaxation and X-Filling Scheme2010
- Author(s)
  K.Miyase, X.Wen, H.Furukawa, Y.Yamato, S.Kajihara, P.Girard, L.-T.Wang, M.Tehranipoor
- Journal Title
  
  IEICE Transactions on Information and Systems Vol.E93-D
  
  Pages: 2-9
- NAID
  10026812940
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] On Estimation of NBTI-Induced Delay Degradation2010
- Author(s)
  M. Noda, S. Kajihara, Y. Sato, K. Miyase, X. Wen, Y. Miura
- Journal Title
  
  15thIEEE European Test Symp
  
  Pages: 107-111
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] High Launch Switching Activity Reduction in At-Speed Scan Testing using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme2009
- Author(s)
  K. Miyase, X. Wen, H. Furukawa, Y. Yamato, S. Kajihara, P. Girard, L.-T. Wang, M. Tehranipoor
- Journal Title
  
  IEICE Trans. Inf. & Syst. Vol.E93-D,No.1
  
  Pages: 2-9
- NAID
  10026812940
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19500047
[Journal Article] Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment2009
- Author(s)
  M.-F. Wu, J.-L. Huang, X. Wen, K. Miyase
- Journal Title
  
  IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems Vol.28,No.11
  
  Pages: 1767-1776
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19500047
[Journal Article] On Calculation of Delay Range in Fault Simulation for Test Cubes2009
- Author(s)
  S.KAJIHARA, S.OKU, K.MIYASE, X.WEN, Y.SATO
- Journal Title
  
  Proc.of International Symposium on VLSI Design, Automation, and Test
  
  Pages: 64-67
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] シグナルインテグリティ考慮型LSIテストを目指して2009
- Author(s)
  温暁青
- Journal Title
  
  信頼性学会誌 Vol.31,No.7
  
  Pages: 498-505
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19500047
[Journal Article] A GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-Speed Scan Testing2009
- Author(s)
  Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara
- Journal Title
  
  IEEE 15th Pacific Rim Int. Symp. on Dependable Computing
  
  Pages: 81-86
- DOI
  10.1109/prdc.2009.21
- NAID
  120006784394
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] シグナルインテグリティ考慮型LSIテストを目指して2009
- Author(s)
  温暁青
- Journal Title
  
  信頼性学会誌 31
  
  Pages: 498-505
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19500047
[Journal Article] CAT : A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing2009
- Author(s)
  K.Enokimoto, X.Wen, Y.Yamato, K.Miyase, H.Sone, S.Kajihara, M.Aso, H.Furukawa
- Journal Title
  
  Proc.of Asian Test Symposium
  
  Pages: 99-104
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] A GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-Speed Scan Testing2009
- Author(s)
  Y.Yamato, X.Wen, K.Miyase, H.Furukawa, S.Kajihara
- Journal Title
  
  Proc.of IEEE 15th Pacific Rim International Symposium on Dependable Computing
  
  Pages: 81-86
- NAID
  120006784394
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment2009
- Author(s)
  M.-F.Wu, J.-L.Huang, X.Wen, K.Miyase
- Journal Title
  
  IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems 28
  
  Pages: 1767-1776
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19500047
[Journal Article] A Novel Post-ATPG IR-Drop Reduction Scheme for At-Speed Scan Testing in Broadcast-Scan-Based Test Compression Environment2009
- Author(s)
  K.Miyase, Y.Yamato, K.Noda, H.Ito, K.Hatayama, T.Aikyo, X.Wen, S.Kajihara
- Journal Title
  
  Proc.of International Conference on Computer-Aided Design
  
  Pages: 97-104
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing2009
- Author(s)
  Kazunari Enokimoto, Xiaoqing Wen, Yuta Yamato, Kohei Miyase, Hiroaki Sone, Seiji Kajihara(他2名)
- Journal Title
  
  Proc. Asian Test Symp
  
  Pages: 99-104
- DOI
  10.1109/ats.2009.22
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21300015
[Journal Article] High Launch Switching Activity Reduction in At-Speed Scan Testing using CTX : A Clock-Gating-Based Test Relaxation and X-Filling Scheme2009
- Author(s)
  K.Miyase, X.Wen, H.Furukawa, Y.Yamato, S.Kajihara, P.Girard, L.-T.Wang, M.Tehranipoor
- Journal Title
  
  IEICE Trans. Inf.& Syst. E93-D
  
  Pages: 2-9
- NAID
  10026812940
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19500047
[Journal Article] Test Strategies for Low-Power Devices2008
- Author(s)
  C.P. Ravikumar, M. Hirech, X. Wen
- Journal Title
  
  Journal of Low Power Electronics Vol.4
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19500047
[Journal Article] Estimation of Delay Test Quality and Its Application to Test Generation2008
- Author(s)
  S. Kajihara, S. Morishima, M. Yamamoto, X. Wen, M. Fukunaga, K. Hatayama, T. Aikyo
- Journal Title
  
  IPSJ Transaction of System LSI Design Methodology 1
  
  Pages: 104-115
- NAID
  130002073185
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19500047
[Journal Article] Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing2008
- Author(s)
  X. Wen, K. Miyase, T. Suzuki, S. Kajiihara, L. -T. Wang, K. K. Saluja, K. Kinoshita
- Journal Title
  
  Journal of Electronic Testing : Theory and Applications, Special Issue on Low Power Testing 24
  
  Pages: 379-391
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19500047
[Journal Article] Test Strategies for Low-Power Devices2008
- Author(s)
  C. P. Ravikumar, M. Hirech, X. Wen
- Journal Title
  
  Journal of Low Power Electronics 4
  
  Pages: 127-138
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19500047
[Journal Article] Estimation of Delay Test Quality and Its Application to Test Generation2008
- Author(s)
  S. Kajihara, S. Morishima, M. Yamamoto, X. Wen, M. Fukunaga, K. Hatayama, T. Aikyo
- Journal Title
  
  IPSJ Transaction of System LSI Design Methodology Vol.1
  
  Pages: 104-115
- NAID
  130002073185
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19500047
[Journal Article] Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing2008
- Author(s)
  X. Wen, K. Miyase, T. Suzuki, S. Kajiihara, L.-T. Wang, K.K. Saluja, K. Kinoshita
- Journal Title
  
  Journal of Electronic Testing: Theory and Applications, Special Issue on Low Power Testing Vol.24
  
  Pages: 379-391
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19500047
[Journal Article] A Novel ATPG Method for Capture Power Reduction During Scan Testing2007
- Author(s)
  X.Wen, S.Kajiihara, K.Miyase, T.Suzuki, K.K.Saluja, L.-T.Wang, K.Kinoshita
- Journal Title
  
  IEICE Trans. Inf. & Syst. E90-D
  
  Pages: 1398-1405
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19500047
[Journal Article] A Novel ATPG Method for Capture Power Reduction During Scan Testing2007
- Author(s)
  X. Wen, S. Kajiihara, K. Miyase, T. Suzuki, K.K. Saluja, L.-T. Wang, K. Kinoshita
- Journal Title
  
  IEICE Trans. Inf. & Syst. E90-D,No.9
  
  Pages: 1398-1405
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19500047
[Journal Article] A New Method for Low-Capture-Power Test Generation for Scan Testing2006
- Author(s)
  X.Wen, Y.Yamashita, S.Kajiihara, L.-T.Wang, K.K.Saluja, K.Kinoshita
- Journal Title
  
  IEICE Trans. Inf. ＆ Syst. Vol.E89-D,No.5
  
  Pages: 1679-1686
- Data Source
  KAKENHI-PROJECT-17500039
[Journal Article] A New Method for Low-Capture-Power Test Generation for Scan Testing2006
- Author(s)
  X.Wen, Y.Yamashita, S.Kajiihara, L.-T.Wang, K.K.Saluja, K.Kinoshita・
- Journal Title
  
  IEICE Trans. Inf. ＆ Syst. Vol. E89-D, No. 5
  
  Pages: 1679-1686
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17500039
[Journal Article] A New Method for Low-Capture-Power Test Generation for Scan Testing2006
- Author(s)
  X.Wen, Y.Yamashita, S.Kajiihara, L.-T.Wang, K.K.Saluja, K.Kinoshita
- Journal Title
  
  IEICE Trans. Inf. ＆ Syst. Vol. E89-D,No. 5
  
  Pages: 1679-1686
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17500039
[Journal Article] 中間故障電圧値を扱う故障シミュレーションの高速化について2005
- Author(s)
  温暁青, 梶原誠司, 玉本英夫, K. K. Saluja, 樹下行三
- Journal Title
  
  電子情報通信学会論文誌D-I Vol. J88-D-1,No. 4
  
  Pages: 906-907
- NAID
  10016599053
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17500039
[Journal Article] 中間故障電圧値を扱う故障シミュレーションの高速化について2005
- Author(s)
  温暁青, 他
- Journal Title
  
  電子情報通信学会論文誌D-I Vol.J88-D-I, No.4
  
  Pages: 906-907
- NAID
  10016599053
- Data Source
  KAKENHI-PROJECT-16500036
[Journal Article] Efficient Test Set Modification for Capture Power Reduction2005
- Author(s)
  Xiaoqing Wen, Tatsuya Suzuki, Seiji Kajihara, Kohei Miyase, Yoshihiro Minamoto, Laung-Terng Wang, K. K. Saluja
- Journal Title
  
  Journal of Low Power Electronics Issue 3
  
  Pages: 319-330
- NAID
  120006782190
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17500039
[Journal Article] Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation2005
- Author(s)
  Y.Doi, S.Kajihara, X.Wen, L.Li, K.Chakrabarty
- Journal Title
  
  Proceedings of Asia and South Pacific Design Automation Conference
  
  Pages: 59-64
- NAID
  110003318193
- Data Source
  KAKENHI-PROJECT-16500036
[Journal Article] 中間故障電圧値を扱う故障シミュレーションの高速化について2005
- Author(s)
  温暁青
- Journal Title
  
  電子情報通信学会論文誌 D-I Vol. J88-D-I No. 4
  
  Pages: 906-907
- NAID
  10016599053
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16500036
[Journal Article] On Speed-Up of Fault Simulation for Handling Intermediate Faulty Voltages2005
- Author(s)
  Xiaoqing Wen, Seiji Kajihara, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita
- Journal Title
  
  IEICE Trans. Inf. ＆ Syst D-I, Vol. J88-D-I, No. 4
  
  Pages: 906-907
- NAID
  10016599053
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17500039
[Journal Article] On Speed-Up of Fault Simulation for Handling Intermediate Faulty Voltages2005
- Author(s)
  Xiaoqing WEN
- Journal Title
  
  IEICE Trans. Info. and Syst. Vol. J88-D-I-No. 4
  
  Pages: 906-907
- NAID
  10016599053
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-16500036
[Journal Article] On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies2005
- Author(s)
  Xiaoqing WEN, 他
- Journal Title
  
  IEICE Trans.Info.and Syst. Vol.E88-D, No.4
  
  Pages: 703-710
- Data Source
  KAKENHI-PROJECT-16500036
[Journal Article] Efficient Test Set Modification for Capture Power Reduction2005
- Author(s)
  X.Wen, T.Suzuki, S.Kajihara, K.Miyase, Y.Minamoto, L.-T.Wang, K.K.Saluja
- Journal Title
  
  Journal of Low Power Electronics Issue 3
  
  Pages: 319-330
- NAID
  120006782190
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17500039
[Journal Article] On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies2005
- Author(s)
  Xiaoqing WEN
- Journal Title
  
  IEICE Trans. Info. and Syst. Vol. E88-D-No. 4
  
  Pages: 703-710
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-16500036
[Journal Article] On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies2005
- Author(s)
  Xiaoqing WEN
- Journal Title
  
  IEICE Trans. Info. and Syst. Vol. E88-D No. 4
  
  Pages: 703-710
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16500036
[Journal Article] On Per-Test Fault Diagnosis Using the X-Fault Model2004
- Author(s)
  X.Wen, T.Miyoshi, S.Kajihara, L.T.Wang, K.K.Saluja, K.Kinoshita
- Journal Title
  
  Proceedings of Int'l Conf.on Computer-Aided Design
  
  Pages: 633-640
- Data Source
  KAKENHI-PROJECT-16500036
[Journal Article] A New Method for Low-Capture-Power Test Generation for Scan Testing
- Author(s)
  Xiaoqing Wen (温暁青)
- Journal Title
  
  IEICE Trans.Inf.& Syst. (平成17年11月4日採録済み)
- Data Source
  KAKENHI-PROJECT-17500039
[Patent] 論理値決定方法及び論理値決定プログラム2008
- Inventor(s)
  宮瀬紘平, 温暁青, 梶原誠司, 大和勇太
- Industrial Property Rights Holder
  九州工業大学
- Industrial Property Number
  2008-211473
- Filing Date
  2008-08-02
- Data Source
  KAKENHI-PROJECT-19500047
[Patent] 論理値決定方法及び論理値決定プログラム2008
- Inventor(s)
  宮瀬絋平, 温暁青, 梶原誠司, 大和勇太
- Industrial Property Rights Holder
  九州工業大学
- Industrial Property Number
  2008-211473
- Filing Date
  2008-08-20
- Data Source
  KAKENHI-PROJECT-19500047
[Patent] 判別方法及びプログラム2008
- Inventor(s)
  呉孟帆, 黄俊郎, 温暁青, 宮瀬紘平
- Industrial Property Rights Holder
  九州工業大学, 台湾大学
- Industrial Property Number
  2008-273484
- Acquisition Date
  2008-10-23
- Data Source
  KAKENHI-PROJECT-19500047
[Patent] 判別方法及びプログラム2008
- Inventor(s)
  呉孟帆, 黄俊郎, 温暁青, 宮瀬絋平
- Industrial Property Rights Holder
  九州工業大学・台湾大学
- Industrial Property Number
  2008-273484
- Filing Date
  2008-10-23
- Data Source
  KAKENHI-PROJECT-19500047
[Patent] 半導体論理回路装置のテスト方法、装置及び半導体論理回路装置のテストプログラムを記憶した記憶媒体2005
- Inventor(s)
  温暁青, 梶原誠司
- Industrial Property Rights Holder
  *九州工業大学
- Industrial Property Number
  2005-130806
- Filing Date
  2005-04-28
- Data Source
  KAKENHI-PROJECT-17500039
[Patent] 半導体論理回路装置のテストベクトル生成方法、装置及び半導体論理回路装置のテストベクトル生成プログラムを記憶した記憶媒体2005
- Inventor(s)
  温暁青, 梶原誠司
- Industrial Property Rights Holder
  九州工業大学
- Industrial Property Number
  2005-215214
- Filing Date
  2005-07-26
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17500039
[Patent] 半導体論理回路装置のテストベクトル生成方法、装置及び半導体論理回路装置のテストベクトル生成プログラムを記憶した記憶媒体2005
- Inventor(s)
  温暁青, 梶原誠司
- Industrial Property Rights Holder
  *九州工業大学
- Industrial Property Number
  2005-215214
- Filing Date
  2005-04-28
- Data Source
  KAKENHI-PROJECT-17500039
[Patent] 半導体論理回路装置のテスト方法、装置及び半導体論理回路装置のテストプログラムを記憶した記憶媒体2005
- Inventor(s)
  温暁青, 梶原誠司
- Industrial Property Rights Holder
  九州工業大学
- Industrial Property Number
  2005-130806
- Filing Date
  2005-04-28
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17500039
[Presentation] A Robust and High-Performance Flip-Flop with Complete Soft-Error Recovery2023
- Author(s)
  A. Yan, X. Li, , T. Ni, Z. Huang, and X. Wen
- Organizer
  The 10th Int'l Conf. on Dependable systems and Their Applications
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21653
[Presentation] Mitigating Test-Induced Yield-Loss by IR-Drop-Aware X-Filling2023
- Author(s)
  S. Shi, S. Holst, and X. Wen
- Organizer
  The 16th IEEE Int`l Symp. on Embedded Milticore/Many-core Systems-on-Chip
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21653
[Presentation] A High-Performance and P-Type FeFET-Based Non-Volatile Latch2023
- Author(s)
  A. Yan, Y. Chen, Z. Huang, J. Cui, and X. Wen
- Organizer
  IEEE Asian Test Symp.
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21653
[Presentation] A Low Area and Low Dealy Latch Design with Complete Double-Node-Upset-Recovery For Aerospace Applications2023
- Author(s)
  A. Yan, S. Wei, J. Zhang, J. Cui, J. Song, Xiang, T. Ni, P. Girard, and X. Wen
- Organizer
  The 33rd Great Lake Symp. on VLSI
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21653
[Presentation] BiSTAHL: A Built-In Self-Testable Soft-Error-Hardened Scan-Cell2023
- Author(s)
  S. Holst, R. Ma, X. Wen, A. Yan, and H. Xu
- Organizer
  IEEE European Test Symp.
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21653
[Presentation] A Low Overhead and Double-Node-Upset Self-Recoverable Latch2023
- Author(s)
  A. Yan, F. Xia, T. Ni, J. Cui, Z. Huang, P. Girard, and X. Wen
- Organizer
  The 7th Int'l Test Conf. in Asia
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21653
[Presentation] Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS2022
- Author(s)
  A. Yan, S. Song, J. Zhang, J. Cui, Z. Huang, T. Ni, X. Wen, and P. Girard
- Organizer
  IEEE Int'l Test Conf. in Asia
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21653
[Presentation] Functional Safety of AI Accelerators with Hardware Defects2022
- Author(s)
  B. Lim, S. Holst, X. Wen
- Organizer
  第13回LSIテストセミナー
- Data Source
  KAKENHI-PROJECT-23K21653
[Presentation] A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology2022
- Author(s)
  A. Yan, Z. Zhou, S. Wei, J. Cui, Y. Zhou, T. Ni, P. Girard, and X. Wen
- Organizer
  the 32nd Great Lake Symp. on VLSI
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21653
[Presentation] Estimation and Reduction of Peak IR-Drop in Scan Shift2022
- Author(s)
  S. Shi, S. Holst, and X. Wen
- Organizer
  the 10th Int'l Symp. on Applied Engineering and Sciences
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21653
[Presentation] A Low-Cost and Robust Latch Protected against Triple Node Upsets in Nanoscale CMOS based on Source-Drain Cross-Coupled Inverters2022
- Author(s)
  A. Yan, S. Song, Y. Chen, J. Cui, Z. Huang, and X. Wen
- Organizer
  IEEE Int'l Conf. on Nanotechnology
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21653
[Presentation] Effective Switching Probability Calculation to Locate Hotspots in Logic Circuits2022
- Author(s)
  T. Utsunomiya, R. Hoshino, K. Miyase, S.-K. Lu, X. Wen, and S. Kajihara
- Organizer
  IEEE Int'l Test Conf. in Asia
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21653
[Presentation] Power-Aware Testing in the Era of IoT2022
- Author(s)
  X. Wen
- Organizer
  IEEE Int'l Conf. on Solid-State and Integrated Circuit Technology
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21653
[Presentation] Functional Safety of AI Accelerators with Hardware Defects2021
- Author(s)
  S. Holst, B. Lim, X. Wen
- Organizer
  The 9th Int'l Symp. on Applied Engineering and Sciences
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21653
[Presentation] STAHL: A Novel Scan-Test-Aware Hardened Latch2021
- Author(s)
  R. Ma, S. Holst, X. Wen
- Organizer
  The 9th Int'l Symp. on Applied Engineering and Sciences
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21653
[Presentation] LSI Testing: A Core Technology to A Successful LSI Industry2021
- Author(s)
  X. Wen
- Organizer
  IEEE Int'l Conf. on ASIC
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21653
[Presentation] GPU-Accelerated Timing Simulation of Systolic Array Based AI Accelerators2021
- Author(s)
  S. Holst, B. Lim, X. Wen
- Organizer
  IEEE Asian Test Symp.
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-23K21653
[Presentation] LSIの高消費電力エリアに対する信号値遷移制御率向上に関する研究2020
- Author(s)
  史傑, 宮瀬紘平, 温暁青, 梶原誠司
- Organizer
  信学技報, Vol. 119, No. 420, DC2019-94
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] Probability of Switching activity to Locate Hotspots in Logic Circuits2020
- Author(s)
  R. Oba, K. Miyase, R. Hoshino, S.-K. Lu, X. Wen, S. Kajihara
- Organizer
  IEEE Workshop on RTL and High Level Testing
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] メモリのサイズおよび形状に起因するロジック部の高消費電力エリア特定に関する研究2020
- Author(s)
  高藤大輝, 星野龍, 宮瀬紘平, 温暁青, 梶原誠司
- Organizer
  電子情報通信学会技術研究報告, DC2020-72
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] LSIの領域毎の信号値遷移確率に基づく電力評価に関する研究2020
- Author(s)
  大庭涼, 星野竜, 宮瀬紘平, 温暁青, 梶原誠司
- Organizer
  信学技報, Vol. 120, No. 236, DC2020-33
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] A Novel High Performance Scan-Test-Aware Hardened Latch Design2020
- Author(s)
  R. Ma, S. Holst, X. Wen, A. Yan, H. Xu,
- Organizer
  電子情報通信学会技術研究報告, DC2020-71
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] メモリ搭載LSIに対するロジック部の消費電力解析に関する研究2020
- Author(s)
  児玉優也, 宮瀬紘平, 高藤大輝, 温暁青, 梶原誠司
- Organizer
  信学技報, Vol. 119, No. 420, DC2019-93
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] Logic Fault Diagnosis of Hidden Delay Defects2020
- Author(s)
  . Holst, M. Kampmann, A. Sprenger, J. D. Reimer, S. Hellebrand, H.-J. Wunderlich, X. Wen
- Organizer
  Int'l Test Conf.
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] Variation-Aware Small Delay Fault Diagnosis on Compacted Failure Data2019
- Author(s)
  S. Holst, E. Schneider, M. A. Kochte, X. Wen, H.-J. Wunderlich
- Organizer
  Int'l Test Conf.
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] ower-Aware Testing for Low-Power VLSI Circuits2019
- Author(s)
  X. Wen
- Organizer
  IEEE Int'l Conf. on Electron Devices and Solid-State Circuits
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] LSIのホットスポット分布の解析に関する研究2019
- Author(s)
  河野雄大, 宮瀬紘平, 呂學坤, 温暁青, 梶原誠司
- Organizer
  電子情報通信学会ディペンダブルコンピューティン研究会
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] Single-Event Double-Upset Self-Recoverable and Single-Event Transient Pulse Filterable Latch Design for Low Power Applications2019
- Author(s)
  A. Yan, Z. Wu, K. Yang, Y. Ling, X. Wen
- Organizer
  22nd Design, Automation and Test in Europe
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] A Static Method for Analyzing Hotspot Distribution on the LSI2019
- Author(s)
  K. Miyase, Y. Kawano, S.-K. Lu, X. Wen, S. Kajihara
- Organizer
  IEEE Int'l Test Conf. in Asia
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption2019
- Author(s)
  Y. Zhang, S. Holst, X. Wen, K. Miyase, S. Kajihara, J. Qian
- Organizer
  第11回LSIテストセミナー
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] Small Delay Fault Diagnosis on Compacted Responses2019
- Author(s)
  S. Holst, E. Schneider, M. A. Kochte, X. Wen, H.-J. Wunderlich
- Organizer
  第80回 FTC 研究会
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] Targeted Partial-Shift For Mitigating Shift Switching Activity Hot-Spots During Scan Test2019
- Author(s)
  S. Holst, S. Shi, and X. Wen
- Organizer
  IEEE Pacific Rim Int'l Symp. on Dependable Computing
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] Bit-Flip Errors Detection using Random Partial Don't-Care Keys for a Soft-Error-Tolerant TCAM2018
- Author(s)
  I. Syafalni, T. Sasao, X. Wen
- Organizer
  27th International Workshop on Logic and Synthesis
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] The Impact of Production Defects on the Soft-Error Tolerance of Hardened Latches2018
- Author(s)
  S. Holst, R. Ma, X. Wen
- Organizer
  第17 回情報科学技術フォーラム
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing2018
- Author(s)
  Y. Zhang, X. Wen, S. Holst, K. Miyase, S. Kajihara, H.-J. Wunderlich, J. Qian
- Organizer
  IEEE Asian Test Symposium
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption2018
- Author(s)
  Y. Zhang, S. Holst, X. Wen, K. Miyase, S. Kajihara, J. Qian
- Organizer
  第17 回情報科学技術フォーラム
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] 正当化操作を用いたレイアウト上のホットスポット特定に関する研究2018
- Author(s)
  河野雄大, 宮瀬紘平, 温暁青, 梶原誠司
- Organizer
  電子情報通信学会DC研究会
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] The Impact of Production Defects on the Soft-Error Tolerance of Hardened Latches2018
- Author(s)
  S. Holst, R. Ma, X. Wen
- Organizer
  IEEE European Test Symposium
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors2017
- Author(s)
  S. Holst, E. Schneiderz, H. Kawagoe, M. A. Kochtez, K. Miyase, H.-J. Wunderlichz, S. Kajihara, X. Wen
- Organizer
  Proc. of IEEE Int'l Test Conf.
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] Locating Hot Spot with Justification Techniques in a Layout Design2017
- Author(s)
  K. Miyase, Y. Kawano, X. Wen, S. Kajihara
- Organizer
  IEEE Workshop on RTL and High Level Testing
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K12003
[Presentation] 電源ネットワークに対するIR-Dropの影響範囲特定に関する研究2017
- Author(s)
  宮瀬紘平, 濱崎機一, ザウアーマティアス, ポリアンイリア, ベッカーベルンド, 温暁青, 梶原誠司
- Organizer
  電子情報通信学会 DC研究会
- Place of Presentation
  東京都
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors2017
- Author(s)
  S. Holst, E. Schneider, H. Kawagoe, M. A. Kochtez, K. Miyase, H.-J. Wunderlichz, S. Kajihara, X. Wen
- Organizer
  IEEE Int'l Test Conf.
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K12003
[Presentation] Locating Hot Spot with Justification Techniques in a Layout Design2017
- Author(s)
  K. Miyase, Y. Kawano, X. Wen, S. Kajihara
- Organizer
  Proc. of IEEE Workshop on RTL and High Level Testing
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption2017
- Author(s)
  Y. Zhang, S. Holst, X. Wen, K. Miyase, S. Kajihara, J. Qia
- Organizer
  IEEE Asian Test Symp.
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K12003
[Presentation] On Avoiding Test Data Corruption by Optimal Scan Chain Grouping2017
- Author(s)
  Y. Zhang, S. Holst, X. Wen, K. Miyase, S. Kajihara, J. Qian
- Organizer
  第181回SLDM・第46回EMB合同研究発表会
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] Locating Hot Spot with Justification Techniques in a Layout Design2017
- Author(s)
  K. Miyase, Y. Kawano, X. Wen, S. Kajihara
- Organizer
  IEEE Workshop on RTL and High Level Testing
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] 高品質実速度スキャンテスト生成に関する研究2017
- Author(s)
  宮崎俊紀、温暁青、ホルストシュテファン、宮瀬紘平、梶原誠司
- Organizer
  第9回LSIテストセミナー
- Place of Presentation
  福岡市
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption2017
- Author(s)
  Y. Zhang, S. Holst, X. Wen, K. Miyase, S. Kajihara, J. Qian
- Organizer
  Proc. of IEEE Asian Test Symp.
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01716
[Presentation] Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test2016
- Author(s)
  S. Holst, E. Schneider, X. Wen, S. Kajihara, Y. Yamato, H.-J. Wunderlich, M. A. Kochte
- Organizer
  IEEE Asian Test Symp.
- Place of Presentation
  Hiroshima, Japan
- Year and Date
  2016-11-24
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K12003
[Presentation] Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test2016
- Author(s)
  S. Eggersgluess, S. Holst, D. Tillex, K. Miyase, X. Wen
- Organizer
  IEEE Asian Test Symp.
- Place of Presentation
  Hiroshima, Japan
- Year and Date
  2016-11-21
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] SAT-Based Post-Processing for Regional Capture Power Reduction in At-Speed Scan Test Generation2016
- Author(s)
  S. Eggersgluess, K. Miyase, X. Wen
- Organizer
  IEEE European Test Symp.
- Place of Presentation
  Amsterdam, The Netherlands
- Year and Date
  2016-05-23
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K12003
[Presentation] Power-Aware Testing For Low-Power VLSI Circuits2016
- Author(s)
  X. Wen
- Organizer
  The 13th IEEE International Conference on Solid-State and Integrated Circuit Technology
- Place of Presentation
  Hangzhu, China
- Year and Date
  2016-10-25
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K12003
[Presentation] Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At- Speed Scan Test2016
- Author(s)
  S. Holst, E. Schneider, X. Wen, S. Kajihara, Y. Yamato, H.-J. Wunderlich, M. A. Kochte
- Organizer
  IEEE Asian Test Symp.
- Place of Presentation
  Hiroshima, Japan
- Year and Date
  2016-11-21
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] Power-Aware Testing For Low-Power VLSI Circuits2016
- Author(s)
  X. Wen
- Organizer
  The 13th IEEE International Conference on Solid-State and Integrated Circuit Technology
- Place of Presentation
  Hangzhu, China
- Year and Date
  2016-10-25
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test2016
- Author(s)
  S. Eggersgluess, S. Holst, D. Tillex, K. Miyase, X. Wen
- Organizer
  IEEE Asian Test Symp.
- Place of Presentation
  Hiroshima, Japan
- Year and Date
  2016-11-24
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K12003
[Presentation] A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST2016
- Author(s)
  T. Kato, S. Wang, Y. Sato, S. Kajiahara, X. Wen
- Organizer
  IEEE Asian Test Symp.
- Place of Presentation
  Hiroshima, Japan
- Year and Date
  2016-11-21
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K12003
[Presentation] Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation2016
- Author(s)
  F. Li, X. Wen, S. Holst, K. Miyase, S. Kajihara
- Organizer
  Int'l Symp. on Applied Engineering and Sciences
- Place of Presentation
  Kitakyushu, Japan
- Year and Date
  2016-12-17
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K12003
[Presentation] On Optimal Power-Aware Path Sensitization2016
- Author(s)
  M. Sauer, J. Jiang, S. Reimer, K. Miyase, X. Wen, B. Becker, I. Polian
- Organizer
  IEEE Asian Test Symp.
- Place of Presentation
  Hiroshima, Japan
- Year and Date
  2016-11-24
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K12003
[Presentation] On Optimal Power-Aware Path Sensitization2016
- Author(s)
  M. Sauer, J. Jiang, S. Reimer, K. Miyase, X. Wen, B. Becker, I. Polian
- Organizer
  IEEE Asian Test Symp.
- Place of Presentation
  Hiroshima, Japan
- Year and Date
  2016-11-21
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] SAT-Based Post-Processing for Regional Capture Power Reduction in At-Speed Scan Test Generation2016
- Author(s)
  S. Eggersgluess, K. Miyase, X. Wen
- Organizer
  IEEE European Test Symp.
- Place of Presentation
  Amsterdam, The Netherlands
- Year and Date
  2016-05-23
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] Multiple-Bit-Flip Detection Scheme for A Soft-Error Resilient TCAM2016
- Author(s)
  Syafalni, T. Sasao, X. Wen
- Organizer
  IEEE Computer Society Annual Symp. on VLSI
- Place of Presentation
  Pittsburgh, USA
- Year and Date
  2016-07-11
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST2016
- Author(s)
  T. Kato, S. Wang, Y. Sato, S. Kajiahara, X. Wen
- Organizer
  IEEE Asian Test Symp.
- Place of Presentation
  Hiroshima, Japan
- Year and Date
  2016-11-21
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] 論理BISTにおけるスキャンイン電力制御手法とTEG評価2016
- Author(s)
  加藤隆明, 王森レイ, 佐藤康夫, 梶原誠司, 温暁青
- Organizer
  情報処理学会 DAシンポジウム
- Place of Presentation
  石川県加賀市
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation2016
- Author(s)
  F. Li, X. Wen, S. Holst, K. Miyase, S. Kajihara
- Organizer
  Int'l Symp. on Applied Engineering and Sciences
- Place of Presentation
  Kitakyushu, Japan
- Year and Date
  2016-12-17
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] A Soft-Error Tolerant TCAM for Multiple-Bit Flips Using Partial Don't Care Keys2015
- Author(s)
  I. Syafalni, T. Sasao, X. Wen
- Organizer
  The 24th Int'l Workshop on Logic and Synthesis
- Place of Presentation
  Mountain View, USA
- Year and Date
  2015-06-12
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] Power Supply Noise and Its Reduction in At-Speed Scan Testing2015
- Author(s)
  X. Wen
- Organizer
  IEEE Int'l Conf. on ASIC
- Place of Presentation
  Chengdu, China
- Year and Date
  2015-11-05
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] Power Supply Noise and Its Reduction in At-Speed Scan Testing2015
- Author(s)
  X. Wen
- Organizer
  IEEE Int'l Conf. on ASIC
- Place of Presentation
  Chengdu, China
- Year and Date
  2015-11-05
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K12003
[Presentation] Identification of High Power Consuming Areas with Gate Type and Logic Level Information2015
- Author(s)
  K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara
- Organizer
  IEEE European Test Symp.
- Place of Presentation
  Cluj-Napoca, Romania
- Year and Date
  2015-05-28
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K12003
[Presentation] Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch2015
- Author(s)
  K. Asada, X. Wen, S. Holst, K. Miyase, S. Kajihara, M. A. Kochte, E. Schneider, H.-J. Wunderlich, J. Qian
- Organizer
  IEEE Asian Test Symp.
- Place of Presentation
  Bombay, India
- Year and Date
  2015-11-24
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] A Soft-Error Tolerant TCAM Using Partial Don’t-Care Keys2015
- Author(s)
  I. Syafalni, T. Sasao, X. Wen, S. Holst, K. Miyase
- Organizer
  IEEE European Test Symp.
- Place of Presentation
  Cluj-Napoca, Romania
- Year and Date
  2015-11-05
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] On Guaranteeing Capture Safety in At-Speed Scan Testing With Broadcast-Scan-Based Test Compression2013
- Author(s)
  K. Enokimoto, X. Wen, K. Miyase, J.-L. Huang, S. Kajihara, L.-T. Wang
- Organizer
  26th Intl. Conf. on VLSI Design
- Place of Presentation
  Pune, India
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST2013
- Author(s)
  A. Tomita, X. Wen, Y. Sato, S. Kajihara, P. Girard, M. Tehranipoor, L.-T. Wang
- Organizer
  IEEE Asian Test Symp.
- Place of Presentation
  Yilan, Taiwan
- Data Source
  KAKENHI-PROJECT-24650022
[Presentation] Low-Power LSI Testing2013
- Author(s)
  X. Wen
- Organizer
  The 13th International Workshop on Microelectronics Assembling and Packaging
- Place of Presentation
  Fukuoka, Japan
- Invited
- Data Source
  KAKENHI-PROJECT-24650022
[Presentation] Controllability Analysis of Local Switching Activity for Layout Design2013
- Author(s)
  K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara
- Organizer
  Workshop on Design and Test Methodologies for Emerging Technologies
- Place of Presentation
  Avignon, France
- Data Source
  KAKENHI-PROJECT-24650022
[Presentation] Controllability Analysis of Local Switching Activity for Layout Design2013
- Author(s)
  K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara
- Organizer
  Workshop on Design and Test Methodologies for Emerging Technologies
- Place of Presentation
  Avignon, France
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] Low-Power LSI Testing2013
- Author(s)
  X. Wen
- Organizer
  The 13th International Workshop on Microelectronics Assembling and Packaging
- Place of Presentation
  Fukuoka, Japan
- Invited
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] Power-Aware Testing: The Next Stage2013
- Author(s)
  X. Wen
- Organizer
  Taiwan Tech and Kyutech Advanced VLSI Testing Workshop
- Place of Presentation
  Taipei, Taiwan
- Invited
- Data Source
  KAKENHI-PROJECT-24650022
[Presentation] ATPG Enhancement Technology2013
- Author(s)
  N.A. Zakaria, M.Z Khalid, X. Wen
- Organizer
  IEEE Workshop on RTL and High Level Testing
- Place of Presentation
  Yilan, Taiwan
- Data Source
  KAKENHI-PROJECT-24650022
[Presentation] ロジック BIST のキャプチャ電力安全性に関する研究2013
- Author(s)
  冨田明宏, 温暁青, 宮瀬紘平, 梶原誠司
- Organizer
  第68回 FTC 研究会
- Place of Presentation
  秋田市
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST2013
- Author(s)
  A. Tomita, X. Wen, Y. Sato, S. Kajihara, P. Girard, M. Tehranipoor, L.-T. Wang
- Organizer
  IEEE Asian Test Symp.
- Place of Presentation
  Yilan, Taiwan
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] SafeTIDE: A Technique for Transition Isolation Scan Cells Hardware Overhead Reduction2013
- Author(s)
  Y.-T. Lin, J.-L. Huang, X. Wen
- Organizer
  VLSI Test Technology Workshop
- Place of Presentation
  New Taipei City, Taiwan
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] Power-Aware Testing: The Next Stage2013
- Author(s)
  X. Wen
- Organizer
  Taiwan Tech and Kyutech Advanced VLSI Testing Workshop
- Place of Presentation
  Taipei, Taiwan
- Invited
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] Search Space Reduction for Low-Power Test Generation2013
- Author(s)
  K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara
- Organizer
  IEEE Asian Test Symp.
- Place of Presentation
  Yilan, Taiwan
- Data Source
  KAKENHI-PROJECT-24650022
[Presentation] SafeTIDE: A Technique for Transition Isolation Scan Cells Hardware Overhead Reduction2013
- Author(s)
  Y.-T. Lin, J.-L. Huang, X. Wen
- Organizer
  VLSI Test Technology Workshop
- Place of Presentation
  New Taipei City, Taiwan
- Data Source
  KAKENHI-PROJECT-24650022
[Presentation] On Guaranteeing Capture Safety in At-Speed Scan Testing With Broadcast-Scan-Based Test Compression2013
- Author(s)
  K. Enokimoto, X. Wen, K. Miyase, J.-L. Huang, S. Kajihara, and L.-T. Wang
- Organizer
  Proc. 26th Intl. Conf. on VLSI Design
- Place of Presentation
  Pune, India
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Search Space Reduction for Low-Power Test Generation2013
- Author(s)
  K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara
- Organizer
  IEEE Asian Test Symp.
- Place of Presentation
  Yilan, Taiwan
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] ATPG Enhancement Technology2013
- Author(s)
  N.A. Zakaria, M.Z Khalid, X. Wen
- Organizer
  IEEE Workshop on RTL and High Level Testing
- Place of Presentation
  Yilan, Taiwan
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] New Test Partition Approach for Segmented Testing with Lower System Failure Rate2012
- Author(s)
  S.Wang, S.Kajihara, Y.Sato, K.Miyase, Xiaoqing Wen
- Organizer
  第66回FTC研究会
- Place of Presentation
  大分県ホテルソラージュ大分・日出
- Year and Date
  2012-01-19
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] A Transition Isolation Scan Cell Design for Low Shift and Capture Power2012
- Author(s)
  Y.-T. Lin, J.-L Huang, X. Wen
- Organizer
  IEEE Asian Test Symp.
- Place of Presentation
  Niigata, Japan
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] ネットリストを用いたドントケアビット数の見積り手法に関する研究2012
- Author(s)
  宮瀬紘平, 梶原誠司, 温暁青
- Organizer
  電子情報通信学会技術研究報告
- Place of Presentation
  福岡市
- Year and Date
  2012-11-28
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] Power-Aware Testing: The Next Stage2012
- Author(s)
  X. Wen
- Organizer
  IEEE European Test Symposium
- Place of Presentation
  Annecy, France
- Invited
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] New Test Partition Approach for Rotating Test with Lower Rate2012
- Author(s)
  S.Wang, S.Kajihara, Y.Sato, K.Miyase, X.Wen
- Organizer
  FTC研究会
- Place of Presentation
  日本大分県
- Year and Date
  2012-01-19
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Towards the Next-Generation Power-Aware Testing Technologies2012
- Author(s)
  X. Wen
- Organizer
  CMOS Emerging Technologies Conference
- Place of Presentation
  Vancouver, Canada
- Invited
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Fault Detection with Optimum March Test Algorithm2012
- Author(s)
  N.A.Zakariz, W.Z.W.Hasan, I.A.Halin, R.M.Sidek, X.Wen
- Organizer
  IEEE International Conference on Intelligent Systems, Modeling and Simulation
- Place of Presentation
  Kota Kinabalu, Malaysia
- Year and Date
  2012-02-08
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] A Transition Isolation Scan Cell Design for Low Shift and Capture Power2012
- Author(s)
  Y. -T. Lin, J. -L Huang, and X. Wen
- Organizer
  Proc. IEEE Asian Test Symp
- Place of Presentation
  Niigata, Japan
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Estimation of the Amount of Don't-Care Bits in Test Vectors2012
- Author(s)
  K. Miyase, S. Kajihara, X. Wen
- Organizer
  IEEE Workshop on RTL and High Level Testing
- Place of Presentation
  Niigata, Japan
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] On Pinpoint Capture Power Management in At-Speed Scan Test Generation2012
- Author(s)
  X. Wen, Y. Nishida, K. Miyase, S. Kajihara, P. Girard, M. Tehranipoor, L.-T. Wang
- Organizer
  IEEE Int'l Test Conf.
- Place of Presentation
  Anaheim, USA
- Data Source
  KAKENHI-PROJECT-24650022
[Presentation] New Test Partition Approach for Segmented Testing with Lower System Failure Rate2012
- Author(s)
  Senling Wang, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen
- Organizer
  第66回 FTC 研究会
- Place of Presentation
  大分
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] 実速度スキャンテストにおける高品質なキャプチャ安全性保障型テスト生成について2012
- Author(s)
  西田優一郎, 温暁青, 工藤雅幸, 宮瀬紘平, 梶原誠司
- Organizer
  FTC研究会
- Place of Presentation
  日本大分県
- Year and Date
  2012-01-21
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] A Novel Capture-Safety Checking Method for Multi-Clock Designs and Accuracy Evaluation with Delay Capture Circuits2012
- Author(s)
  K. Miyase, M. Aso, R. Ootsuka, X. Wen, H. Furukawa, Y. Yamato, K, Enokimoto, S. Kajihara
- Organizer
  IEEE VLSI Test Symp.
- Place of Presentation
  Hawaii, USA
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Estimation of the Amount of Don' t-Care Bits in Test Vectors2012
- Author(s)
  K. Miyase, S. Kajihara, and X. Wen
- Organizer
  Proc. IEEE Workshop on RTL and High Level Testing
- Place of Presentation
  Niigata, Japan
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] A Novel Capture-Safety Checking Method for Multi-Clock Designs and Accuracy Evaluation with Delay Capture Circuits2012
- Author(s)
  K. Miyase, M. Aso, R. Ootsuka, X. Wen, H. Furukawa, Y. Yamato, K, Enokimoto, and S. Kajihara
- Organizer
  Proc. IEEE VLSI Test Symp.
- Place of Presentation
  Hawaii, USA
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] A Transition Isolation Scan Cell Design for Low Shift and Capture Power2012
- Author(s)
  Y. -T. Lin, J. -L. Huang, and X. Wen
- Organizer
  Proc. VLSI Test Technology Workshop
- Place of Presentation
  Yilan, Taiwan
- Year and Date
  2012-01-10
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] A Transition Isolation Scan Cell Design for Low Shift and Capture Power2012
- Author(s)
  Y.-T. Lin, J.-L Huang, X. Wen
- Organizer
  VLSI Test Technology Workshop
- Place of Presentation
  Yilan, Taiwan
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] VLSI Testing and Test Power2011
- Author(s)
  X. Wen
- Organizer
  Proc. Workshop on Low Power System on Chip (SoC)
- Place of Presentation
  Orlando, USA
- Year and Date
  2011-07-28
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Additional Path Delay Fault Detection with Adaptive Test Data2011
- Author(s)
  K.Miyase, H.Tanaka, K.Enokimoto, X.Wen, S.Kajihara
- Organizer
  IEEE Workshop on RTL and High Level Testing
- Place of Presentation
  Jaipur, India
- Year and Date
  2011-11-26
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Power Reduction Through X-filling of Transition Fault Test Vectors for LOS Testing2011
- Author(s)
  F.Wu, L.Dilillo, A.Bosio, P.Girard, S.Pravossoudovitch, A.Virazel, M.Tehranipoor, K.Miyase, X.Wen, N.Ahmed
- Organizer
  6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era
- Place of Presentation
  Athens, Grace
- Year and Date
  2011-04-06
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Mapping Test Power to Functional Power Through Smart X-Filling for LOS Scheme2011
- Author(s)
  F.Wu, L.Dilillo, A.Bosio, P.Girard, M.Tehranipoor, K.Miyase, X.Wen, N.Ahmed
- Organizer
  IEEE Intl.Workshop on Impact of Low-Power design on Test and Reliability
- Place of Presentation
  Trodheim, Norway
- Year and Date
  2011-05-27
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] A Novel Scan Segmentation Design Method for Avoiding Shift Timing Failure in Scan Testing2011
- Author(s)
  Y. Yamato, X. Wen, M. A. Kochte, K. Miyase, S. Ka j ihara, and L. -T. Wang
- Organizer
  Proc. IEEE Intl. Test Conf.
- Place of Presentation
  Anaheim, USA
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] SAT-based Capture-Power Reduction for At-Speed Broadcast-Scan-Based Test Compression Architectures2011
- Author(s)
  M.A.Kochte, K.Miyase, X.Wen, S.Kajihara, Y.Yamato, K.Enokimoto, H.-J.Wunderlich
- Organizer
  IEEE International Symposium on Low Power Electronics and Design
- Place of Presentation
  Fukuoka, Japan
- Year and Date
  2011-08-01
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Power-Aware Test Pattern Generation for At-Speed LOS Testing2011
- Author(s)
  A.Bosio, L.Dilillo, P.Girard, A.Todri, A.Virazel, K.Miyase, X.Wen
- Organizer
  IEEE Asian Test Symposium
- Place of Presentation
  New Delhi, India
- Year and Date
  2011-11-23
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] 実速度テストに対する品質考慮ドントケア判定2011
- Author(s)
  河野潤, 宮瀬紘平, 榎元和成, 大和勇太, 温暁青, 梶原誠司
- Organizer
  第64回FTC研究会
- Place of Presentation
  岐阜県恵那市
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] 実速度テストに対する品質考慮ドントケア判定2011
- Author(s)
  河野潤, 宮瀬紘平,榎元和成,大和勇太,温暁青, 梶原誠司
- Organizer
  第64回FTC研究会
- Place of Presentation
  恵那市
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] VLSI Testing and Test Power2011
- Author(s)
  X.Wen
- Organizer
  IEEE Workshop on Low Power System on Chip (SoC)
- Place of Presentation
  Orlando, USA(招待講演)
- Year and Date
  2011-07-28
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] SAT-based Capture-Power Reduction for At-Speed Broadcast-Scan-Based Test Compression Architectures2011
- Author(s)
  M. A. Kochte, K. Miyase, X. Wen, S. Ka j ihara, Y. Yamato, K. Enokimoto, and H.-J. Wunderlich
- Organizer
  Proc. IEEE Intl. Symp. on Low Power Electronics and Design
- Place of Presentation
  Fukuoka, Japan
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Additional Path Delay Fault Detection with Adaptive Test Data2011
- Author(s)
  K. Miyase, H. Tanaka, K. Enokimoto, X. Wen, and S. Kajihara
- Organizer
  Proc. IEEE Workshop on RTL and High Level Testing
- Place of Presentation
  Jaipur, India
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Effective Launch Power Reduction for Launch-Off-Shift Scheme with Adjacent-Probability-Based X-Filling2011
- Author(s)
  K. Miyase, U. Uchinodan, K. Enokimoto, Y. Yamato, X. Wen, S. Kajihara, F. Wu, L. Dilillo, A. Bosio, and P. Girard
- Organizer
  Proc. IEEE Asian Test Symp.
- Place of Presentation
  New Delhi, India
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Efficient BDD-based Fault Simulation in Presence of Unknown Values2011
- Author(s)
  M.A.Kochte, S.Rundu, K.Miyase, X.Wen, H.-J.Wunderlich
- Organizer
  IEEE Asian Test Symposium
- Place of Presentation
  New Delhi, India
- Year and Date
  2011-11-23
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Power-Aware Test Generation with Guaranteed Launch Safety for At-Speed Scan Testing2011
- Author(s)
  X.Wen, K.Enokimoto, K.Miyase, Y.Yamato, M.Kochte, S.Kajihara, P.Girard, M.Tehranipoor
- Organizer
  IEEE VLSI Test Symposium
- Place of Presentation
  Dana Point, USA
- Year and Date
  2011-05-03
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Effective Launch Power Reduction for Launch-Off-Shift Scheme with Adjacent-Probability-Based X-Filling2011
- Author(s)
  K.Miyase, U.Uchinodan, K.Enokimoto, Y.Yamato, X.Wen, S.Kajihara, F.Wu, L.Dilillo, A.Bosio, P.Girard
- Organizer
  IEEE Asian Test Symposium
- Place of Presentation
  New Delhi, India
- Year and Date
  2011-11-22
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Power-Aware Test Generation with Guaranteed Launch Safety for At-Speed Scan Testing2011
- Author(s)
  X. Wen, K. Enokimoto, K. Miyase, Y. Yamato, M. Kochte, S. Ka j ihara, P. Girard, and M. Tehranipoor
- Organizer
  Proc. IEEE VLSI Test Symp.
- Place of Presentation
  Dana Point, USA
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Efficient BDD-based Fault Simulation in Presence of Unknown Values2011
- Author(s)
  M. A. Kochte, S. Kundu, K. Miyase, X. Wen, and H. -J. Wunderlich
- Organizer
  Proc. IEEE Asian Test Symp.
- Place of Presentation
  New Delhi, India
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of TDF Patterns2011
- Author(s)
  H.Salmani, W.Zhao, M.Tehranipoor, S.Chacravarty, X.Wen
- Organizer
  IEEE Intl.Workshop on Impact of Low-Power design on Test and Reliability
- Place of Presentation
  Trodheim, Norway
- Year and Date
  2011-05-27
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Clock-Gating-Aware Low Launch WSA Test Pattern Generation for At-Speed Scan Testing2011
- Author(s)
  Y. -T. Lin, J. -L. Huang, and X. Wen
- Organizer
  Proc. IEEE Intl. Test Conf.
- Place of Presentation
  Anaheim, USA
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Towards the Next Generation of Low-Power Test Technologies2011
- Author(s)
  X. Wen
- Organizer
  Proc. IEEE Int' 1. Conf. on ASIC
- Place of Presentation
  Hong Kong, China
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] 3値テストパターンに対する遅延テスト品質計算とX割当について2010
- Author(s)
  奥慎治, 梶原誠司, 佐藤康夫, 宮瀬紘平, 温暁青
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  東京都
- Year and Date
  2010-02-15
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] Power-Aware Test for Low-Power LSI Circuits2010
- Author(s)
  X.Wen
- Organizer
  CMOS Emerging Technologies Workshop
- Place of Presentation
  Whistler, Canada
- Year and Date
  2010-05-19
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Power-Aware Test for Low-Power LSI Circuits2010
- Author(s)
  X.Wen
- Organizer
  International Workshop on Microelectronics Assembling and Packaging
- Place of Presentation
  Fukuoka, Japan
- Year and Date
  2010-11-18
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Power-Aware Test for Low-Power Devices2010
- Author(s)
  X.Wen
- Organizer
  IEEE Workshop on RTL and High Level Testing
- Place of Presentation
  Shanghai, China
- Year and Date
  2010-12-05
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Low-Aware Test for Low-Power Devices2010
- Author(s)
  X.Wen
- Organizer
  IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
- Place of Presentation
  Kyoto, Japan
- Year and Date
  2010-10-07
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Towards the Next Generation of Low-Power Test Technologies2010
- Author(s)
  X.Wen
- Organizer
  IEEE International Test on ASIC
- Place of Presentation
  Amoi, China(招待講演)
- Year and Date
  2010-10-27
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Clock-Gating-Aware Low Launch WSA Test Pattern Generation for At-Speed Scan Testing2010
- Author(s)
  Y.-T.Lin, J.-L.Huang, X.Wen
- Organizer
  IEEE International Test Conference
- Place of Presentation
  Anaheim, USA
- Year and Date
  2010-09-20
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] A Path Selection Method for Delay Test Targeting Transistor Aging2010
- Author(s)
  M.Noda, S.Kajihara, Y.Sato, K.Miyase, X.Wen, Y.Miura
- Organizer
  IEEE International Workshop on Reliability Aware System Design and Test
- Place of Presentation
  Bangalore, India
- Year and Date
  2010-01-08
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] X-Identification of Transition Delay Fault Tests for Launch-off Shift Scheme2010
- Author(s)
  K.Miyase, F.Wu, L.Dilillo, A.Bosio, P.Girard, X.Wen, S.Kajihara
- Organizer
  IEEE Workshop on RTL and High Level Testing
- Place of Presentation
  Shanghai, China
- Year and Date
  2010-12-06
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Architectures for Testing 3D Chips Using Time-Division Demultiplexing/Multiplexing2010
- Author(s)
  L.-T.Wang, N.A.Touba, M.S.Hsiao, J.-L.Huang, C.-M.Li, S.Wu, X.Wen, M.Bhattarai, F.Li, Z.Jiang
- Organizer
  IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits
- Place of Presentation
  Anaheim, USA
- Year and Date
  2010-09-23
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] A Path Selection Method for Delay Test Targeting Transistor Aging2010
- Author(s)
  Mitsumasa Noda, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen, Yukiya Miura
- Organizer
  Digest of IEEE International Workshop on Reliability Aware System Design and Test
- Place of Presentation
  Bangalore, India
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] CAT(Critical-Area-Targeted) : A New Paradigm for Reducing Yield Loss Risk in At-Speed Scan Testing2010
- Author(s)
  X.Wen, K.Enokimoto, K.Miyase, S.Kajihara, M.Aso, H.Furukawa
- Organizer
  Symposium II(ISTC/CSTIC) : Metrology, Reliability and Testing
- Place of Presentation
  Shanghai, China
- Year and Date
  2010-03-19
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] 3 値テストパターンに対する遅延テスト品質計算と X 割当について2010
- Author(s)
  奥慎治, 梶原誠司, 佐藤康夫 ,宮瀬紘平, 温暁青
- Organizer
  電子情報通信学会技術研究報告
- Place of Presentation
  東京
- Year and Date
  2010-02-15
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] Test Power Reduction : From Artillery Fire to Sniper Fire2010
- Author(s)
  X.Wen
- Organizer
  International Workshop on the Impact of Low-Power Design on Test and Reliability
- Place of Presentation
  Prague, Czech
- Year and Date
  2010-05-27
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] Low-Capture-Power Post-Processing Test Vectors for Test Compression Using SAT Solver2010
- Author(s)
  K K.Miyase, M.A.Kochte, X.Wen, S.Kajihara, H.-J.Wunderlich
- Organizer
  IEEE Workshop on Defect and Date Driven Testing
- Place of Presentation
  Austin, USA
- Year and Date
  2010-11-05
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] A Novel Scan Segmentation Design Method for Avoiding Shift Timing Failure in Scan Testing2010
- Author(s)
  Y.Yamato, X.Wen, M.A.Kochte, K.Miyase, S.Kajihara, L.-T.Wang
- Organizer
  IEEE International Test Conference
- Place of Presentation
  Anaheim, USA
- Year and Date
  2010-09-21
- Data Source
  KAKENHI-PROJECT-22300017
[Presentation] A Path Selection Method for Delay Test Targeting Transistor Aging2010
- Author(s)
  M.Noda, S.Kajihara, Y.Sato, K.Miyase, X.Wen, Y.Miura
- Organizer
  IEEE Int' 1 Workshop on Reliability Aware System Design and Test
- Place of Presentation
  Bangalore, India
- Year and Date
  2010-01-08
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] 部分X分解によるX故障モデルを用いた故障診断手法の高速化2010
- Author(s)
  宮瀬紘平, 中村優介, 大和勇太, 温暁青, 梶原誠司
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  東京都
- Year and Date
  2010-02-15
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] A Path Selection Method for Delay Test Targeting Transistor Aging2010
- Author(s)
  M. Noda, S. Kajihara, Y. Sato, K. Miyase, X. Wen, Y. Miura
- Organizer
  Digest of First IEEE Int'l Workshop on Reliability Aware System Design and Test
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] 部分X分解によるX故障モデルを用いた故障診断手法の高速化2010
- Author(s)
  宮瀬紘平, 中村優介, 大和勇太, 温暁青, 梶原誠司
- Organizer
  電子情報通信学会技術研究報告
- Place of Presentation
  東京
- Year and Date
  2010-02-15
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] フィールドテストにおける巡回テストとテスト集合印加順序について2010
- Author(s)
  広実一輝, 梶原誠司, 佐藤康夫, 宮瀬紘平, 温暁青
- Organizer
  第62回FTC研究会
- Place of Presentation
  岡山県総社市
- Year and Date
  2010-01-21
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] フィールドテストにおける巡回テストとテスト集合印加順序について2010
- Author(s)
  広実一輝, 梶原誠司, 佐藤康夫, 宮瀬紘平, 温暁青
- Organizer
  第62回FTC研究会
- Place of Presentation
  総社市
- Year and Date
  2010-01-21
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] Power-Aware Test Generation for Reducing Yield Loss Risk in At-Speed Scan Testing2009
- Author(s)
  Y. Yainato, X. Wen, K. Miyase, H. Furukawa, S. Rajihara
- Organizer
  Symposium II (ISTC/CSTIC) : Metrology, Reliability and Testing
- Place of Presentation
  Shanghai, China
- Year and Date
  2009-03-20
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] X-Identification According to Required Distribution for Industrial Circuits2009
- Author(s)
  I.Beppu, K.Miyase, Y.Yamato, X.Wen
- Organizer
  IEEE Workshop on RTL and High Level Testing,
- Place of Presentation
  Hong Kong
- Year and Date
  2009-11-27
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing2009
- Author(s)
  K. Enokimoto, X. Wen, Y. Yamato, K. Miyase, H. Sone, S. Kajihara, M. Aso, H. Furukawa
- Organizer
  Proc. IEEE Asian Test Symp.
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] On Calculation of Delay Range in Fault Simulation for Test Cubes2009
- Author(s)
  S. Oku, S. Kajihara, K. Miyase, X. Wen, Y. Sato
- Organizer
  Proc. Int'l Symp. on VLSI Design, Automation, and Test
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] On Calculation of Delay Range in Fault Simulation for Test Cubes2009
- Author(s)
  S.Oku, S.Kajihara, K.Miyase, X.Wen, Y.Sato
- Organizer
  Int' 1 Symp.on VLSI Design, Automation, and Test
- Place of Presentation
  Hsinchu, Taiwan
- Year and Date
  2009-04-29
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] ブロードキャストスキャン圧縮環境下における実速度テストに対するIR-Drop削減Post-ATPG手法2009
- Author(s)
  宮瀬紘平, 大和勇太, 埜田健治, 伊藤秀昭, 畠山一実, 相京隆, 温暁青, 梶原誠司
- Organizer
  第61回FTC研究会
- Place of Presentation
  三重県多気郡大台町
- Year and Date
  2009-07-18
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] A Novel Post-ATPG IR-Drop Reduction Scheme for At-Speed Scan Testing in Broadcast-Scan-Based Test Compression Environment2009
- Author(s)
  K.Miyase, K.Noda, H.Ito, K.Hatayama, T.Aikyo, Y.Yamato, X.Wen, S.Kajihara
- Organizer
  IEEE/ACM Int'1 Conf.on Computer Aided Design
- Place of Presentation
  San Jose, USA
- Year and Date
  2009-11-02
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] CAT : A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing2009
- Author(s)
  K.Enokimoto, X.Wen, Y.Yamato, K.Miyase, H.Sone, S.Kajihara, M.Aso, H.Furukawa
- Organizer
  IEEE Asian Test Symp.
- Place of Presentation
  Taichung, Taiwan
- Year and Date
  2009-11-24
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] On Calculation of Delay Range in Fault Simulation for Test Cubes2009
- Author(s)
  Y.Yamato, X.Wen, K.Miyase, H.Furukawa, S.Kajihara
- Organizer
  IEEE 15th Pacific Rim Int' 1 Symp.on Dependable Computing, Automation, and Test
- Place of Presentation
  Shanghai, China
- Year and Date
  2009-11-17
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] A Novel Post-ATPG IR-Drop Reduction Scheme for At-Speed Scan Testing in Broadcast-Scan-Based Test Compression Environment2009
- Author(s)
  K. Miyase, K. Noda, H. Ito, K. Hatayama, T. Aikyo, Y. Yamato, X. Wen, S. Kajihara
- Organizer
  Proc. IEEE/ACM Int'l Conf. on Computer Aided Design
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] 信号値遷移削減のためのドントケア判定率の最適化に関する研究2009
- Author(s)
  別府厳,宮瀬紘平,大和勇太,温暁青,梶原誠司
- Organizer
  電子情報通信学会技術研究報告
- Place of Presentation
  高知市
- Year and Date
  2009-10-04
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] 劣化検知テストにおけるパス選択について2009
- Author(s)
  野田光政, 梶原誠司, 佐藤康夫, 宮瀬紘平, 温暁青, 三浦幸也
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  高知市
- Year and Date
  2009-12-05
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] X-Identification According to Required Distribution for Industrial Circuits2009
- Author(s)
  I.Beppu, K.Miyase, Y.Yamato, X.Wen, S.Kajihara
- Organizer
  IEEE Workshop on RTL and High Level Testing
- Place of Presentation
  Hong Kong
- Year and Date
  2009-11-27
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] X-Identification According to Required Distribution for Industrial Circuits2009
- Author(s)
  I. Beppu, K. Miyase, Y. Yamato, X. Wen, S. Kajihara
- Organizer
  Proc. IEEE Workshop on RTL and High Level Testing
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] 信号値遷移削減のためのドントケア判定率の最適化に関する研究2009
- Author(s)
  別府厳, 宮瀬紘平, 大和勇太, 温暁青, 梶原誠司
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  高知市
- Year and Date
  2009-12-04
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] On Calculation of Delay Range in Fault Simulation for Test Cubes2009
- Author(s)
  Y. Yamato, X. Wen, K. Miyase, H. Furukawa, S. Kajihara
- Organizer
  Proc. IEEE 15th Pacific Rim Int'l Symp. on Dependable Computing, Automation, and Test
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] 劣化検知テストにおけるパス選択について2009
- Author(s)
  野田光政, 梶原誠司, 佐藤康夫, 宮瀬紘平, 温暁青, 三浦幸也
- Organizer
  電子情報通信学会技術研究報告
- Place of Presentation
  高知市
- Year and Date
  2009-10-05
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] Optimizing the Percentage of X-Bits to Reduce Switching Activity2009
- Author(s)
  I.Beppu, K.Miyase, Y.Yamato, X.Wen, S.Kajihara
- Organizer
  IEEE International Workshop on Defect and Data Driven Testing
- Place of Presentation
  Austin, TX, USA
- Year and Date
  2009-11-06
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] X-Identification According to Required Distribution for Industrial Circuits2009
- Author(s)
  Isao Beppu, Kohei Miyase, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara
- Organizer
  IEEE Workshop on RTL and High Level Testing
- Place of Presentation
  Hong, Kong
- Year and Date
  2009-10-27
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] Optimizing the Percentage of X-Bits to Reduce Switching Activity2009
- Author(s)
  Isao Beppu, Kohei Miyase, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara
- Organizer
  IEEE International Workshop on Defect and Data Driven Testing
- Place of Presentation
  USA
- Year and Date
  2009-10-06
- Data Source
  KAKENHI-PROJECT-21300015
[Presentation] A Capture- Safe Test Generation Scheme for At-Speed Scan Testing2008
- Author(s)
  X. Wen, K. Miyase, S. Kajihara, H. Furukawa, Y. Yamato, A. Takashima, K. Noda, H. Ito, K. Hatayama, T. Aikyo, K.K. Saluja
- Organizer
  Proc. IEEE European Test Symp.
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] Effective IR-Drop Reduction in At-Speed Scan Testing Using Distribution-Controlling X-Identification2008
- Author(s)
  K. Miyase, K. Noda, H. Ito, K. Hatayama, T. Aikyo, Y. Yamato, H. Furukawa, X. Wen, S. Kajihara
- Organizer
  IEEE/ACM Int'l Conf. on Computer Aided Design
- Place of Presentation
  San Jose, USA
- Year and Date
  2008-11-10
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] GA-Based X-Filling for Reducing Launch Switching Activity in At-Speed Scan Testing2008
- Author(s)
  Y. Yamato, X. Wen, K. Miyase, H. Furukawa, S. Kajihara
- Organizer
  Proc. IEEE Int'l Workshop on Defect Based Testing
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing2008
- Author(s)
  M. -F. Wu, J. -L. Huang, X. Wen, K. Miyase
- Organizer
  Proc. IEEE Int'l Test Conf.
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] Effective IR-Drop Reduction in At-Speed Scan Testing Using Distribution-Controlling X-Identification2008
- Author(s)
  K. Miyase, K. Noda, H. Ito, K. Hatayama, T. Aikyo, Y. Yamato, H. Furukawa, X. Wen, S. Kajihara
- Organizer
  Proc. IEEE/ACM Int'l Conf. on Computer Aided Design
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] Identification of IR-drop Hot-spots in Defective Power Distribution Network Using TDF ATPG2008
- Author(s)
  J. Ma, J. Lee, M. Tehranipoor, X. Wen, A. Crouch
- Organizer
  Proc. IEEE Int'l Workshop on Defect Based Testing
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing2008
- Author(s)
  Meng-Fan Wu, Jiun-Lang Huang, Xiaoqing Wen, Kohei Miyase
- Organizer
  IEEE International Test Conference
- Place of Presentation
  Santa Clara, USA
- Year and Date
  2008-10-29
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] Identification of IR-drop Hot-spots in Defective Power Distribution Network Using TDF ATPG2008
- Author(s)
  J. Ma, J. Lee, M. Tehranipoor, X. Wen, A. Crouch
- Organizer
  IEEE Workshop on Defect and Date Driven Testing (D3T)
- Place of Presentation
  Santa Clara, USA
- Year and Date
  2008-10-30
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] GA-Based X-Filling for Reducing Launch Switching Activity in At-Speed Scan Testing2008
- Author(s)
  Y. Yamato, X. Wen, K. Miyase, H. Furukawa, S. Kajihara
- Organizer
  IEEE Workshop on Defect and Date Driven Testing (D3T)
- Place of Presentation
  Santa Clara, USA
- Year and Date
  2008-10-30
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] A Capture-Safe Test Generation Scheme for At-Speed Scan Testing2008
- Author(s)
  X. Wen, K. Miyase, S. Rajihara, H. Furukawa, Y. Yamato, A. Takashima, K. Noda, H. It o, K. Hatayama, T. Aikyo, K. K. Saluia
- Organizer
  IEEE European Test Symposium
- Place of Presentation
  Verbania, Italy
- Year and Date
  2008-05-26
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] CTX: A Clock- Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing2008
- Author(s)
  H. Furukawa, X. Wen, K. Miyase, Yuta Yamato, S. Kajihara, Patrick Girard, L. -T. Wang, M. Teharanipoor
- Organizer
  Proc. IEEE Asian Test Symp.
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] CTX : A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing2008
- Author(s)
  H. Furukawa, X. Wen, K. Miyase, Yuta Yamato, S. Kajihara, Patrick Girard, L. -T. Wang, M. Teharanipoor
- Organizer
  IEEE Asian Test Symposium
- Place of Presentation
  Saporro, Japan
- Year and Date
  2008-11-27
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] A Method for Improving the Bridging Defect Coverage of a Transition Delay Test Set2007
- Author(s)
  K. Miyase, X. Wen, S. Kajihara, M. Haraguchi, H. Furukawa
- Organizer
  Proc. IEEE Int'l Workshop on Defect Based Testing
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing2007
- Author(s)
  X. Wen, K. Miyase, T. Suzuki, S. Kajihara, Y. Ohsumi, K.K. Saluja
- Organizer
  Proc. IEEE/ACM Design Automation Conf.
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] A Novel Scheme to Reduce Power Supply Noise for High-Quality At-Speed Scan Testing2007
- Author(s)
  X.Wen, K.Miyase, S.Kajihara, T.Suzuki, Y.Yamato, P.Girard, Y.Ohsumi, and L.-T.Wang
- Organizer
  Proc.IEEE Int'l Test Conf.
- Place of Presentation
  Santa Clara, USA
- Year and Date
  2007-10-25
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] Estimation of Delay Test Quality and Its Application to Test Generation2007
- Author(s)
  S.Kajihara, S.Morishima, M.Yamamoto, X.Wen, M.Fukunaga, K.Hatayama, and T.Aikyo
- Organizer
  IEEE/ACM Int'l Conf.on Computer-Aided Design
- Place of Presentation
  San Jose, USA
- Year and Date
  2007-11-06
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing2007
- Author(s)
  X.Wen, K.Miyase, T.Suzuki, S.Kajihara, Y.Ohsumi, K.K.Saluja
- Organizer
  IEEE/ACM Design Automation Conference
- Place of Presentation
  San Diego, USA
- Year and Date
  2007-06-06
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] A Novel Scheme to Reduce Power Supply Noise for High-Quality At-Speed Scan Testing2007
- Author(s)
  X. Wen, K. Miyase, S. Kajihara, T. Suzuki, Y. Yamato, P. Girard, Y. Ohsumi, L. -T. Wang
- Organizer
  Proc. IEEE Int'l Test Conf.
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] A Method for Improving the Bridging Defect Coverage of a Transition Delay Test Set2007
- Author(s)
  K.Miyase, X.Wen, S.Kajihara, M.Haraguchi, and H.Furukawa
- Organizer
  IEEE Int'l Workshop on Defect Based Testing
- Place of Presentation
  Santa Clara, USA
- Year and Date
  2007-10-26
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] Estimation of Delay Test Quality and Its Application to Test Generation2007
- Author(s)
  S. Kajihara, S. Morishima, M. Yamamoto, X. Wen, M. Fukunaga, K. Hatayama, T. Aikyo
- Organizer
  Proc. IEEE/ACM Int'l Conf. on Computer-Aided Design
- Data Source
  KAKENHI-PROJECT-19500047
[Presentation] A Soft-Error Tolerant TCAM for Multiple-Bit Flips Using Partial Don't Care Keys
- Author(s)
  I. Syafalni, T. Sasao, X. Wen
- Organizer
  24th International Conference on Logic and Synthesis
- Place of Presentation
  Mountain View, USA
- Year and Date
  2015-06-12 – 2015-06-13
- Data Source
  KAKENHI-PROJECT-24650022
[Presentation] Identification of High Power Consuming Areas with Gate Type and Logic Level Information
- Author(s)
  K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara
- Organizer
  IEEE European Test Symposium
- Place of Presentation
  Cluj-Napoca, Romania
- Year and Date
  2015-05-25 – 2015-05-29
- Data Source
  KAKENHI-PROJECT-24650022
[Presentation] A Soft-Error Tolerant TCAM Using Partial Don’t-Care Keys
- Author(s)
  I. Syafalni, T. Sasao, X. Wen, S. Holst, K. Miyase
- Organizer
  IEEE European Test Symposium
- Place of Presentation
  Cluj-Napoca, Romania
- Year and Date
  2015-05-25 – 2015-05-29
- Data Source
  KAKENHI-PROJECT-24650022
[Presentation] Data-Parallel Switch-Level Simulation for Fast and Accurate Timing Validation of CMOS Circuits
- Author(s)
  E. Schneider, S. Holst, X. Wen, H.-J. Wunderlich
- Organizer
  Design Automation Conference
- Place of Presentation
  San Francisco, USA
- Year and Date
  2014-06-01 – 2014-06-05
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] GPU-Accelerated Small Delay Fault Simulation
- Author(s)
  E. Schneider, S. Holst, M.-A. Kochte, X. Wen, H.-J. Wunderlich
- Organizer
  Design and Test in Europe
- Place of Presentation
  Grenoble, France
- Year and Date
  2015-03-09 – 2015-03-13
- Data Source
  KAKENHI-PROJECT-24650022
[Presentation] Data-Parallel Switch-Level Simulation for Fast and Accurate Timing Validation of CMOS Circuits
- Author(s)
  E. Schneider, S. Holst, X. Wen, H.-J. Wunderlich
- Organizer
  Design Automation Conference
- Place of Presentation
  San Francisco, USA
- Year and Date
  2014-06-01 – 2014-06-05
- Data Source
  KAKENHI-PROJECT-24650022
[Presentation] Data-Parallel Switch-Level Simulation for Fast and Accurate Timing Validation of CMOS Circuits
- Author(s)
  E. Schneider, S. Holst, X. Wen, H.-J. Wunderlich
- Organizer
  IEEE International Conference on Computer-Aided Design
- Place of Presentation
  San Jose, USA
- Year and Date
  2014-11-03 – 2014-11-06
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] Identification of High Power Consuming Areas with Gate Type and Logic Level Information
- Author(s)
  K. Miyase, M. Sauer, B. Becker, X. Wen, S. Kajihara
- Organizer
  IEEE European Test Symposium
- Place of Presentation
  Cluj-Napoca, Romania
- Year and Date
  2015-05-25 – 2015-05-29
- Data Source
  KAKENHI-PROJECT-25280016
[Presentation] Soft-Error Tolerant TCAMs for High-Reliability Packet Classification
- Author(s)
  I. Syafalni, T. Sasao, X. Wen, S. Holst, K. Miyase
- Organizer
  IEEE Asia Pacific Conference on Circuits and Systems
- Place of Presentation
  Ishigaki Island, Japan
- Year and Date
  2014-11-17 – 2014-11-20
- Data Source
  KAKENHI-PROJECT-24650022
[Presentation] Data-Parallel Switch-Level Simulation for Fast and Accurate Timing Validation of CMOS Circuits
- Author(s)
  E. Schneider, S. Holst, X. Wen, H.-J. Wunderlich
- Organizer
  IEEE International Conference on Computer-Aided Design
- Place of Presentation
  San Jose, USA
- Year and Date
  2014-11-02 – 2014-11-06
- Data Source
  KAKENHI-PROJECT-24650022

1. KAJIHARA Seiji (80252592)

# of Collaborated Projects: 10 results

# of Collaborated Products: 133 results
2. MIYASE Kohei (30452824)

# of Collaborated Projects: 7 results

# of Collaborated Products: 107 results
3. Holst Stefan (40710322)

# of Collaborated Projects: 4 results

# of Collaborated Products: 34 results
4. Tehranipoor M.

# of Collaborated Projects: 2 results

# of Collaborated Products: 1 results
5. Girard P.

# of Collaborated Projects: 2 results

# of Collaborated Products: 1 results
6. KINOSHITA Kozo

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
7. AIKYO Takashi

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
8. TAKAGI Noriaki

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
9. HAMADA Shuji

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
10. HADATE Koji

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
11. Saluja K. K.

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
12. Keller B.

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
13. Varma P.

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
14. Chakravarty K.

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
15. Wunderlich H.-J.

# of Collaborated Projects: 1 results

# of Collaborated Products: 2 results
16. Wang L.-T.

# of Collaborated Projects: 1 results

# of Collaborated Products: 2 results
17. Jan M. E.

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
18. 笹尾勤

# of Collaborated Projects: 0 results

# of Collaborated Products: 1 results

Wen Xiaoqing 温 暁青

WEN Xiaoqing 温 暁青

温 暁青 オン ギョウセイ

Research Projects

Research Products

Co-Researchers

Research on Defect-Aware Soft-Error Mitigation for Reliable LSIsPrincipal Investigator

Principal Investigator

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Research Category

Review Section

Research Institution

Shift-Power-Safe Scan Test Methodology for High-Quality Low-Power LSI CircuitsPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Research on High-Quality Test Method for Avoiding False Testing of Next-Generation Low-Power LSIsPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Research on Extra-Low-Power Self-Test for LSI Circuits in Implantable Medical DevicesPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Research on Logic Switching Activity Balanced Test for High-Quality Low-Cost LSIsPrincipal Investigator

Principal Investigator

Project Period (FY)

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Power Adjustment Testing for Next-Generation Low-Power LSI CircuitsPrincipal Investigator

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A study on high quality field test for VLSIs

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Research on Advanced VLSI Test for Avoiding Signal DegradationPrincipal Investigator

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Research on False Test Avoidance for LSI Yield ImprovementPrincipal Investigator

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Study on LSI testing for multiple fault models

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VLSIの電流テスト容易化設計と電流波形による故障検出に関する研究Principal Investigator

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[Book] Chapter 9 "Low-Power Testing for 2D/3D Devices and Systems" in Design of 3D Integrated Circuits and Systems2014

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[Book] はかる×わかる半導体-入門編2013

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Publisher

Wen Xiaoqing 温暁青

WEN Xiaoqing 温暁青

温暁青オンギョウセイ