Ishihara Tohru 石原亨

… Alternative Names

石原亨イシハラトオル

ISHIHARA Tohru 石原亨

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Researcher Number	30323471
Other IDs	https://orcid.org/0000-0002-1650-9958
External Links
Affiliation (Current)	2026: 名古屋大学, 情報学研究科, 教授
Affiliation (based on the past Project Information) *help	2017 – 2026: 名古屋大学, 情報学研究科, 教授 2014 – 2017: 京都大学, 情報学研究科, 准教授 2011: Kyushu University, 准教授 2008 – 2009: Kyushu University, システムLSI研究センター, 准教授 2002: 東京大学, 大規模集積システム設計教育研究センター, 助手 2001: 東京大学, 大規模集積システム・設計教育研究センター, 助手 2000: Univ.of Tokyo, VDEC, Research Associate, 大規模集積システム設計教育研究センター, 助手
Review Section/Research Field	Principal Investigator Computer system / Broad Section J / Computer system/Network / Medium-sized Section 60:Information science, computer engineering, and related fields / Basic Section 60040:Computer system-related / Information science, computer engineering, and related fields / 電子デバイス・機器工学 Except Principal Investigator Computer system / 計算機科学
Keywords	Principal Investigator 計算機システム / 省エネルギー / 低消費電力設計 / 光ニューラルネットワーク / エネルギー効率化 / 低消費電力・高エネルギー密度 / 高次多値変調 / AI推論 / 光トランシーバ / 光集積回路 … More / 光コンピューティング / システムオンチップ / 電子デバイス・機器 / 低消費電力 / 低消費設計技術 / 集積回路設計技術 / メモリ回路 / 設計最適化 / 光電融合回路 / マイクロプロセッサ / 環境発電 / ハイパフォーマンス・コンピューティング / フォトニック結晶 / スマートセンサ情報システム / 太陽電池 / 高信頼性 / リーク電流 / 閾値電圧 / ディープサブミクロン / SWコデザイン / HW / メモリ … More Except Principal Investigator HW / FPGA / 低消費電力化 / 低消費電力技術 / ディペンダブル・コンピューティング / 省エネルギー / 電子デバイス・機器 / オンチップモニタ / 消費エネルギー最小化 / 基板電圧制御 / 動的電圧制御 / 低電圧動作 / 低消費電力設計 / 最小エネルギー動作 / dynamic optimization / SW codesign / computer architecture / low power design / design optimization / emulation / system LSI / 分散演算 / 動的最適化 / SWコデザイン / 計算機アーキテクチャ / 設計最適化 / エミュレーション / システムLSI / 組込システム / ディペンダブルシステム / 組込みシステム / 製造容易化 / 集積回路 / システムオンチップ Less

光演算回路に基づく広帯域かつ超省エネルギー情報処理基盤の創出Principal Investigator
- Principal Investigator
  
  石原亨
- Project Period (FY)
  2026 – 2028
- Research Category
  
  Grant-in-Aid for Scientific Research (S)
- Review Section
  
  Broad Section J
- Research Institution
  Nagoya University
Highly Energy Efficient and Broadband Information Processing Platform based on Optical Functional CircuitsPrincipal Investigator
- Principal Investigator
  
  石原亨
- Project Period (FY)
  2024 – 2028
- Research Category
  
  Grant-in-Aid for Scientific Research (S)
- Review Section
  
  Broad Section J
- Research Institution
  Nagoya University
Gain Cell DRAMを活用する超省エネルギーコンピューティング基盤の創出Principal Investigator
- Principal Investigator
  
  石原亨
- Project Period (FY)
  2024 – 2025
- Research Category
  
  Grant-in-Aid for Challenging Research (Exploratory)
- Review Section
  
  Medium-sized Section 60:Information science, computer engineering, and related fields
- Research Institution
  Nagoya University
Research on architecture of optoelectronic integrated circuits and their design methodologyPrincipal Investigator
- Principal Investigator
  
  Ishihara Tohru
- Project Period (FY)
  2020 – 2022
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Nagoya University
A Study on Optical Computer Design through Photonics and Electronics Co-OptimizationPrincipal Investigator
- Principal Investigator
  
  Ishihara Tohru
- Project Period (FY)
  2017 – 2019
- Research Category
  
  Grant-in-Aid for Challenging Research (Exploratory)
- Research Field
  
  Information science, computer engineering, and related fields
- Research Institution
  Nagoya University
  Kyoto University
Research on computing infrastructure aimed at realizing an IoT society to comePrincipal Investigator
- Principal Investigator
  
  Ishihara Tohru
- Project Period (FY)
  2017 – 2019
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system
- Research Institution
  Nagoya University
LSI Design Method for Minimum Energy Operation
- Principal Investigator
  
  Onodera Hidetoshi
- Project Period (FY)
  2016 – 2019
- Research Category
  
  Grant-in-Aid for Scientific Research (A)
- Research Field
  
  Computer system
- Research Institution
  Kyoto University
A Study on Energy Harvesting Embedded Computers as a Social InfrastructurePrincipal Investigator
- Principal Investigator
  
  Ishihara Tohru
- Project Period (FY)
  2014 – 2016
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system
- Research Institution
  Kyoto University
A Study on on-chip memories suitable for near-threshold voltage operationPrincipal Investigator
- Principal Investigator
  
  Ishihara Tohru
- Project Period (FY)
  2014 – 2016
- Research Category
  
  Grant-in-Aid for Challenging Exploratory Research
- Research Field
  
  Computer system
- Research Institution
  Kyoto University
LSI design methodology that enables robust operation under the supply as low as threshold voltage by self-compensating performance variability
- Principal Investigator
  
  ONODERA Hidetoshi
- Project Period (FY)
  2013 – 2016
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system
- Research Institution
  Kyoto University
環境発電に適した組込みシステムのアーキテクチャとOS制御による電力管理技術の研究Principal Investigator
- Principal Investigator
  
  石原亨
- Project Period (FY)
  2011
- Research Category
  
  Grant-in-Aid for Young Scientists (A)
- Research Field
  
  Computer system/Network
- Research Institution
  Kyushu University
A Research on Embedded Systems Suited for Energy HarvestingPrincipal Investigator
- Principal Investigator
  
  ISHIHARA Tohru
- Project Period (FY)
  2008 – 2009
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Kyushu University
システムLSI向け低電力メモリアーキテクチャおよび設計支援技術の開発Principal Investigator
- Principal Investigator
  
  石原亨
- Project Period (FY)
  2001 – 2002
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  電子デバイス・機器工学
- Research Institution
  The University of Tokyo
Study on Design Methodologies for Scalable System-LSI Architectures
- Principal Investigator
  
  MURAKAMI Kazuaki
- Project Period (FY)
  1999 – 2000
- Research Category
  
  Grant-in-Aid for Scientific Research (A).
- Research Field
  
  計算機科学
- Research Institution
  Kyushu University

[Book] Multi-Processor System-on-Chip 1: (Chapter 10) Minimum Energy Computing via Supply and Threshold Voltage Scaling2021
- Author(s)
  Jun Shiomi, Tohru Ishihara
- Total Pages
  28
- Publisher
  Wiley - ISTE
- ISBN
  9781119818274
- Data Source
  KAKENHI-PROJECT-17H01712
[Journal Article] Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation2021
- Author(s)
  HATTORI Naoki、SHIOMI Jun、MASUDA Yutaka、ISHIHARA Tohru、SHINYA Akihiko、NOTOMI Masaya
- Journal Title
  
  IEICE Trans. Fundamentals
  
  Volume: E104.A Issue: 11 Pages: 1477-1487
- DOI
  10.1587/transfun.2020KEP0016
- NAID
  130008109846
- ISSN
  0916-8508, 1745-1337
- Year and Date
  2021-11-01
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20H04155
[Journal Article] A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits2021
- Author(s)
  MATSUO Ryosuke、SHIOMI Jun、ISHIHARA Tohru、ONODERA Hidetoshi、SHINYA Akihiko、NOTOMI Masaya
- Journal Title
  
  IEICE Trans. Fundamentals
  
  Volume: E104.A Issue: 11 Pages: 1546-1554
- DOI
  10.1587/transfun.2020KEP0018
- NAID
  130008109844
- ISSN
  0916-8508, 1745-1337
- Year and Date
  2021-11-01
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20H04155
[Journal Article] Optical-electronic implementation of artificial neural network for ultrafast and accurate inference processing2021
- Author(s)
  Hattori Naoki、Masuda Yutaka、Ishihara Tohru、Shiomi Jun、Shinya Akihiko、Notomi Masaya
- Journal Title
  
  Proc. AI and Optical Data Sciences II. International Society for Optics and Photonics
  
  Pages: 415-421
- DOI
  10.1117/12.2577966
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20H04155
[Journal Article] 集積ナノフォトニクスに基づく光ニューラルネットワークを対象とした回路アーキテクチャ探索2020
- Author(s)
  服部直樹, 増田豊, 石原亨, 塩見準, 新家昭彦, 納富雅也
- Journal Title
  
  第33回回路とシステムワークショップ論文集
  
  Volume: IEICE-VLD2019-137 Pages: 10-15
- NAID
  40022400516
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20H04155
[Journal Article] An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics2020
- Author(s)
  Shiomi Jun、Ishihara Tohru、Onodera Hidetoshi、Shinya Akihiko、Notomi Masaya
- Journal Title
  
  Proc. IEEE International Conference on Rebooting Computing
  
  Pages: 95-101
- DOI
  10.1109/icrc2020.2020.00017
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20H04155
[Journal Article] On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing2019
- Author(s)
  XU Hongjie、SHIOMI Jun、ISHIHARA Tohru、ONODERA Hidetoshi
- Journal Title
  
  IEICE Trans. Fundamentals
  
  Volume: E102.A Issue: 12 Pages: 1741-1750
- DOI
  10.1587/transfun.E102.A.1741
- NAID
  130007754040
- ISSN
  0916-8508, 1745-1337
- Year and Date
  2019-12-01
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17H01712
[Journal Article] Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits2019
- Author(s)
  MATSUO Ryosuke、SHIOMI Jun、ISHIHARA Tohru、ONODERA Hidetoshi、SHINYA Akihiko、NOTOMI Masaya
- Journal Title
  
  IEICE Trans. Fundamentals
  
  Volume: E102.A Issue: 12 Pages: 1751-1759
- DOI
  10.1587/transfun.E102.A.1751
- NAID
  130007754051
- ISSN
  0916-8508, 1745-1337
- Year and Date
  2019-12-01
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17K19975
[Journal Article] A Design Method of a Cell-Based Amplifier for Body Bias Generation2019
- Author(s)
  KOYANAGI Takuya、SHIOMI Jun、ISHIHARA Tohru、ONODERA Hidetoshi
- Journal Title
  
  IEICE Trans. Electron.
  
  Volume: E102.C Issue: 7 Pages: 565-572
- DOI
  10.1587/transele.2018CTP0014
- NAID
  130007671364
- ISSN
  0916-8524, 1745-1353
- Year and Date
  2019-07-01
- Language
  English
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-16H01713, KAKENHI-PROJECT-17H01712
[Journal Article] An Integrated Nanophotonic Parallel Adder2018
- Author(s)
  Ishihara Tohru、Shinya Akihiko、Inoue Koji、Nozaki Kengo、Notomi Masaya
- Journal Title
  
  ACM Journal on Emerging Technologies in Computing Systems
  
  Volume: 14 Issue: 2 Pages: 1-20
- DOI
  10.1145/3178452
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17K19975
[Journal Article] A temperature monitor circuit with small voltage sensitivity using a topology-reconfigurable ring oscillator2018
- Author(s)
  Kishimoto Tadashi、Ishihara Tohru、Onodera Hidetoshi
- Journal Title
  
  Japanese Journal of Applied Physics
  
  Volume: 57 Issue: 4S Pages: 04FF09-04FF09
- DOI
  10.7567/jjap.57.04ff09
- NAID
  210000148923
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-16H01713, KAKENHI-PROJECT-17H01712
[Journal Article] Minimum Energy Point Tracking with All-Digital On-Chip Sensors2018
- Author(s)
  Shiomi Jun、Hokimoto Shu、Ishihara Tohru、Onodera Hidetoshi
- Journal Title
  
  Journal of Low Power Electronics
  
  Volume: 14 Issue: 2 Pages: 227-235
- DOI
  10.1166/jolpe.2018.1561
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-16H01713, KAKENHI-PROJECT-17H01712
[Journal Article] Area-Efficient Fully Digital Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing2017
- Author(s)
  Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
- Journal Title
  
  Integration, the VLSI Journal
  
  Volume: N/A Pages: 201-210
- DOI
  10.1016/j.vlsi.2017.07.001
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-16J08694, KAKENHI-PROJECT-16H01713, KAKENHI-PROJECT-17H01712
[Journal Article] A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation2017
- Author(s)
  Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
- Journal Title
  
  IEICE Trans. Fundamentals
  
  Volume: E100.A Issue: 12 Pages: 2764-2775
- DOI
  10.1587/transfun.E100.A.2764
- NAID
  130006236534
- ISSN
  0916-8508, 1745-1337
- Language
  English
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-16J08694, KAKENHI-PROJECT-16H01713, KAKENHI-PROJECT-17H01712
[Journal Article] A Minimum Energy Point Tracking Algorithm Based on Dynamic Voltage Scaling and Adaptive Body Biasing2017
- Author(s)
  HOKIMOTO Shu、ISHIHARA Tohru、ONODERA Hidetoshi
- Journal Title
  
  IEICE Trans. Fundamentals
  
  Volume: E100.A Issue: 12 Pages: 2776-2784
- DOI
  10.1587/transfun.E100.A.2776
- NAID
  130006236535
- ISSN
  0916-8508, 1745-1337
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17H01712
[Journal Article] Analytical Stability Modeling for CMOS Latches in Low Voltage Operation2016
- Author(s)
  Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
- Journal Title
  
  IEICE Trans. Fundamentals
  
  Volume: E99.A Issue: 12 Pages: 2463-2472
- DOI
  10.1587/transfun.E99.A.2463
- NAID
  130005170525
- ISSN
  0916-8508, 1745-1337
- Language
  English
- Peer Reviewed / Acknowledgement Compliant / Open Access
- Data Source
  KAKENHI-PROJECT-25280014, KAKENHI-PROJECT-26280013
[Journal Article] Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell2015
- Author(s)
  Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
- Journal Title
  
  IPSJ Transactions on System LSI Design Methodology
  
  Volume: 8 Issue: 0 Pages: 131-135
- DOI
  10.2197/ipsjtsldm.8.131
- NAID
  130005091214
- ISSN
  1882-6687
- Language
  English
- Peer Reviewed / Acknowledgement Compliant / Open Access
- Data Source
  KAKENHI-PROJECT-25280014
[Journal Article] Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization2015
- Author(s)
  Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
- Journal Title
  
  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
  
  Volume: Vol. E98-A
- NAID
  130005085789
- Peer Reviewed / Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-26280013
[Journal Article] Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization2015
- Author(s)
  Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
- Journal Title
  
  IEICE Trans. Fundamentals
  
  Volume: E98.A Issue: 7 Pages: 1455-1466
- DOI
  10.1587/transfun.E98.A.1455
- NAID
  130005085789
- ISSN
  0916-8508, 1745-1337
- Language
  English
- Peer Reviewed / Acknowledgement Compliant / Open Access
- Data Source
  KAKENHI-PROJECT-25280014, KAKENHI-PROJECT-26280013
[Journal Article] Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation2013
- Author(s)
  Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
- Journal Title
  
  IEICE Trans. Fundamentals
  
  Volume: E96.A Issue: 12 Pages: 2499-2507
- DOI
  10.1587/transfun.E96.A.2499
- NAID
  130003385302
- ISSN
  0916-8508, 1745-1337
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-25280014
[Journal Article] Single-Cycle-Accessible Two-Level Caches and Compilation Technique for Energy Reduction2009
- Author(s)
  S.Yamaguchi, Y.Ishitobi, T.Ishihara, H.Yasuura
- Journal Title
  
  IPSJ Transactions on System LSI Design Methodology Vol.2
  
  Pages: 189-199
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20700049
[Journal Article] Single-Cycle-Accessible Two-Level Caches and Compilation Technique for Energy Reduction2009
- Author(s)
  S. Yamaguchi, Y. Ishitobi, T. Ishihara, H. Yasuura
- Journal Title
  
  IPSJ Transactions on System LSI Design Methodology Vol.2
  
  Pages: 189-199
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20700049
[Journal Article] An Optimization Technique for Low-Energy Embedded Memory Systems2009
- Author(s)
  T.Matsumura, T.Ishihara, H.Yasuura
- Journal Title
  
  IPSJ Transactions on System LSI Design Methodology Vol.2
  
  Pages: 239-249
- NAID
  110009598039
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20700049
[Journal Article] An Optimization Technique for Low-Energy Embedded Memory Systems2009
- Author(s)
  T. Matsumura, T. Ishihara, H. Yasuu ra
- Journal Title
  
  IPSJ Transactions on System LSI D esign Methodology Vol.2
  
  Pages: 239-249
- NAID
  110009598039
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20700049
[Patent] 半導体装置及び半導体装置の製造方法2016
- Inventor(s)
  石原亨、塩見準
- Industrial Property Rights Holder
  石原亨、塩見準
- Industrial Property Rights Type
  特許
- Filing Date
  2016-01-20
- Data Source
  KAKENHI-PROJECT-26540021
[Presentation] A Cell-based DRAM for Fully Synthesizable PiM Accelerator Design2024
- Author(s)
  Tohru Ishihara
- Organizer
  22nd International Forum on MPSoC
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-24K22292
[Presentation] Gain-Cell DRAMを活用する近しきい値電圧動作に適した行列積演算器2024
- Author(s)
  陳岱鋒，増田豊，石原亨
- Organizer
  情報処理学会DA シンポジウム
- Data Source
  KAKENHI-PROJECT-24K22292
[Presentation] An optoelectronic pipelined convolutional-RNN architecture for energy-efficient AI accelerator2024
- Author(s)
  Chunlu Wang, Yutaka Masuda, Tohru Ishihara
- Organizer
  Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-20H04155
[Presentation] Optoelectronic Implementation of Compact and Power-Efficient Recurrent Neural Networks2022
- Author(s)
  Taisei Ichikawa, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi
- Organizer
  IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-20H04155
[Presentation] 省面積と低電力を両立する光電融合RNN アーキテクチャ2022
- Author(s)
  市川大生, 増田豊, 石原亨, 新家昭彦, 納富雅也
- Organizer
  第35 回回路とシステムワークショップ論文集
- Data Source
  KAKENHI-PROJECT-20H04155
[Presentation] Energy efficient OEO conversion and its applications to photonic integrated systems2022
- Author(s)
  Akihiko Shinya, Kengo Nozaki, Shota Kita, Tohru Ishihara, Shingo Matsuo, Masaya Notomi,
- Organizer
  IEEE Optical Fiber Communications Conference and Exhibition (OFC)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-20H04155
[Presentation] Power-Aware Pruning for Ultrafast, Energy-Efficient, and Accurate Optical Neural Network Design2022
- Author(s)
  Naoki Hattori, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi
- Organizer
  Design Automation Conference (DAC)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-20H04155
[Presentation] An Accuracy Reconfigurable Multiply-Accumulate Unit Based on Operand-Decomposed Mitchell’s Multiplier2021
- Author(s)
  L. Hou, Y. Masuda, T. Ishihara
- Organizer
  Workshop on Synthesis And System Integration of Mixed Information technologies
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01712
[Presentation] Optical-electronic implementation of artificial neural network for ultrafast and accurate inference processing2021
- Author(s)
  Hattori Naoki、Masuda Yutaka、Ishihara Tohru、Shiomi Jun、Shinya Akihiko、Notomi Masaya
- Organizer
  SPIE Conference 11703, AI and Optical Data Sciences II
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-20H04155
[Presentation] Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy2020
- Author(s)
  Kiyawat Khyati、Masuda Yutaka、Shiomi Jun、Ishihara Tohru
- Organizer
  IEEE Computer Society Annual Symposium on VLSI
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01712
[Presentation] ニューラルネットワークの集積ナノフォトニクス実装に適した回路構造探索2020
- Author(s)
  服部直樹、増田豊、石原亨、塩見準、新家昭彦、納富雅也
- Organizer
  電子情報通信学会 VLSI設計技術研究会技術報告119(443)
- Data Source
  KAKENHI-PROJECT-17K19975
[Presentation] An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics2020
- Author(s)
  Shiomi Jun、Ishihara Tohru、Onodera Hidetoshi、Shinya Akihiko、Notomi Masaya
- Organizer
  IEEE International Conference on Rebooting Computing
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-20H04155
[Presentation] 集積ナノフォトニクスに基づく光ニューラルネットワークを対象とした回路アーキテクチャ探索2020
- Author(s)
  服部直樹, 増田豊, 石原亨, 塩見準, 新家昭彦, 納富雅也
- Organizer
  第33回回路とシステムワークショップ
- Data Source
  KAKENHI-PROJECT-20H04155
[Presentation] An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator2019
- Author(s)
  ISHIHARA Tohru、SHIOMI Jun、HATTORI Naoki、MASUDA Yutaka、SHINYA Akihiko、NOTOMI Masaya
- Organizer
  IEEE/ACM Workshop on Photonics-Optics Technology Oriented Networking, Information and Computing Systems
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17K19975
[Presentation] BDDに基づく光論理回路の素子数削減と消費電力低減2019
- Author(s)
  松尾亮祐、塩見凖、石原亨、小野寺秀俊、新家昭彦、納富雅也
- Organizer
  電子情報通信学会VLSI設計技術研究会
- Data Source
  KAKENHI-PROJECT-17K19975
[Presentation] A Process-Scheduler-Based Approach to Minimum Energy Point Tracking2019
- Author(s)
  Shengyu Liu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
- Organizer
  DAシンポジウム
- Data Source
  KAKENHI-PROJECT-17H01712
[Presentation] Society5.0の実現に向けたエナジーハーベスティング技術2019
- Author(s)
  石原　亨
- Organizer
  公益社団法人電気化学会キャパシタ技術委員会
- Invited
- Data Source
  KAKENHI-PROJECT-17H01712
[Presentation] 広範囲な電圧領域で動作するフリップフロップのタイミング特性モデル2019
- Author(s)
  内田翼、塩見準、石原亨、小野寺秀俊
- Organizer
  DAシンポジウム
- Data Source
  KAKENHI-PROJECT-17H01712
[Presentation] BDD-based Synthesis of Optical Logic Circuits Exploting Wavelength Division Multiplexing2019
- Author(s)
  Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
- Organizer
  Asia and South Pacific Design Automation Conference
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17K19975
[Presentation] Integrated Optical Neural Networks Exploiting Light Speed Approximate Parallel Multipliers2019
- Author(s)
  Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, and Masaya Notomi
- Organizer
  5th International Workshop on Optical/Photonic Interconnects
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17K19975
[Presentation] Near-Threshold Cache Architecture for Ultra-Low Energy Computing2019
- Author(s)
  Tohru ISHIHARA
- Organizer
  International Forum on MPSoC for Software defined Hardware
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01712
[Presentation] Independent N-well and P-well Biasing for Minimum Leakage Energy Operation2018
- Author(s)
  Yosuke Okamura, Tohru Ishihara, Hidetoshi Onodera
- Organizer
  The International Symposium on On-Line Testing and Robust System Design
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16H01713
[Presentation] A Light Speed Optical Approximate Parallel Multiplier and Its Applications2018
- Author(s)
  Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, and Masaya Notomi
- Organizer
  Workshop on Photonics-Optics Technology Oriented Networking, Information, and Computing Systems
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17K19975
[Presentation] アルタイム電圧最適化によるマルチタスク処理の消費エネルギー最小化2018
- Author(s)
  塩見準，石原亨，小野寺秀俊
- Organizer
  情報処理学会システムとLSIの設計技術研究会
- Data Source
  KAKENHI-PROJECT-17H01712
[Presentation] Multi-Level Optimization for Large Fan-In Optical Logic Circuits using Integrated Nanophotonics2018
- Author(s)
  Takumi Egawa, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi
- Organizer
  IEEE International Conference on Rebooting Computing
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17K19975
[Presentation] 集積ナノフォトニクスに基づく近似二進対数を用いた低レイテンシ光並列乗算器2018
- Author(s)
  塩見凖、石原亨、小野寺秀俊、新家昭彦、納富雅也
- Organizer
  DAシンポジウム2018
- Data Source
  KAKENHI-PROJECT-17K19975
[Presentation] Independent N-Well And P-Well Biasing For Minimum Leakage Energy Operation2018
- Author(s)
  Okamura Yosuke、Ishihara Tohru、Onodera Hidetoshi
- Organizer
  International Symposium on On-Line Testing and Robust System Design
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01712
[Presentation] An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms towards Light Speed Data Processing2018
- Author(s)
  Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
- Organizer
  IEEE International Conference on Rebooting Computing
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17K19975
[Presentation] A Hybrid Caching System Using SRAM and Standard-Cell Memory for Energy-Efficient Near-Threshold Circuits2018
- Author(s)
  Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
- Organizer
  The 21st Workshop on Synthesis And System Integration of Mixed Information technologies
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01712
[Presentation] On-Chip Reconfigurable Monitor Circuit for Process Variation and Temperature Estimation2018
- Author(s)
  Tadashi Kishimoto, Tohru Ishihara and Hidetoshi Onodera
- Organizer
  International Conference on Microelectronic Test Structures
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16H01713
[Presentation] 幅広い動作環境にわたってLSIの最大遅延特性を追跡するクリティカルパスレプリカの構成法2018
- Author(s)
  福田展和, 塩見準, 石原亨, 小野寺秀俊
- Organizer
  情報処理学会システムとLSIの設計技術研究発表会
- Data Source
  KAKENHI-PROJECT-17H01712
[Presentation] Individual Voltage Scaling in Logic and Memory Circuits towards Runtime Energy Optimization in Processors2018
- Author(s)
  Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
- Organizer
  International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01712
[Presentation] A Software Implementation of Minimum Energy Point Tracking Algorithm for Microprocessors2018
- Author(s)
  Shengyu Liu，Jun Shiomi，Tohru Ishihara，Hidetoshi Onodera
- Organizer
  情報処理学会DAシンポジウム
- Data Source
  KAKENHI-PROJECT-17H01712
[Presentation] 選択的活性化によるスタンダードセルメモリの低消費エネルギー化2018
- Author(s)
  塩見準，石原亨，小野寺秀俊
- Organizer
  情報処理学会システムとLSIの設計技術研究会
- Data Source
  KAKENHI-PROJECT-17H01712
[Presentation] All-digital on-chip heterogeneous sensors for tracking the minimum energy point of processors2018
- Author(s)
  Hokimoto Shu、Shiomi Jun、Ishihara Tohru、Onodera Hidetoshi
- Organizer
  International Conference on Microelectronic Test Structures
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01712
[Presentation] On-chip reconfigurable monitor circuit for process variation and temperature estimation2018
- Author(s)
  Kishimoto Tadashi、Ishihara Tohru、Onodera Hidetoshi
- Organizer
  International Conference on Microelectronic Test Structures
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01712
[Presentation] Maximizing Energy Efficiency of on-Chip Caches Exploiting Hybrid Memory Structure2018
- Author(s)
  Xu Hongjie、Shiomi Jun、Ishihara Tohru、Onodera Hidetoshi
- Organizer
  The 28th International Symposium on Power and Timing Modeling, Optimization and Simulation
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01712
[Presentation] 複数電源ドメインの実行時電圧制御によるCMOS LSIの消費エネルギー最小化2018
- Author(s)
  塩見準，石原亨，小野寺秀俊
- Organizer
  情報処理学会DAシンポジウム
- Data Source
  KAKENHI-PROJECT-17H01712
[Presentation] 波長多重を用いた二分決定グラフに基づく光論理回路の合成2018
- Author(s)
  松尾亮祐、塩見凖、石原亨、小野寺秀俊、新家昭彦、納富雅也
- Organizer
  DAシンポジウム2018
- Data Source
  KAKENHI-PROJECT-17K19975
[Presentation] セルベース設計に適合した基板バイアス制御用増幅回路の設計手法2018
- Author(s)
  小柳卓也, 塩見準, 石原亨, 小野寺秀俊
- Organizer
  情報処理学会DAシンポジウム
- Data Source
  KAKENHI-PROJECT-17H01712
[Presentation] Minimum Energy Point Tracking Exploiting All-Digital On-Chip Sensors2018
- Author(s)
  Tohru Ishihara
- Organizer
  The 28th International Forum on MPSoC for Software-defined Hardware
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01712
[Presentation] トポロジー可変リングオシレータを用いた電圧感度の小さい動作温度モニタ2017
- Author(s)
  岸本真，石原亨，小野寺秀俊
- Organizer
  情報処理学会DAシンポジウム
- Data Source
  KAKENHI-PROJECT-17H01712
[Presentation] On-Chip Temperature and Process Variation Sensing using a Reconfigurable Ring Oscillator2017
- Author(s)
  Tadashi Kishimoto, Tohru Ishihara, and Hidetoshi Onodera
- Organizer
  2017 International Symposium on VLSI Design, Automation and Test
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16H01713
[Presentation] リークエネルギーを最小化するP/N基板電圧の設定手法2017
- Author(s)
  岡村陽介,石原亨，小野寺秀俊
- Organizer
  情報処理学会DAシンポジウム
- Data Source
  KAKENHI-PROJECT-17H01712
[Presentation] On-Chip Temperature and Process Variation Sensing using a Reconfigurable Ring Oscillator2017
- Author(s)
  Tadashi Kishimoto, Tohru Ishihara, and Hidetoshi Onodera
- Organizer
  International Symposium on VLSI Design, Automation and Test
- Place of Presentation
  Shinchu, Taiwan
- Year and Date
  2017-04-24
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26280013
[Presentation] 最小エネルギー動作点追跡アルゴリズムの実チップ評価2017
- Author(s)
  保木本修, 塩見準，石原亨，小野寺秀俊
- Organizer
  情報処理学会DAシンポジウム
- Data Source
  KAKENHI-PROJECT-17H01712
[Presentation] On-chip temperature and process variation sensing using a reconfigurable Ring Oscillator2017
- Author(s)
  Kishimoto Tadashi、Ishihara Tohru、Onodera Hidetoshi
- Organizer
  International Symposium on VLSI Design, Automation and Test
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01712
[Presentation] アクセス頻度に応じた電圧調節によるオンチップメモリの消費エネルギー最小化2017
- Author(s)
  塩見準，石原亨，小野寺秀俊
- Organizer
  情報処理学会DAシンポジウム
- Data Source
  KAKENHI-PROJECT-17H01712
[Presentation] Minimum Energy Point Tracking for Self-Powered IoT Processors2017
- Author(s)
  Tohru Ishihara
- Organizer
  17th International Forum on MPSoC for software-defined hardware
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17H01712
[Presentation] A Temperature Monitor Circuit with Small Voltage Sensitivity using a Topology Reconfigurable Ring Oscillator2017
- Author(s)
  Tadashi Kishimotoy, Tohru Ishiharay, and Hidetoshi Onodera
- Organizer
  2017 International Conference on Solid State Devices and Materials
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16H01713
[Presentation] Fully Digital On-Chip Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing2016
- Author(s)
  Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
- Organizer
  International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)
- Place of Presentation
  Bremen(Germany)
- Year and Date
  2016-09-21
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16H01713
[Presentation] A Processor Architecture Integrating Voltage Scalable On-Chip Memories for Individual Tracking of Minimum Energy Points in Logic and Memory2016
- Author(s)
  Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
- Organizer
  The 20th Workshop on Synthesis And System Integration of Mixed Information technologies
- Place of Presentation
  京都リサーチパーク、京都府京都市
- Year and Date
  2016-09-24
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26280013
[Presentation] A Closed-Form Stability Model for Cross-Coupled Inverters Operating in Sub-Threshold Voltage Region2016
- Author(s)
  Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
- Organizer
  Asia and South Pacific Design Automation Conference
- Place of Presentation
  Holiday Inn, Sands Cotai, Macau
- Year and Date
  2016-01-26
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26540021
[Presentation] 広範囲な動作性能領域においてエネルギー最小点追跡を可能にするオンチップメモリ2016
- Author(s)
  塩見準、石原亨、小野寺秀俊
- Organizer
  情報処理学会DAシンポジウム
- Place of Presentation
  山代温泉ゆのくに天祥、石川県加賀市
- Year and Date
  2016-09-14
- Data Source
  KAKENHI-PROJECT-26540021
[Presentation] 広範囲な動作性能領域においてエネルギー最小点追跡を可能にするオンチップメモリ2016
- Author(s)
  塩見準、石原亨、小野寺秀俊
- Organizer
  情報処理学会DAシンポジウム
- Place of Presentation
  山代温泉ゆのくに天祥、石川県加賀市
- Year and Date
  2016-09-14
- Data Source
  KAKENHI-PROJECT-26280013
[Presentation] A Closed-Form Stability Model for Cross-Coupled Inverters Operating in Sub-Threshold Voltage Region2016
- Author(s)
  Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
- Organizer
  21st Asia and South Pacific Design Automation Conference (ASP-DAC)
- Place of Presentation
  Macao(China)
- Year and Date
  2016-01-25
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280014
[Presentation] A Processor Architecture Integrating Voltage Scalable On-Chip Memories for Individual Tracking of Minimum Energy Points in Logic and Memory2016
- Author(s)
  Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
- Organizer
  The 20th Workshop on Synthesis And System Integration of Mixed Information technologies
- Place of Presentation
  京都リサーチパーク、京都府京都市
- Year and Date
  2016-10-24
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26540021
[Presentation] 回路トポロジー可変なリングオシレータを用いたプロセス変動量と動作温度の推定方法2016
- Author(s)
  岸本真、石原亨、小野寺秀俊
- Organizer
  情報処理学会DAシンポジウム
- Place of Presentation
  山代温泉ゆのくに天祥、石川県加賀市
- Year and Date
  2016-09-14
- Data Source
  KAKENHI-PROJECT-26280013
[Presentation] Minimum Energy Point Tracking Using Combined Dynamic Voltage Scaling and Adaptive Body Biasing2016
- Author(s)
  Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera
- Organizer
  IEEE International System-on-Chip Conference
- Place of Presentation
  Seattle, USA
- Year and Date
  2016-09-06
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26280013
[Presentation] プロセッサにおける電源電圧と基板電圧の同時調節によるエネルギー最小点追跡手法2016
- Author(s)
  保木本修、石原亨、小野寺秀俊
- Organizer
  情報処理学会DAシンポジウム
- Place of Presentation
  山代温泉ゆのくに天祥、石川県加賀市
- Year and Date
  2016-09-14
- Data Source
  KAKENHI-PROJECT-26280013
[Presentation] A Closed-Form Stability Model for Cross-Coupled Inverters Operating in Sub-Threshold Voltage Region2016
- Author(s)
  Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
- Organizer
  Asia and South Pacific Design Automation Conference
- Place of Presentation
  Sands Cotai, Macau
- Year and Date
  2016-01-26
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26280013
[Presentation] Minimum Energy Point Tracking under a Wide Range of PVT Conditions2016
- Author(s)
  Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera
- Organizer
  The 20th Workshop on Synthesis And System Integration of Mixed Information technologies
- Place of Presentation
  京都リサーチパーク、京都府京都市
- Year and Date
  2016-10-24
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26280013
[Presentation] A Processor Architecture Integrating Voltage Scalable On-Chip Memories for Individual Tracking of Minimum Energy Points in Logic and Memory2016
- Author(s)
  Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
- Organizer
  The 20th Workshop on Synthesis And System Integration of Mixed Information technologies
- Place of Presentation
  KRP(京都)
- Year and Date
  2016-10-24
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16H01713
[Presentation] Variability- and Correlation-Aware Logical Effort for Near-Threshold Circuit Design2016
- Author(s)
  Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
- Organizer
  International Symposium on Quality Electronic Design
- Place of Presentation
  Santa Clara Convention Center, Santa Clara, California, USA
- Year and Date
  2016-03-15
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26540021
[Presentation] Guidelines for Effective and Simplified Dynamic Supply and Threshold Voltage Scaling2016
- Author(s)
  Toshihiro Takeshita, Tohru ISHIHARA, Hidetoshi Onodera
- Organizer
  International Symposium on VLSI Design, Automation and Test
- Place of Presentation
  Hsinchu, Taiwan
- Year and Date
  2016-04-25
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26280013
[Presentation] Fully Digital On-Chip Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing2016
- Author(s)
  Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
- Organizer
  International Workshop on Power and Timing Modeling, Optimization and Simulation
- Place of Presentation
  Bremen, Germany
- Year and Date
  2016-09-21
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26540021
[Presentation] Fully Digital On-Chip Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing2016
- Author(s)
  Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
- Organizer
  International Workshop on Power and Timing Modeling, Optimization and Simulation
- Place of Presentation
  Bremen, Germany
- Year and Date
  2016-09-21
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26280013
[Presentation] CMOS LSIにおけるエネルギー最小点追跡のための電源電圧としきい値電圧の動的調節指針2016
- Author(s)
  竹下俊宏, 塩見準，石原亨，小野寺秀俊
- Organizer
  情報処理学会システムLSI設計技術研究会研究報告, 2016-SLDM-175(32)
- Place of Presentation
  福江文化会館、長崎県福江市
- Year and Date
  2016-03-24
- Data Source
  KAKENHI-PROJECT-26280013
[Presentation] Variability- and Correlation-Aware Logical Effort for Near-Threshold Circuit Design2016
- Author(s)
  Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
- Organizer
  International Symposium on Quality Electronic Design
- Place of Presentation
  Santa Clara, California, USA
- Year and Date
  2016-03-15
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26280013
[Presentation] Practical Supply and Threshold Voltage Scaling for Energy Efficient Operation of Microprocessors2015
- Author(s)
  Tohru Ishihara
- Organizer
  International Forum on FDSOI IC Design
- Place of Presentation
  Grenoble, France
- Year and Date
  2015-06-22
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26280013
[Presentation] 電源電圧としきい値電圧の同時最適化が集積回路の消費エネルギーに与える影響の解析2015
- Author(s)
  竹下俊宏、西澤真一、Islam AKM Mahfuzul、石原　亨、小野寺秀俊
- Organizer
  電子情報通信学会VLSI設計技術研究会
- Place of Presentation
  慶應義塾大学日吉キャンパス来往舎、神奈川県横浜市
- Year and Date
  2015-01-29
- Data Source
  KAKENHI-PROJECT-26280013
[Presentation] 統計的タイミングモデルに基づくニアスレッショルド回路のゲートサイジング2015
- Author(s)
  塩見準，石原亨，小野寺秀俊
- Organizer
  情報処理学会DAシンポジウム
- Place of Presentation
  山代温泉ゆのくに天祥、石川県加賀市
- Year and Date
  2015-08-26
- Data Source
  KAKENHI-PROJECT-26540021
[Presentation] An impact of process variation on supply voltage dependence of logic path delay variation2015
- Author(s)
  S. Nishizawa, T. Ishihara, H. Onodera
- Organizer
  International Symposium on VLSI Design, Automation and Test
- Place of Presentation
  Hsinchu, Taiwan
- Year and Date
  2015-04-27
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26280013
[Presentation] Slew- and Variability-Aware Logical Effort for Near-Threshold Circuit Design2015
- Author(s)
  Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
- Organizer
  International Workshop on Variability Modeling and Characterization
- Place of Presentation
  San Jose, California, USA
- Year and Date
  2015-11-05
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26280013
[Presentation] Practical Supply and Threshold Voltage Scaling for Energy Efficient Operation of Microprocessors2015
- Author(s)
  Tohru Ishihara
- Organizer
  International Forum on Embedded MPSoC and Multicore
- Place of Presentation
  Ventura, California, USA
- Year and Date
  2015-07-13
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26280013
[Presentation] An impact of process variation on supply voltage dependence of logic path delay variation2015
- Author(s)
  S. Nishizawa, T. Ishihara, H. Onodera
- Organizer
  International Symposium on VLSI Design, Automation and Test
- Place of Presentation
  Hsinchu(Taiwan)
- Year and Date
  2015-04-27
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25280014
[Presentation] サブスレッショルド領域におけるラッチ回路の動作安定性モデル2015
- Author(s)
  鎌苅竜也，塩見準，石原亨，小野寺秀俊
- Organizer
  情報処理学会DAシンポジウム
- Place of Presentation
  山代温泉ゆのくに天祥、石川県加賀市
- Year and Date
  2015-08-26
- Data Source
  KAKENHI-PROJECT-26540021
[Presentation] 統計的タイミングモデルに基づくニアスレッショルド回路のゲートサイジング2015
- Author(s)
  塩見準，石原亨，小野寺秀俊
- Organizer
  情報処理学会DAシンポジウム2015
- Place of Presentation
  温泉ゆのくに天祥、石川県加賀市
- Year and Date
  2015-08-26
- Data Source
  KAKENHI-PROJECT-26280013
[Presentation] サブスレッショルド領域におけるラッチ回路の動作安定性モデル2015
- Author(s)
  鎌苅竜也，塩見準，石原亨，小野寺秀俊
- Organizer
  情報処理学会DAシンポジウム2015
- Place of Presentation
  温泉ゆのくに天祥、石川県加賀市
- Year and Date
  2015-08-26
- Data Source
  KAKENHI-PROJECT-26280013
[Presentation] Variation Tolerant Design of D-Flip-Flops for Low Voltage Circuit Operation2014
- Author(s)
  Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
- Organizer
  International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)
- Place of Presentation
  Santa Cruz, CA, USA
- Data Source
  KAKENHI-PROJECT-25280014
[Presentation] A Lognormal Timing Model and Design Guidelines for Near-Threshold Circuits2014
- Author(s)
  Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
- Organizer
  International Workshop on Variability Modeling and Charactorization
- Place of Presentation
  San Jose, California, USA
- Year and Date
  2014-11-06
- Data Source
  KAKENHI-PROJECT-26280013
[Presentation] Reconfigurable Delay Cell for Area-efficient Implementation of On-chip MOSFET Monitor Schemes2013
- Author(s)
  A.K.M. Mahfuzul Islam, Tohru Ishihara, and Hidetoshi Onodera
- Organizer
  IEEE Asian Solid State Circuits Conference
- Place of Presentation
  Singapore
- Data Source
  KAKENHI-PROJECT-25280014
[Presentation] A Run-Time Power Analysis Method using OS-Observable Parameters for Mobile Terminals2010
- Author(s)
  Y.Kaneda, T.Okuhira, T.Ishihara, K.Hisazumi, T.Kamiyama, M.Katagiri
- Organizer
  International Conference on Embedded Systems and Intelligent Technology
- Place of Presentation
  タイチェンマイ
- Year and Date
  2010-02-07
- Data Source
  KAKENHI-PROJECT-20700049
[Presentation] Unification of Multiple Gated Flip-Flops for Saving the Power Consumption of Register Circuits2010
- Author(s)
  T.Okuhira, T.Ishihara
- Organizer
  International Conference on Embedded Systems and Intelligent Technology
- Place of Presentation
  タイチェンマイ
- Year and Date
  2010-02-06
- Data Source
  KAKENHI-PROJECT-20700049
[Presentation] Unification of Multiple Gated Flip-Flops for Saving the Power Consumption of Register Circuits2010
- Author(s)
  T. Okuhira, T. Ishihara
- Organizer
  Proc. of Int'l Conference on Embedded Systems and Intelligent Technology
- Data Source
  KAKENHI-PROJECT-20700049
[Presentation] Real-Time Power Management for a Multi-Performance Processor2009
- Author(s)
  T.Ishihara
- Organizer
  International SoC Design Conference
- Place of Presentation
  韓国釜山
- Year and Date
  2009-11-23
- Data Source
  KAKENHI-PROJECT-20700049
[Presentation] ゲーテッドフリップフロップの多ビット統合によるレジスタの低電力化2009
- Author(s)
  奥平拓見、石原亨、安浦寛人
- Organizer
  電子情報通信学会総合大会
- Place of Presentation
  愛媛県松山市(愛媛大学)
- Year and Date
  2009-03-17
- Data Source
  KAKENHI-PROJECT-20700049
[Presentation] [Invited Talk] Real-Time Dynamic Voltage Hopping on MPSoCs2009
- Author(s)
  T. Ishihara
- Organizer
  International Forum on Embedded MPSoC and Multicore
- Data Source
  KAKENHI-PROJECT-20700049
[Presentation] A Run-Time Power Analysis Method using OS-Observable Parameters for Mobile Terminals2009
- Author(s)
  Y. Kaneda, T. Okuhira, T. Ishihara, K. Hisazumi, T. Kamiyama, M. Katagiri
- Organizer
  Proc. of International Conference on Embedded Systems and Intelligent Technology
- Data Source
  KAKENHI-PROJECT-20700049
[Presentation] Real-Time Power Management for a Multi-Performance Processor2009
- Author(s)
  T. Ishihara
- Organizer
  Proc. of Int'l SoC Design Conference
- Data Source
  KAKENHI-PROJECT-20700049
[Presentation] OSから解析可能な無線通信端末の消費電力モデルとその生成手法2009
- Author(s)
  石原亨、奥平拓見、久住憲嗣、神山剛、関根和寿、片桐雅二
- Organizer
  情報処理学会システムLSI設計技術研究会
- Place of Presentation
  新潟県佐渡市
- Year and Date
  2009-03-05
- Data Source
  KAKENHI-PROJECT-20700049
[Presentation] OSから解析可能な無線通信端末の消費電力モデルとその生成手法2009
- Author(s)
  石原亨, 奥平拓見, 久住憲嗣, 神山剛, 関根和寿, 片桐雅二
- Organizer
  情報処理学会研究報告
- Data Source
  KAKENHI-PROJECT-20700049
[Presentation] ゲーテッドフリップフロップの多ビット結合によるレジスタ回路の低消費電力化2009
- Author(s)
  奥平拓見, 石原亨, 井上弘士
- Organizer
  DAシンポジウム2009論文集
- Data Source
  KAKENHI-PROJECT-20700049
[Presentation] ゲーテッドフリップフロップの多ビット結合によるレジスタの低電力化2009
- Author(s)
  奥平拓見, 石原亨, 安浦寛人
- Organizer
  電子情報通信学会総合大会
- Data Source
  KAKENHI-PROJECT-20700049
[Presentation] Real-Time Dynamic Voltage Hopping on MPSoCs2009
- Author(s)
  T.Ishihara
- Organizer
  International Forum on Embedded MPSoC and Multicore
- Place of Presentation
  米国ジョージア州サバンナ
- Year and Date
  2009-08-05
- Data Source
  KAKENHI-PROJECT-20700049
[Presentation] ゲーテッドフリップフロップの多ビット統合によるレジスタ回路の低消費電力化2009
- Author(s)
  奥平拓見、石原亨、井上弘士
- Organizer
  DAシンポジウム
- Place of Presentation
  石川県加賀市
- Year and Date
  2009-08-26
- Data Source
  KAKENHI-PROJECT-20700049
[Presentation] A Single Cycle Accessible Two-Level Cache Architecture for Reducing the Energy Consumption of Embedded Systems2008
- Author(s)
  S. Yamaguchi, T. Ishihara, H. Yasuura
- Organizer
  Proc. of Int'l SoC Design Conference
- Data Source
  KAKENHI-PROJECT-20700049
[Presentation] A Single Cycle Accessible Two-Level Cache Architecture for R educing the Energy Consumption of Embedded Systems2008
- Author(s)
  S. Yamaguchi, T. Ishihara, H. Y asuura
- Organizer
  International SoC Design Conference
- Place of Presentation
  韓国・釜山
- Year and Date
  2008-11-25
- Data Source
  KAKENHI-PROJECT-20700049
[Presentation] Microarchitectural-Level Statistical Timing Models for Near-Threshold Circuit Design
- Author(s)
  Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
- Organizer
  20th Asia and South Pacific Design Automation Conference
- Place of Presentation
  幕張メッセ、千葉県千葉市
- Year and Date
  2015-01-19 – 2015-01-22
- Data Source
  KAKENHI-PROJECT-26280013
[Presentation] An Energy-Efficient On-Chip Memory Structure for Variability-Aware Near-Threshold Operation
- Author(s)
  Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
- Organizer
  16th International Symposium on Quality Electronic Design
- Place of Presentation
  San Jose, California, USA
- Year and Date
  2015-03-03 – 2015-03-05
- Data Source
  KAKENHI-PROJECT-26540021
[Presentation] ニアスレッショルド回路設計のための基本定理
- Author(s)
  塩見準，石原亨，小野寺秀俊
- Organizer
  電子情報通信学会VLSI設計技術研究会
- Place of Presentation
  沖縄県青年会館、沖縄県那覇市
- Year and Date
  2015-03-02 – 2015-03-04
- Data Source
  KAKENHI-PROJECT-26280013
[Presentation] ニアスレッショルド電圧動作に適した単一電源で動作する高歩留まりオンチップメモリの設計
- Author(s)
  塩見準，石原亨，小野寺秀俊
- Organizer
  情報処理学会DAシンポジウム2014
- Place of Presentation
  ホテル下呂温泉水明館、岐阜県下呂市
- Year and Date
  2014-08-28 – 2014-08-29
- Data Source
  KAKENHI-PROJECT-26540021
[Presentation] 電源電圧に応じてトランジスタサイズを最適化可能なセルライブラリの生成システム
- Author(s)
  西澤真一, 石原亨, 小野寺秀俊
- Organizer
  情報処理学会DAシンポジウム2014
- Place of Presentation
  ホテル下呂温泉水明館、岐阜県下呂市
- Year and Date
  2014-08-28 – 2014-08-29
- Data Source
  KAKENHI-PROJECT-26280013
[Presentation] Near-Threshold Computing on Heterogeneous Multicore Architectures
- Author(s)
  Tohru Ishihara
- Organizer
  14th International Forum on Embedded MPSoC and Multicore
- Place of Presentation
  Margaux, France
- Year and Date
  2014-07-07 – 2014-07-11
- Invited
- Data Source
  KAKENHI-PROJECT-26280013
[Presentation] Energy Reduction by Built-in Body Biasing with Single Supply Voltage Operation
- Author(s)
  Norihiro Kamae, Akira Tsuchiya, Tohru Ishihara, Hidetoshi Onodera
- Organizer
  International Symposium on Quality Electronic Design
- Place of Presentation
  San Jose, California, USA
- Year and Date
  2015-03-03 – 2015-03-04
- Data Source
  KAKENHI-PROJECT-26280013
[Presentation] PLLの物理レイアウト自動生成を目指した設計手法
- Author(s)
  釡江典裕, 土谷亮, 石原亨, 小野寺秀俊
- Organizer
  情報処理学会DAシンポジウム2014
- Place of Presentation
  ホテル下呂温泉水明館、岐阜県下呂市
- Year and Date
  2014-08-28 – 2014-08-29
- Data Source
  KAKENHI-PROJECT-26280013
[Presentation] Design Methodology of Process Variation Tolerant D-Flip-Flops for Low Voltage Circuit Operation
- Author(s)
  Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
- Organizer
  IEEE International System-On-Chip Conference
- Place of Presentation
  Las Vegas, Nevada, USA
- Year and Date
  2014-09-02 – 2014-09-05
- Data Source
  KAKENHI-PROJECT-25280014
[Presentation] A Variability-Aware Energy-Efficient On-Chip Memory for Near-Threshold Operation using Cell-Based Structure
- Author(s)
  Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
- Organizer
  The 19th Workshop on Synthesis And System Integration of Mixed Information technologies
- Place of Presentation
  Evergreen Resort Hotel, Yilan, Taiwan
- Year and Date
  2015-03-16 – 2015-03-17
- Data Source
  KAKENHI-PROJECT-26540021
[Presentation] 製造ばらつきを考慮した極低電圧動作向けフリップフロップの設計手法
- Author(s)
  鎌苅竜也，西澤真一，石原亨，小野寺秀俊
- Organizer
  情報処理学会DAシンポジウム2014
- Place of Presentation
  ホテル下呂温泉水明館、岐阜県下呂市
- Year and Date
  2014-08-28 – 2014-08-29
- Data Source
  KAKENHI-PROJECT-26280013
[Presentation] Design Methodology of Process Variation Tolerant D-Flip-Flops for Low Voltage Circuit Operation
- Author(s)
  Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
- Organizer
  IEEE International System-On-Chip Conference
- Place of Presentation
  Las Vegas, Nevada, USA
- Year and Date
  2014-09-02 – 2014-09-05
- Data Source
  KAKENHI-PROJECT-26280013
[Presentation] Variation-Aware Flip-Flop Energy Optimization for Ultra Low Voltage Operation
- Author(s)
  Tatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
- Organizer
  IEEE International System-On-Chip Conference
- Place of Presentation
  Las Vegas, Nevada, USA
- Year and Date
  2014-09-02 – 2014-09-05
- Data Source
  KAKENHI-PROJECT-25280014
[Presentation] Variation-Aware Flip-Flop Energy Optimization for Ultra Low Voltage Operation
- Author(s)
  Tatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
- Organizer
  IEEE International System-On-Chip Conference
- Place of Presentation
  Las Vegas, Nevada, USA
- Year and Date
  2014-09-02 – 2014-09-05
- Data Source
  KAKENHI-PROJECT-26280013

1. ONODERA Hidetoshi (80160927)

# of Collaborated Projects: 4 results

# of Collaborated Products: 60 results
2. 増田豊 (60845527)

# of Collaborated Projects: 4 results

# of Collaborated Products: 10 results
3. 土谷亮 (20432411)

# of Collaborated Projects: 3 results

# of Collaborated Products: 2 results
4. 塩見準 (40809795)

# of Collaborated Projects: 2 results

# of Collaborated Products: 9 results
5. 長谷川浩 (40323802)

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
6. 森洋二郎 (10722100)

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
7. NISHIZAWA Sinichi (40757522)

# of Collaborated Projects: 1 results

# of Collaborated Products: 4 results
8. MURAKAMI Kazuaki (10200263)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
9. SAWADA Sunao (70235464)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
10. IWAIHARA Mizuho (40253538)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
11. YASUURA Hiroto (80135540)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
12. Mahfuzul Islam A. K. M. (80762195)

# of Collaborated Projects: 1 results

# of Collaborated Products: 1 results
13. 納富雅也 (50393799)

# of Collaborated Projects: 1 results

# of Collaborated Products: 10 results
14. 廣瀬啓

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results

Ishihara Tohru 石原 亨

石原 亨 イシハラ トオル

ISHIHARA Tohru 石原 亨

Research Projects

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Co-Researchers

光演算回路に基づく広帯域かつ超省エネルギー情報処理基盤の創出Principal Investigator

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Highly Energy Efficient and Broadband Information Processing Platform based on Optical Functional CircuitsPrincipal Investigator

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Gain Cell DRAMを活用する超省エネルギーコンピューティング基盤の創出Principal Investigator

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Research on architecture of optoelectronic integrated circuits and their design methodologyPrincipal Investigator

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A Study on Optical Computer Design through Photonics and Electronics Co-OptimizationPrincipal Investigator

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Research on computing infrastructure aimed at realizing an IoT society to comePrincipal Investigator

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LSI Design Method for Minimum Energy Operation

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A Study on Energy Harvesting Embedded Computers as a Social InfrastructurePrincipal Investigator

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A Study on on-chip memories suitable for near-threshold voltage operationPrincipal Investigator

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LSI design methodology that enables robust operation under the supply as low as threshold voltage by self-compensating performance variability

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環境発電に適した組込みシステムのアーキテクチャとOS制御による電力管理技術の研究Principal Investigator

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A Research on Embedded Systems Suited for Energy HarvestingPrincipal Investigator

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Research Institution

システムLSI向け低電力メモリアーキテクチャおよび設計支援技術の開発Principal Investigator

Principal Investigator

Ishihara Tohru 石原亨

石原亨イシハラトオル

ISHIHARA Tohru 石原亨