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DONG QING  董 青

ORCIDConnect your ORCID iD *help
Researcher Number 30638804
Affiliation (based on the past Project Information) *help 2012 – 2013: 北九州市立大学, 国際環境工学部, 講師
Review Section/Research Field
Principal Investigator
Electron device/Electronic equipment
Keywords
Principal Investigator
自己診断システム / アナログLSI
  • Research Projects

    (1 results)
  • Research Products

    (12 results)
  •  Research of BIST for smart analog devicePrincipal Investigator

    • Principal Investigator
      DONG QING
    • Project Period (FY)
      2012 – 2013
    • Research Category
      Grant-in-Aid for Research Activity Start-up
    • Research Field
      Electron device/Electronic equipment
    • Research Institution
      The University of Kitakyushu

All 2013 2012

All Journal Article Presentation

  • [Journal Article] Structured Analog Circuit and Layout Design with Transistor Array2013

    • Author(s)
      B. Yang, Q. Dong, J. Li and S. Nakatake
    • Journal Title

      IEICE

      Volume: Vol.E96-A,No.12 Pages: 2475-2486

    • NAID

      130003385300

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-24860054
  • [Journal Article] Structured Analog Circuit and Layout Design with Transistor Array2013

    • Author(s)
      Bo Yang, Qing Dong, Jing Li and Shigetoshi Nakatake
    • Journal Title

      IEICE Trans. Fundamentals

      Volume: E96.A Issue: 12 Pages: 2475-2486

    • DOI

      10.1587/transfun.E96.A.2475

    • NAID

      130003385300

    • ISSN
      0916-8508, 1745-1337
    • Language
      English
    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-24860054
  • [Journal Article] Analog circuit synthesis with constraint generation of layout dependent effects by geometric programming2013

    • Author(s)
      Y. Zhang, B. Yang, J. Li, Q. Dong and S. Nakatake
    • Journal Title

      IEICE

      Volume: Vol.E96-A, No.12 Pages: 2487-2498

    • NAID

      130003385301

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-24860054
  • [Journal Article] Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming2013

    • Author(s)
      Yu Zhang, Bo Yang, Jing Li, Qing Dong and Shigetoshi Nakatake
    • Journal Title

      IEICE Trans. Fundamentals

      Volume: E96.A Issue: 12 Pages: 2487-2498

    • DOI

      10.1587/transfun.E96.A.2487

    • NAID

      130003385301

    • ISSN
      0916-8508, 1745-1337
    • Language
      English
    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-24860054
  • [Presentation] A Comparator Energy Model Considering Shallow Trench Isolation Stress by Geometric Programming2013

    • Author(s)
      G. Chen, Y. Zhang, B. Yang, Q. Dong, S. Nakatake
    • Organizer
      ISQED, 2013
    • Place of Presentation
      SantaClara, CA, USA
    • Year and Date
      2013-03-06
    • Data Source
      KAKENHI-PROJECT-24860054
  • [Presentation] Performance-driven SRAM Macro Design with Parameterized Cell Considering Layout-dependent Effects2013

    • Author(s)
      Y. Zhang, G. Chen, Q. Dong, M. Li and S. Nakatake
    • Organizer
      VLSI-SOC 2013
    • Place of Presentation
      Istanbul, Turkey
    • Year and Date
      2013-10-07
    • Data Source
      KAKENHI-PROJECT-24860054
  • [Presentation] A Delay-Locked Loop with Multi-Level Channel Length Decomposed Programming Delay Elements2013

    • Author(s)
      Z. Yu, G. Chen, M. Li, Q. Dong and S. Nakatake
    • Organizer
      ICDV 2013
    • Place of Presentation
      Ho Chi Minh City,Vietnam
    • Year and Date
      2013-11-16
    • Data Source
      KAKENHI-PROJECT-24860054
  • [Presentation] A 9-bit 50MSps SAR ADC with Pre-charge VCM-based Double Input Range Algorithm2013

    • Author(s)
      G. Chen, Y. Zhang, Q. Dong, B. Yang, J. Li and S. Nakatake
    • Organizer
      GLVLSI 2013
    • Place of Presentation
      Paris, France
    • Year and Date
      2013-05-02
    • Data Source
      KAKENHI-PROJECT-24860054
  • [Presentation] Routability-driven Common-centroid Capacitor Array Generation with Signal Coupling Constraints2013

    • Author(s)
      G. Chen, J. Li, B. Yang, Q. Dong and S. Nakatake
    • Organizer
      ICDV 2013
    • Place of Presentation
      Ho Chi Minh City,Vietnam
    • Year and Date
      2013-11-16
    • Data Source
      KAKENHI-PROJECT-24860054
  • [Presentation] Simplified Compressed Sensing-Based Volterra Model for Broadband Wireless Power Amplifiers2013

    • Author(s)
      M. Li, G. Chen, Y. Zhang, Q. Dong, S. Nakatake
    • Organizer
      kws 2013
    • Place of Presentation
      兵庫県淡路市
    • Year and Date
      2013-07-29
    • Data Source
      KAKENHI-PROJECT-24860054
  • [Presentation] SRAM Macro Synthesis with Layout- dependent Effect by Geometric Programming2012

    • Author(s)
      Y. Zhang, Q. Dong, S. Nakatake
    • Organizer
      IEEE/ACM Workshop on Variability Modeling and Characterization(VMC) 2012
    • Place of Presentation
      Hilton San Jose, CA, USA
    • Year and Date
      2012-11-08
    • Data Source
      KAKENHI-PROJECT-24860054
  • [Presentation] High Routability and Low Ratio Mismatch Driven Common-Centroid Capacitor Array Generation2012

    • Author(s)
      J. Li, B. Yang, Q. Dong, S. Nakatake
    • Organizer
      IEEE/ACM Workshop on Variability Modeling and Characterization (VMC) 2012
    • Place of Presentation
      Hilton San Jose, CA, USA
    • Year and Date
      2012-11-08
    • Data Source
      KAKENHI-PROJECT-24860054

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