Furuta Jun 古田潤

… Alternative Names

Researcher Number	30735767
Affiliation (Current)	2022: 京都工芸繊維大学, 電気電子工学系, 助教
Affiliation (based on the past Project Information) *help	2016 – 2020: 京都工芸繊維大学, 電気電子工学系, 助教 2015: 京都工芸繊維大学, グリーンイノベーションセンター, 特任助教 2014 – 2015: 京都工芸繊維大学, 学内共同利用施設等, 助教
Review Section/Research Field	Principal Investigator Electron device/Electronic equipment / Basic Section 60040:Computer system-related Except Principal Investigator Computer system
Keywords	Principal Investigator ソフトエラー / 重イオン / フリップフロップ / 中性子 / FD-SOI / 完全空乏型トランジスタ / SEU / 低電力 / SiC MOSFET / 放射線 … More Except Principal Investigator IoT / ソフトエラー / 経年劣化 / パワーエレクトロニクス / 一時故障 / 永久故障 / NBTI / RTN / 信頼性 / ランダムテレグラフノイズ / BTI / パワエレ / FDSOI / バルク / スタックトランジスタ Less

宇宙環境における次世代パワー半導体の寿命予測Principal Investigator
- Principal Investigator
  
  古田潤
- Project Period (FY)
  2020 – 2022
- Research Category
  
  Grant-in-Aid for Early-Career Scientists
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Kyoto Institute of Technology
Radiation-hardened Design for Low-power SupercomputersPrincipal Investigator
- Principal Investigator
  
  Furuta Jun
- Project Period (FY)
  2017 – 2019
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  Kyoto Institute of Technology
An IoT that can keep on running over years efficiently and reliably
- Principal Investigator
  
  Kobayashi Kazutoshi
- Project Period (FY)
  2015 – 2018
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system
- Research Institution
  Kyoto Institute of Technology
Low Power/delay Radiation-hardended Flip-flop in a FD-SOI proessPrincipal Investigator
- Principal Investigator
  
  furuta jun
- Project Period (FY)
  2014 – 2015
- Research Category
  
  Grant-in-Aid for Research Activity Start-up
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  Kyoto Institute of Technology

All 2019 2018 2017 2016 2015

All Journal Article Presentation Patent

[Journal Article] Radiation-Hardened Structure to Reduce Sensitive Range of a Stacked Structure for FDSOI2019
- Author(s)
  K. Yamada, M. Ebara, K. Kojima, Y. Tsukita, J. Furuta, and K. Kobayashi
- Journal Title
  
  IEEE Transactions on Nuclear Science
  
  Volume: 1 Pages: 1-1
- DOI
  10.1109/tns.2019.2908722
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17K14667
[Journal Article] A Low-Power Radiation-Hardened Flip-Flop with Stacked Transistors in a 65 nm FDSOI Process2018
- Author(s)
  MARUOKA Haruki、HIFUMI Masashi、FURUTA Jun、KOBAYASHI Kazutoshi
- Journal Title
  
  IEICE Transactions on Electronics
  
  Volume: E101.C Issue: 4 Pages: 273-280
- DOI
  10.1587/transele.e101.c.273
  10.1587/transele.E101.C.273
- NAID
  130006602277
- ISSN
  0916-8524, 1745-1353
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-15H02677
[Journal Article] Evaluation of plasma-induced damage and bias temperature instability depending on type of antenna layer using current-starved ring oscillators2018
- Author(s)
  Kishida Ryo、Furuta Jun、Kobayashi Kazutoshi
- Journal Title
  
  Jpn. J. Appl. Phys.
  
  Volume: 57 Issue: 4S Pages: 04FD12-04FD12
- DOI
  10.7567/jjap.57.04fd12
- NAID
  210000148889
- ISSN
  0021-4922, 1347-4065
- Data Source
  KAKENHI-PROJECT-15H02677
[Journal Article] Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model2017
- Author(s)
  T. Komawaki, M. Yabuuchi, R. Kishida, J. Furuta, T. Matsumoto, and K. Kobayashi
- Journal Title
  
  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
  
  Volume: E-100A Issue: 12 Pages: 2758-2763
- DOI
  10.1587/transfun.e100.a.2758
  10.1587/transfun.E100.A.2758
- NAID
  130006236533
- ISSN
  0916-8508, 1745-1337
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-15H02677
[Journal Article] A Radiation-Hardened Non-Redundant Flip-Flop, Stacked Leveling Critical Charge Flip-Flop in a 65 nm Thin BOX FD-SOI Process2016
- Author(s)
  J. Furuta, J. Yamaguchi, and K. Kobayashi
- Journal Title
  
  IEEE Trans. on Nuclear Science
  
  Volume: 63 Pages: 2080-2086
- DOI
  10.1109/tns.2016.2543745
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-15H02677
[Journal Article] A Radiation-Hardened Non-redundant Flip-Flop, Stacked Leveling Critical Charge Flip-Flop in a 65 nm Thin BOX FD-SOI Process2016
- Author(s)
  Jun Furuta, Junki Yamaguchi, Kazutoshi Kobayashi
- Journal Title
  
  IEEE Transactions on Neuclear Science
  
  Volume: 1 Pages: 1-1
- Peer Reviewed / Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-26889037
[Journal Article] Impact of Cell Distance and Well-contact Density on Neutron-induced Multiple Cell Upsets2015
- Author(s)
  古田, 小林, 小野寺
- Journal Title
  
  IEICE Transactions on Electronics
  
  Volume: E98-C Issue: 4 Pages: 1745-1353
- DOI
  10.1587/transele.e98.c.298
  10.1587/transele.E98.C.298
- NAID
  130005061834
- ISSN
  0916-8524, 1745-1353
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-15H02677
[Patent] D-type Flip-flop Circuit2019
- Inventor(s)
  小林和淑, 古田潤, 山田晃大
- Industrial Property Rights Holder
  小林和淑, 古田潤, 山田晃大
- Industrial Property Rights Type
  特許
- Filing Date
  2019
- Overseas
- Data Source
  KAKENHI-PROJECT-17K14667
[Patent] 入出力回路、及びフリップフロップ回路2015
- Inventor(s)
  小林和淑、古田潤、山口潤己
- Industrial Property Rights Holder
  小林和淑、古田潤、山口潤己
- Industrial Property Rights Type
  特許
- Filing Date
  2015-08-17
- Data Source
  KAKENHI-PROJECT-26889037
[Patent] 入出力回路、及びフリップフロップ回路2015
- Inventor(s)
  小林，古田，山口
- Industrial Property Rights Holder
  国立大学法人京都工芸繊維大学
- Industrial Property Rights Type
  特許
- Industrial Property Number
  2015-160642
- Filing Date
  2015-08-17
- Data Source
  KAKENHI-PROJECT-15H02677
[Presentation] Evaluation of Soft-Error Tolerance by Neutrons and Heavy Ions on Flip Flops with Guard Gates in a 65 nm Thin BOX FDSOI Process2019
- Author(s)
  M. Ebara, K. Yamada, K. Kojima, Y. Tsukita, J. Furuta, and K. Kobayashi
- Organizer
  Radiation and its Effects on Components and Systems
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17K14667
[Presentation] Impact of Combinational Logic Delay for Single Event Upset on Flip Flops in a 65 nm FDSOI Process2019
- Author(s)
  J. Furuta, Y. Tsukita, K. Yamada, M. Ebara, K. Kojima, and K. Kobayashi
- Organizer
  IEEE International Reliability Physics Symposium
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17K14667
[Presentation] Evaluation of Heavy-Ion-Induced SEU Cross Sections of a 65 nm Thin BOX FD-SOI Flip-Flops Based on Stacked Inverter2018
- Author(s)
  J. Furuta, K. Kojima, and K. Kobayashi
- Organizer
  The conference on Radiation and its Effects on Components and Systems
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-17K14667
[Presentation] Sensitivity to Soft Errors of NMOS and PMOS Transistors Evaluated by Latches with Stacking Structures in a 65 nm FDSOI Proces2018
- Author(s)
  K. Yamada, H. Maruoka, J. Furuta, and K. Kobayashi
- Organizer
  IEEE International Reliability Physics Symposium
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H02677
[Presentation] Evaluation of Heavy-Ion-Induced SEU Cross Sections of a 65 nm Thin BOX FD-SOI Flip-Flops Based on Stacked Inverter2018
- Author(s)
  Jun Furuta
- Organizer
  The conference on Radiation and its Effects on Components and Systems
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H02677
[Presentation] Circuit-level Simulation Methodology for Random Telegraph Noise by Using Verilog-AMS2017
- Author(s)
  T. Komawaki, M. Yabuuchi, R. Kishida, J. Furuta, T. Matsumoto, and K. Kobayashi
- Organizer
  Circuit-level Simulation Methodology for Random Telegraph Noise by Using Verilog-AMS
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H02677
[Presentation] Plasma Induced Damage Depending on Antenna Layers in Ring Oscillators2017
- Author(s)
  R. Kishida, J. Furuta, and K. Kobayashi
- Organizer
  International Conference on Solid State Devices and Materials
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H02677
[Presentation] Radiation-Hardened Flip-Flops with Low Delay Overheads Using PMOS Pass-Transistors to Suppress a SET Pulse in a 65 nm FDSOI Process2017
- Author(s)
  K. Yamada, H. Maruoka, J. Furuta, and K. Kobayashi
- Organizer
  The conference on Radiation and its Effects on Components and Systems
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H02677
[Presentation] A Flip-Flop with High Soft-error Tolerance and Small Power and Delay Overheads2017
- Author(s)
  K. Yamada, H. Maruoka, J. Furuta, and K. Kobayashi
- Organizer
  Symposium on Low-Power and High-Speed Chips (COOL Chips)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H02677
[Presentation] A 16 nm FinFET Radiation-hardened Flip-Flop, Bistable Cross-coupled Dual-Modular-Redundancy FF for Terrestrial and Outer-Space Highly-reliable Systems2017
- Author(s)
  K. Kobayashi, J. Furuta, H. Maruoka, M. Hifumi, S. Kumashiro, T. Kato, and S. Kohri
- Organizer
  IEEE International Reliability Physics Symposium
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H02677
[Presentation] Influence of Layout Structures to Soft Errors Caused by Higher-energy Particles on 28/65 nm FDSOI Flip-Flops2017
- Author(s)
  M. Hifumi, H. Maruoka, S. Umehara, K. Yamada, J. Furuta, and K. Kobayashi
- Organizer
  IEEE International Reliability Physics Symposium
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H02677
[Presentation] A Radiation-hard Layout Structure to Control Back-Gate Biases in a 65 nm Thin-BOX FDSOI Process2016
- Author(s)
  J. Yamaguchi, J. Furuta, and K. Kobayashi
- Organizer
  SOI-3D-Subthreshold Microelectronics Technology Unified Conference
- Place of Presentation
  Burlingame, CA, USA
- Year and Date
  2016-10-10
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H02677
[Presentation] A Non-Redundant Low-Power Flip Flop with Stacked Transistors in a 65 nm Thin BOX FDSOI Process2016
- Author(s)
  H. Maruoka, M. Hifumi, J. Furuta, and K. Kobayashi
- Organizer
  The conference on Radiation and its Effects on Components and Systems
- Place of Presentation
  Bremen, Germany
- Year and Date
  2016-09-19
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H02677
[Presentation] Radiation Hardness Evaluations of FFs on 28nm and 65nm Thin BOX FD-SOI Processes by Heavy-Ion Irradiation2015
- Author(s)
  M. Hifumi, E. Sonezaki, J. Furuta, and K. Kobayashi
- Organizer
  International Workshop on Radiation Effects on Semiconductor Devices for Space Applications
- Place of Presentation
  Gunma, Japan
- Year and Date
  2015-11-11
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26889037
[Presentation] A Radiation-Hardened Non-redundant Flip-Flop, Stacked Leveling Critical Charge Flip-Flop in a 65 nm Thin BOX FD-SOI Process2015
- Author(s)
  山口, 古田, 小林
- Organizer
  The conference on Radiation and its Effects on Components and Systems
- Place of Presentation
  Moscow, Russia
- Year and Date
  2015-09-10
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H02677
[Presentation] Anasysis of BOX Layer Thickness on SERs of 65 and 28nm FD-SOI Processes by a Monte-Carlo Based Simulation Tool2015
- Author(s)
  張, 神田, 山口, 古田
- Organizer
  International Conference on Solid State Devices and Materials
- Place of Presentation
  Moscow, Russia
- Year and Date
  2015-09-30
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H02677
[Presentation] PHITS-TCADシミュレーションによる完全空乏型SOIプロセスにおけるBOX層の厚さと基板バイアスによるソフトエラー耐性の評価2015
- Author(s)
  張魁元, 神田翔平, 山口潤己, 古田潤, 小林和淑
- Organizer
  DAシンポジウム
- Place of Presentation
  石川県加賀市
- Year and Date
  2015-08-26
- Data Source
  KAKENHI-PROJECT-26889037
[Presentation] 65nm薄膜FD-SOIとバルクプロセスにおけるアンテナダイオード起因ソフトエラーの実測と評価2015
- Author(s)
  曽根崎詠二, 古田潤, 小林和淑
- Organizer
  DAシンポジウム
- Place of Presentation
  石川県加賀市
- Year and Date
  2015-08-26
- Data Source
  KAKENHI-PROJECT-26889037
[Presentation] 65nmFD-SOIプロセスにおける非冗長化耐ソフトエラーフリップフロップのエラー耐性評価2015
- Author(s)
  山口潤己, 古田潤, 小林和淑
- Organizer
  DAシンポジウム
- Place of Presentation
  石川県加賀市
- Year and Date
  2015-08-26
- Data Source
  KAKENHI-PROJECT-26889037
[Presentation] 28 nm UTBB FD-SOIプロセスにおけるα線照射による低電圧動作時のFFのソフトエラー耐性評価2015
- Author(s)
  一二三潤, 曽根崎詠二, 山口潤己, 古田潤, 小林和淑
- Organizer
  DAシンポジウム
- Place of Presentation
  石川県加賀市
- Year and Date
  2015-08-26
- Data Source
  KAKENHI-PROJECT-26889037
[Presentation] Analysis of the Soft Error Rates on 65-nm SOTB and 28-nm UTBB FD-SOI Structures by a PHITS- TCAD Based Simulation Tool2015
- Author(s)
  張, 神田, 山口, 古田, 小林
- Organizer
  International Conference on Simulation of Semiconductor Processes and Devices
- Place of Presentation
  Washington DC, USA
- Year and Date
  2015-09-10
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H02677
[Presentation] A Radiation-Hardened Non-redundant Flip-Flop, Stacked Leveling Critical Charge Flip-Flop in a 65 nm Thin BOX FD-SOI Process2015
- Author(s)
  J. Yamaguchi, J. Furuta, and K. Kobayashi
- Organizer
  The conference on Radiation and its Effects on Components and Systems
- Place of Presentation
  Moscow, Russia
- Year and Date
  2015-09-14
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26889037
[Presentation] 28 nm UTBB FD-SOIプロセスにおけるデバイスシミュレーションによるのソフトエラー耐性の評価2015
- Author(s)
  梅原成宏, 張魁元, 一二三潤, 古田潤, 小林和淑
- Organizer
  DAシンポジウム
- Place of Presentation
  石川県加賀市
- Year and Date
  2015-08-26
- Data Source
  KAKENHI-PROJECT-26889037

1. Kobayashi Kazutoshi (70252476)

# of Collaborated Projects: 1 results

# of Collaborated Products: 16 results
2. 西澤真一 (40757522)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
3. 吉河武文 (60636702)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
4. 松本高士 (70417369)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
5. Stoffels Steve

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
6. Posthuma Niels

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
7. Li Xiangdong

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
8. Decoutere Stefaan

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results

Furuta Jun 古田 潤

furuta jun 古田 潤

Research Projects

Research Products

Co-Researchers

宇宙環境における次世代パワー半導体の寿命予測Principal Investigator

Principal Investigator

Project Period (FY)

Research Category

Review Section

Research Institution

Radiation-hardened Design for Low-power SupercomputersPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

An IoT that can keep on running over years efficiently and reliably

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Low Power/delay Radiation-hardended Flip-flop in a FD-SOI proessPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

[Journal Article] Radiation-Hardened Structure to Reduce Sensitive Range of a Stacked Structure for FDSOI2019

Author(s)

Journal Title

DOI

Data Source

[Journal Article] A Low-Power Radiation-Hardened Flip-Flop with Stacked Transistors in a 65 nm FDSOI Process2018

Author(s)

Journal Title

DOI

NAID

ISSN

Language

Data Source

[Journal Article] Evaluation of plasma-induced damage and bias temperature instability depending on type of antenna layer using current-starved ring oscillators2018

Author(s)

Journal Title

DOI

NAID

ISSN

Data Source

[Journal Article] Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model2017

Author(s)

Journal Title

DOI

NAID

ISSN

Language

Data Source

[Journal Article] A Radiation-Hardened Non-Redundant Flip-Flop, Stacked Leveling Critical Charge Flip-Flop in a 65 nm Thin BOX FD-SOI Process2016

Author(s)

Journal Title

DOI

Data Source

[Journal Article] A Radiation-Hardened Non-redundant Flip-Flop, Stacked Leveling Critical Charge Flip-Flop in a 65 nm Thin BOX FD-SOI Process2016

Author(s)

Journal Title

Data Source

[Journal Article] Impact of Cell Distance and Well-contact Density on Neutron-induced Multiple Cell Upsets2015

Author(s)

Journal Title

DOI

NAID

ISSN

Language

Data Source

[Patent] D-type Flip-flop Circuit2019

Inventor(s)

Industrial Property Rights Holder

Industrial Property Rights Type

Filing Date

Data Source

Furuta Jun 古田潤

furuta jun 古田潤