furuta jun 古田潤

Researcher Number	30735767
Affiliation *help	2016 – 2018 : 京都工芸繊維大学, 電気電子工学系, 助教 2015 – 2016 : 京都工芸繊維大学, グリーンイノベーションセンター, 特任助教 2014 – 2015 : 京都工芸繊維大学, 学内共同利用施設等, 助教
Review Section/Research Field	Principal Investigator Electron device/Electronic equipment Except Principal Investigator Computer system
Keywords	Principal Investigator フリップフロップ / ソフトエラー / 重イオン / 中性子 / 低電力 / FD-SOI / 完全空乏型トランジスタ Except Principal Investigator RTN / ランダムテレグラフノイズ / 経年劣化 … More

低電力スーパーコンピュータの高信頼性設計法の提案Principal InvestigatorOngoing
- Principal Investigator
  
  古田潤
- Project Period (FY)
  2017 – 2019
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  Kyoto Institute of Technology
高効率かつ高信頼で長時間動作可能な「もの」のインターネット機器の実現Ongoing
- Principal Investigator
  
  小林和淑
- Project Period (FY)
  2015 – 2018
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system
- Research Institution
  Kyoto Institute of Technology
Low Power/delay Radiation-hardended Flip-flop in a FD-SOI proessPrincipal Investigator
- Principal Investigator
  
  furuta jun
- Project Period (FY)
  2014 – 2015
- Research Category
  
  Grant-in-Aid for Research Activity start-up
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  Kyoto Institute of Technology

All 2018 2017 2016 2015

All Journal Article Presentation

[Journal Article] Evaluation of plasma-induced damage and bias temperature instability depending on type of antenna layer using current-starved ring oscillators2018
- Author(s)
  Kishida Ryo、Furuta Jun、Kobayashi Kazutoshi
- Journal Title
  
  Japanese Journal of Applied Physics
  
  Volume : 57
- DOI
  10.7567/jjap.57.04fd12
- Data Source
  KAKENHI-PROJECT-15H02677
[Journal Article] Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model2017
- Author(s)
  T. Komawaki, M. Yabuuchi, R. Kishida, J. Furuta, T. Matsumoto, and K. Kobayashi
- Journal Title
  
  IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
  
  Volume : E-100A Pages : 2758-2763
- DOI
  10.1587/transfun.e100.a.2758
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-15H02677
[Journal Article] A Radiation-Hardened Non-redundant Flip-Flop, Stacked Leveling Critical Charge Flip-Flop in a 65 nm Thin BOX FD-SOI Process2016
- Author(s)
  Jun Furuta, Junki Yamaguchi, Kazutoshi Kobayashi
- Journal Title
  
  IEEE Transactions on Neuclear Science
  
  Volume : 1 Pages : 1-1
- Peer Reviewed / Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-26889037
[Journal Article] A Radiation-Hardened Non-Redundant Flip-Flop, Stacked Leveling Critical Charge Flip-Flop in a 65 nm Thin BOX FD-SOI Process2016
- Author(s)
  J. Furuta, J. Yamaguchi, and K. Kobayashi
- Journal Title
  
  IEEE Trans. on Nuclear Science
  
  Volume : 63 Pages : 2080-2086
- DOI
  10.1109/tns.2016.2543745
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-15H02677
[Journal Article] Impact of Cell Distance and Well-contact Density on Neutron-induced Multiple Cell Upsets2015
- Author(s)
  古田, 小林, 小野寺
- Journal Title
  
  IEICE Trans. on Electronics
  
  Volume : E98-C Pages : 1745-1353
- DOI
  10.1587/transele.e98.c.298
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-15H02677
[Presentation] Sensitivity to Soft Errors of NMOS and PMOS Transistors Evaluated by Latches with Stacking Structures in a 65 nm FDSOI Proces2018
- Author(s)
  K. Yamada, H. Maruoka, J. Furuta, and K. Kobayashi
- Organizer
  IEEE International Reliability Physics Symposium
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H02677
[Presentation] Plasma Induced Damage Depending on Antenna Layers in Ring Oscillators2017
- Author(s)
  R. Kishida, J. Furuta, and K. Kobayashi
- Organizer
  International Conference on Solid State Devices and Materials
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H02677
[Presentation] Circuit-level Simulation Methodology for Random Telegraph Noise by Using Verilog-AMS2017
- Author(s)
  T. Komawaki, M. Yabuuchi, R. Kishida, J. Furuta, T. Matsumoto, and K. Kobayashi
- Organizer
  Circuit-level Simulation Methodology for Random Telegraph Noise by Using Verilog-AMS
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H02677
[Presentation] Radiation-Hardened Flip-Flops with Low Delay Overheads Using PMOS Pass-Transistors to Suppress a SET Pulse in a 65 nm FDSOI Process2017
- Author(s)
  K. Yamada, H. Maruoka, J. Furuta, and K. Kobayashi
- Organizer
  The conference on Radiation and its Effects on Components and Systems
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H02677
[Presentation] Influence of Layout Structures to Soft Errors Caused by Higher-energy Particles on 28/65 nm FDSOI Flip-Flops2017
- Author(s)
  M. Hifumi, H. Maruoka, S. Umehara, K. Yamada, J. Furuta, and K. Kobayashi
- Organizer
  IEEE International Reliability Physics Symposium
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H02677
[Presentation] A Flip-Flop with High Soft-error Tolerance and Small Power and Delay Overheads2017
- Author(s)
  K. Yamada, H. Maruoka, J. Furuta, and K. Kobayashi
- Organizer
  Symposium on Low-Power and High-Speed Chips (COOL Chips)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H02677
[Presentation] A 16 nm FinFET Radiation-hardened Flip-Flop, Bistable Cross-coupled Dual-Modular-Redundancy FF for Terrestrial and Outer-Space Highly-reliable Systems2017
- Author(s)
  K. Kobayashi, J. Furuta, H. Maruoka, M. Hifumi, S. Kumashiro, T. Kato, and S. Kohri
- Organizer
  IEEE International Reliability Physics Symposium
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H02677
[Presentation] A Non-Redundant Low-Power Flip Flop with Stacked Transistors in a 65 nm Thin BOX FDSOI Process2016
- Author(s)
  H. Maruoka, M. Hifumi, J. Furuta, and K. Kobayashi
- Organizer
  The conference on Radiation and its Effects on Components and Systems
- Place of Presentation
  Bremen, Germany
- Year and Date
  2016-09-19
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H02677
[Presentation] A Radiation-hard Layout Structure to Control Back-Gate Biases in a 65 nm Thin-BOX FDSOI Process2016
- Author(s)
  J. Yamaguchi, J. Furuta, and K. Kobayashi
- Organizer
  SOI-3D-Subthreshold Microelectronics Technology Unified Conference
- Place of Presentation
  Burlingame, CA, USA
- Year and Date
  2016-10-10
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H02677
[Presentation] PHITS-TCADシミュレーションによる完全空乏型SOIプロセスにおけるBOX層の厚さと基板バイアスによるソフトエラー耐性の評価2015
- Author(s)
  張魁元, 神田翔平, 山口潤己, 古田潤, 小林和淑
- Organizer
  DAシンポジウム
- Place of Presentation
  石川県加賀市
- Year and Date
  2015-08-26
- Data Source
  KAKENHI-PROJECT-26889037
[Presentation] A Radiation-Hardened Non-redundant Flip-Flop, Stacked Leveling Critical Charge Flip-Flop in a 65 nm Thin BOX FD-SOI Process2015
- Author(s)
  J. Yamaguchi, J. Furuta, and K. Kobayashi
- Organizer
  The conference on Radiation and its Effects on Components and Systems
- Place of Presentation
  Moscow, Russia
- Year and Date
  2015-09-14
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26889037
[Presentation] Radiation Hardness Evaluations of FFs on 28nm and 65nm Thin BOX FD-SOI Processes by Heavy-Ion Irradiation2015
- Author(s)
  M. Hifumi, E. Sonezaki, J. Furuta, and K. Kobayashi
- Organizer
  International Workshop on Radiation Effects on Semiconductor Devices for Space Applications
- Place of Presentation
  Gunma, Japan
- Year and Date
  2015-11-11
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26889037
[Presentation] 28 nm UTBB FD-SOIプロセスにおけるα線照射による低電圧動作時のFFのソフトエラー耐性評価2015
- Author(s)
  一二三潤, 曽根崎詠二, 山口潤己, 古田潤, 小林和淑
- Organizer
  DAシンポジウム
- Place of Presentation
  石川県加賀市
- Year and Date
  2015-08-26
- Data Source
  KAKENHI-PROJECT-26889037
[Presentation] 65nmFD-SOIプロセスにおける非冗長化耐ソフトエラーフリップフロップのエラー耐性評価2015
- Author(s)
  山口潤己, 古田潤, 小林和淑
- Organizer
  DAシンポジウム
- Place of Presentation
  石川県加賀市
- Year and Date
  2015-08-26
- Data Source
  KAKENHI-PROJECT-26889037
[Presentation] 65nm薄膜FD-SOIとバルクプロセスにおけるアンテナダイオード起因ソフトエラーの実測と評価2015
- Author(s)
  曽根崎詠二, 古田潤, 小林和淑
- Organizer
  DAシンポジウム
- Place of Presentation
  石川県加賀市
- Year and Date
  2015-08-26
- Data Source
  KAKENHI-PROJECT-26889037
[Presentation] 28 nm UTBB FD-SOIプロセスにおけるデバイスシミュレーションによるのソフトエラー耐性の評価2015
- Author(s)
  梅原成宏, 張魁元, 一二三潤, 古田潤, 小林和淑
- Organizer
  DAシンポジウム
- Place of Presentation
  石川県加賀市
- Year and Date
  2015-08-26
- Data Source
  KAKENHI-PROJECT-26889037
[Presentation] Analysis of the Soft Error Rates on 65-nm SOTB and 28-nm UTBB FD-SOI Structures by a PHITS- TCAD Based Simulation Tool2015
- Author(s)
  張, 神田, 山口, 古田, 小林
- Organizer
  International Conference on Simulation of Semiconductor Processes and Devices
- Place of Presentation
  Washington DC, USA
- Year and Date
  2015-09-10
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H02677
[Presentation] Anasysis of BOX Layer Thickness on SERs of 65 and 28nm FD-SOI Processes by a Monte-Carlo Based Simulation Tool2015
- Author(s)
  張, 神田, 山口, 古田
- Organizer
  International Conference on Solid State Devices and Materials
- Place of Presentation
  Moscow, Russia
- Year and Date
  2015-09-30
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H02677
[Presentation] A Radiation-Hardened Non-redundant Flip-Flop, Stacked Leveling Critical Charge Flip-Flop in a 65 nm Thin BOX FD-SOI Process2015
- Author(s)
  山口, 古田, 小林
- Organizer
  The conference on Radiation and its Effects on Components and Systems
- Place of Presentation
  Moscow, Russia
- Year and Date
  2015-09-10
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15H02677

1. 小林和淑 (70252476)

# of Collaborated Projects : 1results

# of Collaborated Products : 15results
2. 西澤真一 (40757522)

# of Collaborated Projects : 1results

# of Collaborated Products : 0results
3. 吉河武文 (60636702)

# of Collaborated Projects : 1results

# of Collaborated Products : 0results
4. 松本高士 (70417369)

# of Collaborated Projects : 1results

# of Collaborated Products : 2results

furuta jun 古田 潤

Research Projects

Research Products

Co-Researchers

低電力スーパーコンピュータの高信頼性設計法の提案Principal InvestigatorOngoing

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

高効率かつ高信頼で長時間動作可能な「もの」のインターネット機器の実現Ongoing

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Low Power/delay Radiation-hardended Flip-flop in a FD-SOI proessPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

[Journal Article] Evaluation of plasma-induced damage and bias temperature instability depending on type of antenna layer using current-starved ring oscillators2018

Author(s)

Journal Title

DOI

Data Source

[Journal Article] Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model2017

Author(s)

Journal Title

DOI

Data Source

[Journal Article] A Radiation-Hardened Non-redundant Flip-Flop, Stacked Leveling Critical Charge Flip-Flop in a 65 nm Thin BOX FD-SOI Process2016

Author(s)

Journal Title

Data Source

[Journal Article] A Radiation-Hardened Non-Redundant Flip-Flop, Stacked Leveling Critical Charge Flip-Flop in a 65 nm Thin BOX FD-SOI Process2016

Author(s)

Journal Title

DOI

Data Source

[Journal Article] Impact of Cell Distance and Well-contact Density on Neutron-induced Multiple Cell Upsets2015

Author(s)

Journal Title

DOI

Data Source

[Presentation] Sensitivity to Soft Errors of NMOS and PMOS Transistors Evaluated by Latches with Stacking Structures in a 65 nm FDSOI Proces2018

Author(s)

Organizer

Data Source

[Presentation] Plasma Induced Damage Depending on Antenna Layers in Ring Oscillators2017

Author(s)

Organizer

Data Source

[Presentation] Circuit-level Simulation Methodology for Random Telegraph Noise by Using Verilog-AMS2017

Author(s)

Organizer

Data Source

[Presentation] Radiation-Hardened Flip-Flops with Low Delay Overheads Using PMOS Pass-Transistors to Suppress a SET Pulse in a 65 nm FDSOI Process2017

Author(s)

Organizer

Data Source

[Presentation] Influence of Layout Structures to Soft Errors Caused by Higher-energy Particles on 28/65 nm FDSOI Flip-Flops2017

Author(s)

Organizer

Data Source

[Presentation] A Flip-Flop with High Soft-error Tolerance and Small Power and Delay Overheads2017

Author(s)

Organizer

Data Source

[Presentation] A 16 nm FinFET Radiation-hardened Flip-Flop, Bistable Cross-coupled Dual-Modular-Redundancy FF for Terrestrial and Outer-Space Highly-reliable Systems2017

Author(s)

Organizer

Data Source

[Presentation] A Non-Redundant Low-Power Flip Flop with Stacked Transistors in a 65 nm Thin BOX FDSOI Process2016

Author(s)

Organizer

Place of Presentation

Year and Date

Data Source

furuta jun 古田潤