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衛藤 優  エトウ ユウ

ORCIDConnect your ORCID iD *help
Researcher Number 31041907
Other IDs
Affiliation (based on the past Project Information) *help 2026: 奈良工業高等専門学校, 情報工学科, 助教
Review Section/Research Field
Except Principal Investigator
Basic Section 60040:Computer system-related
Keywords
Except Principal Investigator
排他制御素子 / スキャン設計 / 大域非同期・局所同期設計 / 非同期式回路 / テスト容易化設計 / ネットワーク中心性 / 機械学習 / EDA / DFT / VLSI
  • Research Projects

    (2 results)
  • Co-Researchers

    (2 People)
  •  中心性認識AIを用いたTestable-by-Construction VLSIの統一フレームワーク

    • Principal Investigator
      山口 賢一
    • Project Period (FY)
      2026 – 2028
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Review Section
      Basic Section 60040:Computer system-related
    • Research Institution
      Nara National College of Technology
  •  A Design for Testability Method for Asynchronous Sequential Elements within/out Scan Design

    • Principal Investigator
      岩田 大志
    • Project Period (FY)
      2026 – 2030
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Review Section
      Basic Section 60040:Computer system-related
    • Research Institution
      Nara National College of Technology
  • 1.  山口 賢一 (50370010)
    # of Collaborated Projects: 2 results
    # of Collaborated Products: 0 results
  • 2.  岩田 大志 (50613139)
    # of Collaborated Projects: 2 results
    # of Collaborated Products: 0 results

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