Ochi Hiroyuki 越智裕之

… Alternative Names

OCHI Hiroyuki 越智裕之

越智裕之オチヒロユキ

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Researcher Number	40264957
Other IDs
External Links
Affiliation (Current)	2025: 立命館大学, 情報理工学部, 教授
Affiliation (based on the past Project Information) *help	2016 – 2021: 立命館大学, 情報理工学部, 教授 2013: 立命館大学, 情報理工学部, 教授 2012: 京都大学, 大学院・情報学研究科, 准教授 2010 – 2012: 京都大学, 情報学研究科, 准教授 2007 – 2008: Kyoto University, Graduate School of Informatics, Associate Professor … More 2007 – 2008: Kyoto University, 情報学研究科, 准教授 2005 – 2006: 京都大学, 情報学研究科, 助教授 1997 – 1998: 広島市立大学, 情報科学部, 助教授 Less
Review Section/Research Field	Principal Investigator Computer system/Network / Basic Section 60040:Computer system-related / Computer system / 計算機科学 Except Principal Investigator Computer system/Network / Electron device/Electronic equipment
Keywords	Principal Investigator オンチップ太陽電池 / FPGA / Self-poweredなセンサノードチップ / 電源自給型センサノードチップ / マイクロエナジーハーベスティング / フローティングゲート / メタルフリンジキャパシタ / プログラマブルROM / チャージポンプ回路 / 超低消費電力設計 … More / アナログデジタル混載集積回路 / 2段昇圧型チャージポンプ回路 / 標準CMOSプロセス互換不揮発性メモリ / 面積効率を考慮したチャージポンプ回路 / 不揮発性メモリ / チャージポンプ型昇圧回路 / 超低電圧・超低消費電力回路 / エナジーハーベスティング / センサデバイス / アドホックネットワーク / マスクROM / 長期信頼性 / 非接触電源供給 / 非接触通信 / PCA / プロセスばらつき / 集積回路設計自動化 / 非同期回路 / 再構成デバイス / フィールドプログラマブルケ-トアレイ / レイアウトドリブン設計 / データパスレイアウト優先設計 / セルベース設計 / 配線容量 / 低消費電力設計 … More Except Principal Investigator FPGA / coarse-grained reconfigurable device / plastic cell architecture / dvnamic self-reconfiguration / reconfigurable architecture / Plastc Cell Architecture / レイアウト合成 / 高位合成 / 性能及び回路面積の比較検討 / Plastic Cell Architecture / セルアレイ型再構成アーキテクチャ / 粗粒度再構成デバイス / Plastic Cell Architwcture / 動的・自律的再構成 / 再構成アーキテクチャ / 電子回路CAD / 集積回路設計 / モンテカルロ法 / タイミング解析 / CAD / 集積回路設計技術 Less

CMOS-compatible ultra-low-power non-volatile memory and its application to sensor node chipPrincipal Investigator
- Principal Investigator
  
  Ochi Hiroyuki
- Project Period (FY)
  2019 – 2021
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Ritsumeikan University
Highly efficient voltage booster for embedded on-chip solar cellsPrincipal Investigator
- Principal Investigator
  
  Ochi Hiroyuki
- Project Period (FY)
  2016 – 2018
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system
- Research Institution
  Ritsumeikan University
Architecture for Large-scale Long-term Digital Storage SystemPrincipal Investigator
- Principal Investigator
  
  OCHI Hiroyuki
- Project Period (FY)
  2011 – 2013
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Ritsumeikan University
  Kyoto University
Acceleration of Timing Analysis using Monte Carlo Methods
- Principal Investigator
  
  SATO Takashi
- Project Period (FY)
  2010 – 2012
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  Kyoto University
Development of FPGA Design Methodology Considering Process VariationPrincipal Investigator
- Principal Investigator
  
  OCHI Hiroyuki
- Project Period (FY)
  2006 – 2008
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system/Network
- Research Institution
  Kyoto University
Development of Coarse-Grained Dynamic Self-Reconfigurable Device aiming for Reduction of Reconfiguration Overhead
- Principal Investigator
  
  NAKAMURA Yukihiro
- Project Period (FY)
  2005 – 2007
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Ritsumeikan University
  Kyoto University
RISCプロセッサのデータパスレイアウト優先設計Principal Investigator
- Principal Investigator
  
  越智裕之
- Project Period (FY)
  1997 – 1998
- Research Category
  
  Grant-in-Aid for Encouragement of Young Scientists (A)
- Research Field
  
  計算機科学
- Research Institution
  Hiroshima City University

[Journal Article] A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis2013
- Author(s)
  Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi and Takashi Sato
- Journal Title
  
  IEICE Trans. Electron.
  
  Volume: E96.C Issue: 4 Pages: 454-462
- DOI
  10.1587/transele.E96.C.454
- NAID
  10031182821
- ISSN
  0916-8524, 1745-1353
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22360143
[Journal Article] Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element2013
- Author(s)
  Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi and Takashi Sato
- Journal Title
  
  IEICE Trans. Electron.
  
  Volume: E96.C Issue: 4 Pages: 473-481
- DOI
  10.1587/transele.E96.C.473
- NAID
  10031182823
- ISSN
  0916-8524, 1745-1353
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22360143
[Journal Article] A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits2012
- Author(s)
  Junya Kawashima, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato
- Journal Title
  
  IEICE Trans. Fundamentals
  
  Volume: E95.A Issue: 12 Pages: 2242-2250
- DOI
  10.1587/transfun.E95.A.2242
- NAID
  10031161358
- ISSN
  0916-8508, 1745-1337
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22360143
[Journal Article] Bayesian Estimation of Multi-Trap RTN Parameters Using Markov Chain Monte Carlo Method2012
- Author(s)
  Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato
- Journal Title
  
  IEICE Trans. Fundamentals
  
  Volume: E95.A Issue: 12 Pages: 2272-2283
- DOI
  10.1587/transfun.E95.A.2272
- NAID
  10031161361
- ISSN
  0916-8508, 1745-1337
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22360143
[Journal Article] Reliability evaluation environment for exploring design space of coarse-grained reconfigurable architectures2010
- Author(s)
  Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato
- Journal Title
  
  IEICE Transactions of Fundamentals on Electronics, Communications and Computer Sciences
  
  Volume: Vol.E93-A, No.12 Pages: 2524-2532
- NAID
  10027985803
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22360143
[Journal Article] An Asyn- chronous IEEE-754-Standard Single- Precision Floating-Point Divider for FPGA2009
- Author(s)
  Masayuki Hiromoto, Hiroyuki Ochi, and Yukihiro Nakamura
- Journal Title
  
  IPSJ Trans. on System LSI Design Methodology Vol.2
  
  Pages: 103-113
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18500036
[Journal Article] An Asynchronous IEEE-754-Standard Single-Precision Floating-Point Divider for FPGA2009
- Author(s)
  Masayuki Hiromoto, Hiroyuki Ochi, Yukihiro Nakamura
- Journal Title
  
  IPSJ Trans. on System LSI Design Methodology 2
  
  Pages: 103-113
- NAID
  130000120669
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18500036
[Journal Article] A Simulation Platform for Designing Cell-Array-Based Self-Reconfigurable Architecture2007
- Author(s)
  [1] Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura
- Journal Title
  
  IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences Vol. E90-A, No.4
  
  Pages: 784-791
- NAID
  110007519135
- Data Source
  KAKENHI-PROJECT-17300016
[Journal Article] 非同期単精度浮動小数点除算器の方式検討とFPGA実装2007
- Author(s)
  廣本正之, 高橋温子, 神山真一, 越智裕之, 中村行宏
- Journal Title
  
  電子情報通信学会技術報告(VLSI設計技術研究会2007年5月11日発表予定) vol.107,no.32
  
  Pages: 19-24
- NAID
  110006290350
- Data Source
  KAKENHI-PROJECT-18500036
[Journal Article] セルアレイ型自己再構成デバイスの設計検討のためのシミュレーション環境2006
- Author(s)
  [2] 神山真一, 泉知論, 越智裕之, 中村行宏
- Journal Title
  
  第19回回路とシステム軽井沢ワークショップ論文集
  
  Pages: 571-576
- Data Source
  KAKENHI-PROJECT-17300016
[Journal Article] 自己再構成アーキテクチャ評価検討のための合成ツール2006
- Author(s)
  [5] 廣本正之, 神山真一, 中原健太郎, 筒井弘, 越智裕之, 中村行宏
- Journal Title
  
  情報処理学会シンポジウムシリーズ(DAシンポジウム2006論文集) Vol. 2006, no. 7
  
  Pages: 181-186
- Data Source
  KAKENHI-PROJECT-17300016
[Journal Article] ALUアレイ型動的再構成可能デバイスの性能見積もりとこれを用いた語長の検討2006
- Author(s)
  [4] 神山真一, 森江太士, 廣本正之, 泉知論, 越智裕之, 中村行宏
- Journal Title
  
  第28回パルテノン研究会資料集
  
  Pages: 56-72
- Data Source
  KAKENHI-PROJECT-17300016
[Journal Article] セルアレイ型自己再構成アーキテクチャ評価検討のためのコンパイラ2006
- Author(s)
  [3] 廣本正之, 神山真一, 中原健太郎, 筒井弘, 越智裕之, 中村行宏
- Journal Title
  
  電子情報通信学会技術研究報告(RECONF研) Vol. 106, No. 49
  
  Pages: 7-12
- NAID
  110004741127
- Data Source
  KAKENHI-PROJECT-17300016
[Journal Article] 自己再構成デバイスの設計検討のためのアーキテクチャモデルとシミュレーション環境2005
- Author(s)
  神山真一, 森江太士, 中原健太郎, 泉知論, 越智裕之, 中村行宏
- Journal Title
  
  第27回パルテノン研究会資料集 27
  
  Pages: 37-44
- Data Source
  KAKENHI-PROJECT-17300016
[Journal Article] 演算粒度評価環境の構築と自己再構成デバイスアーキテクチャ検討2005
- Author(s)
  神山真一, 森江太士, 中原健太郎, 泉知論, 越智裕之, 中村行宏
- Journal Title
  
  電子情報通信学会技術研究報告,RECONF2005-36, 105・287
  
  Pages: 37-42
- NAID
  110003494618
- Data Source
  KAKENHI-PROJECT-17300016
[Patent] 太陽電池、複合太陽電池および集積回路2013
- Inventor(s)
  越智裕之、佐藤高史、池辺卓
- Industrial Property Rights Holder
  国立大学法人京都大学
- Industrial Property Rights Type
  特許
- Industrial Property Number
  2013-020277
- Filing Date
  2013
- Data Source
  KAKENHI-PROJECT-23300015
[Patent] 太陽電池, 複合太陽電池および集積回路2013
- Inventor(s)
  越智裕之, 佐藤高史, 池辺卓
- Industrial Property Rights Holder
  国立大学法人京都大学
- Industrial Property Rights Type
  特許
- Industrial Property Number
  2013-020277
- Filing Date
  2013-02-05
- Data Source
  KAKENHI-PROJECT-23300015
[Presentation] Zero-standby-power Nonvolatile Standard Cell Memory Using FiCC for IoT Processors with Intermittent Operations2022
- Author(s)
  Yuki Abe, Kazutoshi Kobayashi, Jun Shiomi, Hiroyuki Ochi
- Organizer
  IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 25)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19K11889
[Presentation] Nonvolatile SRAM Using Fishbone-in-Cage Capacitor in a 180 nm Standard CMOS Process for Zero-standby and Instant-powerup Embedded Memory on IoT2021
- Author(s)
  Takaki Urabe, Hiroyuki Ochi, and Kazutoshi Kobayashi
- Organizer
  IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 24)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19K11889
[Presentation] 間欠動作を行うIoT向けプロセッサに適したFiCCを用いた不揮発スタンダードセルメモリの実測評価2021
- Author(s)
  阿部佑貴, 小林和淑, 塩見準, 越智裕之
- Organizer
  情報処理学会DAシンポジウム2021, pp.3-8
- Data Source
  KAKENHI-PROJECT-19K11889
[Presentation] 太陽電池混載チップでのCMOS互換回路による電源電圧変動に頑強な温度センサの測定2021
- Author(s)
  室原脩人, 坂野達也, 木村知也, 今川隆司, 越智裕之
- Organizer
  信学技報, vol. 120, no. 400, VLD2020-74, pp. 32-37
- Data Source
  KAKENHI-PROJECT-19K11889
[Presentation] FiCCを用いたCMOS互換な不揮発性メモリ素子の閾値電圧特性の測定ならびに読み出し方式検討2019
- Author(s)
  田中一平, 宮川尚之, 木村知也, 今川隆司, 越智裕之
- Organizer
  情報処理学会DAシンポジウム2019
- Data Source
  KAKENHI-PROJECT-19K11889
[Presentation] FiCCを用いたCMOS互換な不揮発性メモリ実現に向けた素子特性測定2019
- Author(s)
  田中一平, 宮川尚之, 木村知也, 今川隆司, 越智裕之
- Organizer
  電子情報通信学会VLSI設計技術研究会
- Data Source
  KAKENHI-PROJECT-19K11889
[Presentation] FiCCを用いたCMOS互換な超低消費電力不揮発性メモリ素子の特性測定回路の設計と試作2018
- Author(s)
  田中一平, 宮川尚之, 木村知也, 今川隆司, 越智裕之
- Organizer
  デザインガイア2018 (電子情報通信学会VLSI設計技術研究会)
- Data Source
  KAKENHI-PROJECT-16K00085
[Presentation] FiCC:高集積向け耐クロストークノイズメタルフリンジキャパシタ2017
- Author(s)
  宮川尚之, 木村知也, 越智裕之
- Organizer
  電子情報通信学会VLSI設計技術研究会
- Place of Presentation
  沖縄県青年会館（沖縄県・那覇市）
- Year and Date
  2017-03-02
- Data Source
  KAKENHI-PROJECT-16K00085
[Presentation] 太陽電池混載チップ向けCMOS 互換温度・照度センサ2017
- Author(s)
  坂野達也, 木村知也, 今川隆司, 越智裕之
- Organizer
  電子情報通信学会VLSI設計技術研究会
- Data Source
  KAKENHI-PROJECT-16K00085
[Presentation] マイクロエナジーハーベスティングのための2段昇圧型チャージポンプ回路2016
- Author(s)
  木村知也, 越智裕之
- Organizer
  電子情報通信学会VLSI設計技術研究会
- Place of Presentation
  立命館大学大阪いばらきキャンパス（大阪府・茨木市）
- Year and Date
  2016-11-28
- Data Source
  KAKENHI-PROJECT-16K00085
[Presentation] 低電圧起動回路を用いた省電力チップ間非接触通信回路2014
- Author(s)
  佐川善彦, 廣本正之, 佐藤高史, 越智裕之
- Organizer
  第166回システムとLSIの設計技術研究会
- Place of Presentation
  北九州国際会議場(福岡県)
- Year and Date
  2014-05-29
- Data Source
  KAKENHI-PROJECT-23300015
[Presentation] Evaluation of dependent node selection of histogram propagation based statistical timing analysis2013
- Author(s)
  Shiyi Zhang, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato
- Organizer
  電子情報通信学会総合大会
- Place of Presentation
  岐阜大学，岐阜市
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] Multi-trap RTN parameter extraction based on Bayesian inference2013
- Author(s)
  Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato
- Organizer
  International Symposium on Quality Electronic Design (ISQED)
- Place of Presentation
  Techmart Center, Santa Clara, USA
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] Multi-Trap RTN Parameter Extraction Based on Bayesian Inference2013
- Author(s)
  Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato
- Organizer
  International Symposium on Quality Electrical Design (ISQED) (Techmart Center
- Place of Presentation
  Santa Clara, USA
- Year and Date
  2013-03-06
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] Architecture for sealed wafer-scale mask ROM for long-term digital data preservation2013
- Author(s)
  Shinya Matsuda, Takashi Imagawa, Hiroshi Tsutsui, Takashi Sato, Yukihiro Nakamura, and Hiroyuki Ochi
- Organizer
  28th Intl. Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)
- Place of Presentation
  Yeosu, (Korea)
- Year and Date
  2013-07-01
- Data Source
  KAKENHI-PROJECT-23300015
[Presentation] ランダムウォーク線形回路解析のスレッド並列化における電圧源化排他制御の検討2013
- Author(s)
  岡崎剛, 筒井弘, 越智裕之, 佐藤高史
- Organizer
  電子情報通信学会総合大会
- Place of Presentation
  岐阜大学，岐阜市
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] Evaluation of dependent node selection of histogram propagation based statistical timing analysis2013
- Author(s)
  Shiyi Zhang, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato
- Organizer
  電子情報通信学会総合大会
- Place of Presentation
  岐阜大学,岐阜市
- Year and Date
  2013-03-19
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] 回路構造の異なるラッチの消費エネルギーの比較2013
- Author(s)
  藤田隆史, 筒井弘, 越智裕之, 佐藤高史
- Organizer
  電子情報通信学会総合大会
- Place of Presentation
  岐阜大学，岐阜市
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] Realization of frequency-domain circuit analysis through random walk2013
- Author(s)
  Tetsuro Miyakawa, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato
- Organizer
  ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC)
- Place of Presentation
  Pacifico Yokohama, Yokohama
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] 回路構造の異なるラッチの消費エネルギーの比較2013
- Author(s)
  藤田隆史, 筒井弘, 越智裕之, 佐藤高史
- Organizer
  電子情報通信学会総合大会
- Place of Presentation
  岐阜大学,岐阜市
- Year and Date
  2013-03-19
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] Acceleration Scheme for Monte Carlo Based SSTA using Generalized STA Processing Element2012
- Author(s)
  Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
- Organizer
  ACM/IEEE International Workshop on Timing Issues (TAU)
- Place of Presentation
  Taipei, Taiwan
- Year and Date
  2012-01-18
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] クリロフ部分空間法を用いた電源回路網解析の GPU 実装による高速化2012
- Author(s)
  森下拓海, 筒井弘, 越智裕之, 佐藤高史
- Organizer
  回路とシステムワークショップ
- Place of Presentation
  淡路夢舞台国際会議場，淡路市
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] 回路の最小動作電圧改善とその予測精度向上の一検討2012
- Author(s)
  川島潤也, 越智裕之, 筒井弘, 佐藤高史
- Organizer
  第25回回路とシステムワークショップ
- Place of Presentation
  淡路夢舞台国際会議場,淡路市
- Year and Date
  2012-07-31
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] GPU Acceleration of Cycle-Based Soft-Error Simulation for Reconfigurable Array Architectures2012
- Author(s)
  Takashi Imagawa, Takahiro Oue, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
- Organizer
  the 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2012)
- Place of Presentation
  B-con Plaza, Beppu, Oita, Japan
- Year and Date
  2012-03-08
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] 情報量規準を用いる RTN モデルパラメータ推定の自動化2012
- Author(s)
  清水裕史, 筒井弘, 越智裕之, 佐藤高史
- Organizer
  DA シンポジウム
- Place of Presentation
  ホテル下呂温泉水明館，下呂市
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] チップ試作による最小動作電圧予測手法の評価2012
- Author(s)
  川島潤也, 筒井弘, 越智裕之, 佐藤高史
- Organizer
  電子情報通信学会 ICD研究会
- Place of Presentation
  東京工業大学大岡山キャンパス東工大大蔵前会館ロイアルブルーホール,東京都
- Year and Date
  2012-12-17
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] Accurate I/O Buffer Impedance Self-Adjustment using Vth and Temperature Sensors2012
- Author(s)
  Zhi Li, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato
- Organizer
  デザインガイア
- Place of Presentation
  九州大学医学部百年講堂，福岡市
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] 回路の最小動作電圧改善とその予測精度向上の一検討2012
- Author(s)
  川島潤也, 越智裕之, 筒井弘, 佐藤高史
- Organizer
  回路とシステムワークショップ
- Place of Presentation
  淡路夢舞台国際会議場，淡路市
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] Acceleration Scheme for Monte Carlo Based SSTA using Generalized STA Processing Element2012
- Author(s)
  Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato
- Organizer
  ACM/IEEE International Workshop on Timing Issues (TAU)
- Place of Presentation
  National Taiwan University, Taipei, Taiwan
- Year and Date
  2012-01-18
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] Accurate I/O Buffer Impedance Self-Adjustment using Vth and Temperature Sensors2012
- Author(s)
  Zhi Li, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato
- Organizer
  デザインガイア
- Place of Presentation
  九州大学医学部百年講堂,福岡市
- Year and Date
  2012-11-27
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] チップ試作による最小動作電圧予測手法の評価2012
- Author(s)
  川島潤也, 筒井弘, 越智裕之, 佐藤高史
- Organizer
  電子情報通信学会 ICD研究会
- Place of Presentation
  東京工業大学大岡山キャンパス東工大蔵前会館ロイアルブルーホール，東京都
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] 情報量規準を用いるRTNモデルパラメータ推定の自動化2012
- Author(s)
  清水裕史, 筒井弘, 越智裕之, 佐藤高史
- Organizer
  DAシンポジウム
- Place of Presentation
  ホテル下呂温泉水明館,下呂市
- Year and Date
  2012-08-29
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] Statistical Observations of NBTI-Induced Threshold Voltage Shifts on Small Channel-Area Devices2012
- Author(s)
  Takashi Sato, Hiromitsu Awano, Hirofumi Shimizu, Hiroshi Tsutsui, Hiroyuki Ochi
- Organizer
  International Symposium on Quality Electrical Design (ISQED)
- Place of Presentation
  Santa Clara, CA USA
- Year and Date
  2012-03-20
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] Hardware Architecture for Accelerating Monte Carlo Based SSTA using Generalized STA Processing Element2012
- Author(s)
  Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
- Organizer
  the 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2012)
- Place of Presentation
  B-con Plaza, Beppu, Oita, Japan
- Year and Date
  2012-03-08
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] EM法によるMOSデバイス界面状態数の自動推定2011
- Author(s)
  清水裕史, 筒井弘, 越智裕之, 佐藤高史
- Organizer
  電子情報通信学会ソサイエティ大会
- Place of Presentation
  北海道大学,札幌キャンパス
- Year and Date
  2011-09-13
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] A fully pipelined implementation of Monte Carlo based SSTA on FPGAs2011
- Author(s)
  Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato
- Organizer
  International Symposium on Quality Electrical Design (ISQED)
- Place of Presentation
  Techmart Center, Santa Clara, USA
- Year and Date
  2011-03-16
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] A Stress-Parallelized Device Array for Efficient Bias-Temperature Stability Measurements2011
- Author(s)
  Takashi Sato, Tadamichi Kozaki, Takumi Uezono, Hiroshi Tsutsui, and Hiroyuki Ochi
- Organizer
  IEEE International Workshop on Design for Manufacturability and Yield 2011(DFM&Y)
- Place of Presentation
  San Diego Convention Center, San Diego, USA
- Year and Date
  2011-06-06
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] A Device Array for Efficient Bias-Temperature Instability Measurements2011
- Author(s)
  Takashi Sato, Tadamichi Kozaki, Takumi Uezono, Hiroshi Tsutsui, Hiroyuki Ochi
- Organizer
  European Solid-State Device Research Conference (ESSDERC)
- Place of Presentation
  Helsinki, Finland
- Year and Date
  2011-09-13
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] ヤコビ法を用いた電源回路網解析のGPU実装2011
- Author(s)
  森下拓海, 筒井弘, 越智裕之, 佐藤高史
- Organizer
  電子情報通信学会ソサイエティ大会
- Place of Presentation
  北海道大学,札幌キャンパス
- Year and Date
  2011-09-15
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] エネルギー最小化と動作保証を考慮したサブスレッショルド回路の設計指針の検討2011
- Author(s)
  川島潤也, 越智裕之, 筒井弘, 佐藤高史
- Organizer
  第24回回路とシステムワークショップ
- Place of Presentation
  淡路夢舞台国際会議場(兵庫県)
- Year and Date
  2011-08-02
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] A Device Array for Efficient Bias-Temperature Instability Measurements2011
- Author(s)
  Takashi Sato, Tadamichi Kozaki, Takumi Uezono, Hiroshi Tsutsui, a nd Hiroyuki Ochi
- Organizer
  European Solid-State Device Research Conference (ESSDERC)
- Place of Presentation
  Finlandia Hall, Helsinki, Finland
- Year and Date
  2011-09-13
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] ランダムテレグラフノイズモデル化のためのパラメータ推定法の検討2011
- Author(s)
  粟野皓光, 清水裕史, 筒井弘, 越智裕之, 佐藤高史
- Organizer
  電子情報通信学会技術研究報告(デザインガイア2011-VLSI設計の新しい大地-)
- Place of Presentation
  ニューウェルシティ宮崎(宮崎県)
- Year and Date
  2011-11-28
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] 複数不良領域を持つ回路歩留まり解析のための逐次重点的サンプリング法2011
- Author(s)
  片山健太朗, 筒井弘, 越智裕之, 佐藤高史
- Organizer
  情報処理学会DAシンポジウム2011
- Place of Presentation
  ホテル下呂温泉水明館(岐阜県)
- Year and Date
  2011-08-31
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] ゼロ分散推定重点的サンプリングを用いたランダムウォークによる線形回路の過渡解析2011
- Author(s)
  宮川哲朗, 筒井弘, 越智裕之, 佐藤高史
- Organizer
  電子情報通信学会技術研究報告(デザインガイア2011-VLSI設計の新しい大地-)
- Place of Presentation
  ニューウェルシティ宮崎(宮崎県)
- Year and Date
  2011-11-28
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] Acceleration of Random-Walk-Based Linear Circuit Analysis using Importance Sampling2011
- Author(s)
  Tetsuro Miyakawa, Koh Yamanaga, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
- Organizer
  GLSVLSI 2011
- Place of Presentation
  Lausanne, Switzerland
- Year and Date
  2011-05-04
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] A Sensor-Based Self-Adjustment Approach for Controlling I/O Buffer Impedance2011
- Author(s)
  Zhi Li, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
- Organizer
  IEICE Society Conference
- Place of Presentation
  Hokkaido University, Sapporo Campus
- Year and Date
  2011-09-15
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] A Stress-Parallelized Device Array for Efficient Bias-Temperature Stability Measurement2011
- Author(s)
  Takashi Sato, Tadamichi Kozaki, Takumi Uezono, Hiroshi Tsutsui, Hiroyuki Ochi
- Organizer
  IEEE International Workshop on Design for Manufacturability and Yield 2011 (DFM&Y)
- Place of Presentation
  San Diego, California, USA
- Year and Date
  2011-06-06
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] エネルギー最小化と動作保証を考慮したサブスレッショルド回路の設計指針の検討2011
- Author(s)
  川島潤也, 越智裕之, 筒井弘, 佐藤高史
- Organizer
  第24回回路とシステムワークショップ
- Place of Presentation
  淡路夢舞台国際会議場,淡路市
- Year and Date
  2011-08-02
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] A transistor-array for parallel BTI-effects measurements2011
- Author(s)
  Takumi Uezono, Tadamichi Kozaki, Hiroyuki Ochi, Takashi Sato
- Organizer
  Workshop on variability modeling and characterization (VMC)
- Place of Presentation
  San Jose, USA
- Year and Date
  2011-11-11
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] A Design Strategy for Sub-Threshold Circuits Considering Energy-Minimization and Yield-Maximization2011
- Author(s)
  Junya Kawashima, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
- Organizer
  IEEE International SOC Conference (SOCC)
- Place of Presentation
  Taipei, Taiwan
- Year and Date
  2011-09-26
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] EM法によるMOSデバイス界面状態数の自動推定2011
- Author(s)
  清水裕史, 筒井弘, 越智裕之, 佐藤高史
- Organizer
  電子情報通信学会ソサイエティ大会
- Place of Presentation
  北海道大学,札幌市
- Year and Date
  2011-09-13
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] ブロック反復法による電源回路網解析の高速化2011
- Author(s)
  森下拓海, 筒井弘, 越智裕之, 佐藤高史
- Organizer
  電子情報通信学会技術研究報告(デザインガイア2011-VLSI設計の新しい大地-)
- Place of Presentation
  ニューウェルシティ宮崎(宮崎県)
- Year and Date
  2011-11-28
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] A Design Strategy for Sub-Threshold Circuits Considering Energy-Minimization and Yield-Maximization2011
- Author(s)
  Junya Kawashima, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato
- Organizer
  IEEE International SOC Conference (SOCC)
- Place of Presentation
  Grand Hotel, Taipei, Taiwan
- Year and Date
  2011-09-26
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] 配線資源の信頼性モデルを用いた粗粒度再構成可能アーキテクチャ向け選択的三重化の最適化手法2011
- Author(s)
  今川隆司, 湯浅洋史, 筒井弘, 越智裕之, 佐藤高史
- Organizer
  情報処理学会DAシンポジウム2011
- Place of Presentation
  ホテル下呂温泉水明館(岐阜県)
- Year and Date
  2011-09-01
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] A fully pipelined implementation of Monte Carlo based SSTA on FPGAs2011
- Author(s)
  Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
- Organizer
  International Symposium on Quality Electrical Design (ISQED)
- Place of Presentation
  Santa Clara, USA
- Year and Date
  2011-03-16
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] A transistor-array for parallel BTI-effects measurements2010
- Author(s)
  Takumi Uezono, Tadamichi Kozaki, Hiroyuki Ochi, and Takashi Sato
- Organizer
  Workshop on Variability Modeling and Characterization (VMC)
- Place of Presentation
  DoubleTreeHotel, San Jose, USA
- Year and Date
  2010-11-11
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] Sequential importance sampling for low-probability and high-dimensional SRAM yield analysis2010
- Author(s)
  Kentaro Katayama, Shiho Hagiwara, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
- Organizer
  ACM/IEEE International Conference on Computer-Aided Design (ICCAD)
- Place of Presentation
  San Jose, USA
- Year and Date
  2010-11-11
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] Path clustering for adaptive test2010
- Author(s)
  Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato
- Organizer
  IEEE VLSI test symposium (VTS)
- Place of Presentation
  Santa Cruz, USA
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] A routing architecture exploration for coarse-grained reconfigurable architecture with an automation of SEU-tolerance evaluation2010
- Author(s)
  Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato
- Organizer
  23rd IEEE International SOC Conference (SOCC)
- Place of Presentation
  Las Vegas, USA
- Year and Date
  2010-09-28
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] Small delay and area overhead process parameter estimation through path-delay inequalities2010
- Author(s)
  Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato
- Organizer
  IEEE International Symposium on Circuits and Systems (ISCAS)
- Place of Presentation
  Paris, France
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] A tool chain for generating SEU-vulnerability map for coarse-grained reconfigurable architecture2010
- Author(s)
  Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato
- Organizer
  The 25th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)
- Place of Presentation
  Bangkok, Thai
- Year and Date
  2010-07-06
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] リングオシレータによるしきい値簡易測定の温度依存性の検討2010
- Author(s)
  上薗巧, 越智裕之, 佐藤高史
- Organizer
  電子情報通信学会 VLSI設計技術研究会(VLD)
- Place of Presentation
  京都府京都工芸繊維大学
- Year and Date
  2010-09-28
- Data Source
  KAKENHI-PROJECT-22360143
[Presentation] プロセッサモードを組み込んだALUベース動的再構成デバイス2008
- Author(s)
  神山真一, 廣本正之, 越智裕之, 中村行宏
- Organizer
  電子情報通信学会VLD・CPSY・RECONF/情報処理学会SLDM合同研究会
- Place of Presentation
  慶應義塾大学日吉キャンパス
- Year and Date
  2008-01-17
- Data Source
  KAKENHI-PROJECT-17300016
[Presentation] 非同期式設計によるFPGA向けIEEE754準拠単精度浮動小数点除算器2008
- Author(s)
  廣本正之, 越智裕之, 中村行宏
- Organizer
  電子情報通信学会技術研究報告 (於屋久島環境文化村センター)
- Place of Presentation
  Vol.107, No.559
- Data Source
  KAKENHI-PROJECT-18500036
[Presentation] プロセッサモードを組み込んだALUベース動的再構成デバイス2008
- Author(s)
  神山真一, 廣本正之, 越智裕之, 中村行宏
- Organizer
  電子情報通信学会VLD・CPSY・RECONF/情報処理学会SLDM 合同研究会
- Place of Presentation
  神奈川県慶應義塾大学
- Year and Date
  2008-01-17
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300016
[Presentation] 非同期単精度浮動小数点除算器の方式検討とFPGA実装2007
- Author(s)
  廣本正之, 神山真一, 越智裕之, 中村行宏
- Organizer
  第30回パルテノン研究会 (於東京都青山オーバルビル15階 Nasic セミナーホール)
- Place of Presentation
  43-48
- Data Source
  KAKENHI-PROJECT-18500036
[Presentation] "An Asynchronous Single- Precision Floating-Point Divider and its Implementation on FPGA", in Proc2007
- Author(s)
  Masayuki Hiromoto, Shin'ichi Kouyama, Hiroyuki Ochi, and Yukihiro Nakamura
- Organizer
  of the 14th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2007)
- Place of Presentation
  Hokkaido, Japan
- Data Source
  KAKENHI-PROJECT-18500036
[Presentation] 非同期単精度浮動小数点除算器の方式検討とFPGA実装2007
- Author(s)
  廣本正之, 高橋温子, 神山真一, 越智裕之, 中村行宏
- Organizer
  電子情報通信学会技術研究報告 (於京都府京大会館)
- Place of Presentation
  Vol.107, No.32
- Data Source
  KAKENHI-PROJECT-18500036
[Presentation] 非同期単精度浮動小数点除算回路のFPGAへの実装検討2006
- Author(s)
  高橋温子, 神山真一, 越智裕之, 中村行宏
- Organizer
  第29回パルテノン研究会 (於東京都青梅市ブリヂストン奥多摩園)
- Place of Presentation
  1-6
- Data Source
  KAKENHI-PROJECT-18500036
[Presentation] Architecture for sealed wafer-scale mask ROM for long-term digital data preservation
- Author(s)
  Shinya Matsuda, Takashi Imagawa, Hiroshi Tsutsui, Takashi Sato, Yukihiro Nakamura, and Hiroyuki Ochi
- Organizer
  28th Intl. Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)
- Place of Presentation
  Yeosu, Korea
- Data Source
  KAKENHI-PROJECT-23300015
[Presentation] 低電圧起動回路を用いた省電力チップ間非接触通信回路
- Author(s)
  佐川善彦, 廣本正之, 佐藤高史, 越智裕之
- Organizer
  第166回システムとLSIの設計技術研究発表会
- Place of Presentation
  北九州国際会議場, 福岡県
- Data Source
  KAKENHI-PROJECT-23300015

1. SATO Takashi (20431992)

# of Collaborated Projects: 2 results

# of Collaborated Products: 55 results
2. TSUTSUI Hiroshi (30402803)

# of Collaborated Projects: 2 results

# of Collaborated Products: 45 results
3. NAKAMURA Yukihiro (60283628)

# of Collaborated Projects: 2 results

# of Collaborated Products: 11 results
4. IZUMI Tomonori (30303887)

# of Collaborated Projects: 1 results

# of Collaborated Products: 5 results
5. 今川隆司 (90771395)

# of Collaborated Projects: 1 results

# of Collaborated Products: 3 results

Ochi Hiroyuki 越智 裕之

OCHI Hiroyuki 越智 裕之

越智 裕之 オチ ヒロユキ

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CMOS-compatible ultra-low-power non-volatile memory and its application to sensor node chipPrincipal Investigator

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Highly efficient voltage booster for embedded on-chip solar cellsPrincipal Investigator

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Architecture for Large-scale Long-term Digital Storage SystemPrincipal Investigator

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Acceleration of Timing Analysis using Monte Carlo Methods

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Development of FPGA Design Methodology Considering Process VariationPrincipal Investigator

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Development of Coarse-Grained Dynamic Self-Reconfigurable Device aiming for Reduction of Reconfiguration Overhead

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RISCプロセッサのデータパスレイアウト優先設計Principal Investigator

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[Journal Article] A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis2013

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[Journal Article] Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element2013

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[Journal Article] A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits2012

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[Journal Article] Bayesian Estimation of Multi-Trap RTN Parameters Using Markov Chain Monte Carlo Method2012

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Ochi Hiroyuki 越智裕之

OCHI Hiroyuki 越智裕之

越智裕之オチヒロユキ