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SAITO Hiroshi  齋藤 寛

ORCIDConnect your ORCID iD *help
Researcher Number 50361671
Other IDs
Affiliation (Current) 2022: 会津大学, コンピュータ理工学部, 上級准教授
Affiliation (based on the past Project Information) *help 2015 – 2021: 会津大学, コンピュータ理工学部, 上級准教授
2007 – 2016: The University of Aizu, コンピュータ理工学部, 准教授
2009 – 2010: 公立大学法人会津大学, コンピュータ理工学部, 准教授
2004 – 2006: 会津大学, コンピュータ理工学部, 講師
Review Section/Research Field
Principal Investigator
Computer system/Network / Basic Section 60040:Computer system-related / Computer system
Except Principal Investigator
Educational technology / Educational technology / Communication/Network engineering
Keywords
Principal Investigator
非同期式回路 / 動作合成 / FPGA / プロセッサ / 畳み込みニューラルネットワーク / 非同期式VLSIシステム / 設計自動化 / 束データ方式 / 低消費エネルギー / 低消費エネルギ … More / マイクロプロセッサ / 低消費電力化 / サイドチャネルアタック / LSI設計技術 … More
Except Principal Investigator
eラーニング / デジタル・ライブラリ / 学習管理システム / 活動理論 / プロジェクト・ベース / e-ラーニング / ブロジェクト・ベース / デジタルストーリーテリング / 学生が製作したビデオ / 工業英語 / アクティブ・ラーニング / メディアの活用 / MOOC / 高速シリアル通信 / 細粒度パワーゲーティング / 4値レベル信号 / PLL/DLLレス / 同期/非同期インタフェース / 同期/非同期インタフェース / 通信方式 / シリアル通信 / 低消費電力化 / クロック埋め込み Less
  • Research Projects

    (10 results)
  • Research Products

    (36 results)
  • Co-Researchers

    (9 People)
  •  非同期式回路による省エネルギーなエッジAIデバイスの実現Principal Investigator

    • Principal Investigator
      齋藤 寛
    • Project Period (FY)
      2021 – 2023
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Review Section
      Basic Section 60040:Computer system-related
    • Research Institution
      The University of Aizu
  •  FPGA implementation of low energy asynchronous convolutional neural network circuitsPrincipal Investigator

    • Principal Investigator
      Saito Hiroshi
    • Project Period (FY)
      2018 – 2020
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Review Section
      Basic Section 60040:Computer system-related
    • Research Institution
      The University of Aizu
  •  Evaluation of Tamper Resistance for Asynchronous Circuits with Bundled-data Implementation Using Programmable Delay ElementPrincipal Investigator

    • Principal Investigator
      Saito Hiroshi
    • Project Period (FY)
      2015 – 2018
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Research Field
      Computer system
    • Research Institution
      The University of Aizu
  •  Study on Implementation for Greatly Reducing Power Dissipation of Serial Communication Mechanisms

    • Principal Investigator
      YONEDA Tomohiro
    • Project Period (FY)
      2015 – 2017
    • Research Category
      Grant-in-Aid for Scientific Research (A)
    • Research Field
      Communication/Network engineering
    • Research Institution
      National Institute of Informatics
  •  Digital Storytelling for Computer Science Team Project Documentaries

    • Principal Investigator
      Brine John
    • Project Period (FY)
      2014 – 2016
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Research Field
      Educational technology
    • Research Institution
      The University of Aizu
  •  Transformation from Synchronous Circuits to Low Power Asynchronous CircuitsPrincipal Investigator

    • Principal Investigator
      SAITO Hiroshi
    • Project Period (FY)
      2012 – 2014
    • Research Category
      Grant-in-Aid for Young Scientists (B)
    • Research Field
      Computer system/Network
    • Research Institution
      The University of Aizu
  •  Energy Optimization for Asynchronous Circuits using Freedom of Execution SpeedPrincipal Investigator

    • Principal Investigator
      SAITO Hiroshi
    • Project Period (FY)
      2009 – 2011
    • Research Category
      Grant-in-Aid for Young Scientists (B)
    • Research Field
      Computer system/Network
    • Research Institution
      The University of Aizu
  •  Globalizing Technical English Curriculum Design : Using Collaborative eLearning Tools

    • Principal Investigator
      JOHN Brine
    • Project Period (FY)
      2008 – 2010
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Research Field
      Educational technology
    • Research Institution
      The University of Aizu
  •  非同期式回路を対象とした動作合成・最適化手法に関する研究Principal Investigator

    • Principal Investigator
      SAITO Hiroshi
    • Project Period (FY)
      2006 – 2008
    • Research Category
      Grant-in-Aid for Young Scientists (B)
    • Research Field
      Computer system/Network
    • Research Institution
      The University of Aizu
  •  C言語による仕様記述からの非同期式VLSIシステム論理設計自動化に関する研究Principal Investigator

    • Principal Investigator
      齋藤 寛
    • Project Period (FY)
      2004 – 2005
    • Research Category
      Grant-in-Aid for Young Scientists (B)
    • Research Field
      Computer system/Network
    • Research Institution
      The University of Aizu

All 2021 2020 2019 2018 2016 2015 2013 2011 2009 2008 2007 2006 2004 Other

All Journal Article Presentation

  • [Journal Article] Optimization Methods during RTL Conversion from Synchronous RTL Models to Asynchronous RTL Models2020

    • Author(s)
      SEMBA Shogo、SAITO Hiroshi、TATSUOKA Masato、FUJIMURA Katsuya
    • Journal Title

      IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

      Volume: E103.A Issue: 12 Pages: 1417-1426

    • DOI

      10.1587/transfun.2020vlp0004

      10.1587/transfun.2020VLP0004

    • NAID

      130007948308

    • ISSN
      0916-8508, 1745-1337
    • Language
      English
    • Peer Reviewed / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-20J11724, KAKENHI-PROJECT-18K11221
  • [Journal Article] A Design Method for Designing Asynchronous Circuits on Commercial FPGAs Using Placement Constraints2020

    • Author(s)
      OTAKE Tatsuki、SAITO Hiroshi
    • Journal Title

      IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

      Volume: E103.A Issue: 12 Pages: 1427-1436

    • DOI

      10.1587/transfun.2020vlp0006

      10.1587/transfun.2020VLP0006

    • NAID

      130007948286

    • ISSN
      0916-8508, 1745-1337
    • Language
      English
    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18K11221
  • [Journal Article] Conversion from Synchronous RTL Models to Asynchronous RTL Models2019

    • Author(s)
      S. Semba and H. Saito
    • Journal Title

      IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

      Volume: E102-A, Issue 7 Issue: 7 Pages: 904-913

    • DOI

      10.1587/transfun.e102.a.904

      10.1587/transfun.E102.A.904

    • NAID

      130007670864

    • ISSN
      0916-8508, 1745-1337
    • Language
      English
    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18K11221
  • [Journal Article] Conversion from Synchronous RTL Models to Asynchronous RTL Models2019

    • Author(s)
      Shogo Semba and Hiroshi Saito
    • Journal Title

      IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences

      Volume: E102-A, No. 7

    • NAID

      130007670864

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-15K00080
  • [Journal Article] Design of an Asynchronous Processor with Bundled-data Implementation on a Commercial Field Programmable Gate Array2016

    • Author(s)
      J. Furushima, M. Nakajima, and H. Saito
    • Journal Title

      Informatica, An International Journal of Computing and Informatics

      Volume: 40 Pages: 399-408

    • Peer Reviewed / Acknowledgement Compliant / Open Access
    • Data Source
      KAKENHI-PROJECT-15K00080
  • [Journal Article] An ASIC Design Support Tool Set for Non-pipelined Asynchronous Circuits with Bundled-Data Implementation2013

    • Author(s)
      Minoru Iizuka, Naohiro Hamada, and Hiroshi Saito
    • Journal Title

      IEICE TRANSACTIONS on Electronics

      Volume: Vol.E96-C Pages: 482-491

    • NAID

      10031182824

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-24700051
  • [Journal Article] A Behavioral Synthesis System for Asynchronous Circuitsowith Bundled-data Implementation2009

    • Author(s)
      Naohiro Hamada, Yuuki Shiga, Takao Konishi, Hiroshi Saito, Tomohiro Yoneda, Chris Myers, Takashi Nanya
    • Journal Title

      IPSJ Transaction on System LSI Design Methodology 2

      Pages: 64-79

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18700047
  • [Journal Article] A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation2009

    • Author(s)
      Naohiro Hamada, Yuuki Shiga,Takao Konishi, Hiroshi Saito, Tomohiro Yoneda, Chris Myers, Takashi Nanya,
    • Journal Title

      IPSJ Transaction on System LSI Design Methodology vol.2

      Pages: 64-79

    • NAID

      110006452844

    • Data Source
      KAKENHI-PROJECT-18700047
  • [Journal Article] Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times2007

    • Author(s)
      Hiroshi Saito, Naohiro Hamada, Tomohiro Yoneda, Chris Myers, Takashi Nanya
    • Journal Title

      IEICE Transaction vol.E90-A

    • NAID

      110007538025

    • Data Source
      KAKENHI-PROJECT-18700047
  • [Journal Article] Scheduling Methods for Asynchronous Circuits with Bundled-Data Imple mentations Based on the Approximation of Start Times2007

    • Author(s)
      H.Saito, N.Hamada, N.Jindapetch, T.Yoneda, C.Myers, T.Nanya
    • Journal Title

      IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E90-A

      Pages: 2790-2799

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18700047
  • [Journal Article] Logic Optimization of Asynchronous Speed-Independent Circuits Using Transduction Methods2004

    • Author(s)
      齋藤寛, 中村宏, 藤田昌宏, 南谷崇
    • Journal Title

      情報処理学会論文誌 45巻・5号

      Pages: 1289-1299

    • Data Source
      KAKENHI-PROJECT-16700050
  • [Presentation] Study on an RTL Conversion Method from Pipelined Synchronous RTL Models into Asynchronous RTL Models2021

    • Author(s)
      SEMBA Shogo、SAITO Hiroshi
    • Organizer
      The 23rd Workshop on Synthesis And System Integration of Mixed Information technologies
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18K11221
  • [Presentation] Comparison of RTL Conversion and GL Conversion from Synchronous Circuits to Asynchronous Circuits2019

    • Author(s)
      Shogo Semba and Hiroshi Saito
    • Organizer
      International Symposium on Circuits and Systems
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-15K00080
  • [Presentation] Design of Asynchronous Circuits on Commercial FPGAs Using Placement Constraints2019

    • Author(s)
      T. Otake and H. Saito
    • Organizer
      Workshop on Synthesis And System Integration of Mixed Information technologies
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18K11221
  • [Presentation] Design of Asynchronous CNN Circuits on Commercial FPGA from Synchronous CNN Circuits2019

    • Author(s)
      H. Kato and H. Saito
    • Organizer
      IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18K11221
  • [Presentation] Comparison of RTL Conversion and GL Conversion from Synchronous Circuits to Asynchronous Circuits2019

    • Author(s)
      S. Semba and H. Saito
    • Organizer
      IEEE International Symposium on Circuits and Systems
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18K11221
  • [Presentation] A Study on the Optimization of Asynchronous Circuits During RTL Conversion from Synchronous Circuits2019

    • Author(s)
      S. Semba and H. Saito
    • Organizer
      Workshop on Synthesis And System Integration of Mixed Information technologies
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18K11221
  • [Presentation] Performance Optimization by Placement Constraints for FPGA-based Asynchronous Processors2018

    • Author(s)
      J. Furushima, T. Otake, and H. Saito
    • Organizer
      SASIMI 2018
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-15K00080
  • [Presentation] Comparison of Pipelined Asynchronous Circuits Designed for FPGA2018

    • Author(s)
      Takuya Kudo and Hiroshi Saito
    • Organizer
      3rd International Conference on Applications in Information Technology
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18K11221
  • [Presentation] A Delay Adjustment Method for Asynchronous Circuits with Bundled ‐ data Implementation Considering a Latency Constraint2016

    • Author(s)
      K. Yoshimi and H. Saito
    • Organizer
      Workshop on Synthesis And System Integration of Mixed Information Technologies
    • Place of Presentation
      Kyoto Research Park
    • Year and Date
      2016-10-25
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-15K00080
  • [Presentation] Design of an Asynchronous Inverse Discrete Cosine Transform Circuit on an FPGA2016

    • Author(s)
      T. Urakawa and H. Saito
    • Organizer
      International Conference on Applications in Information Technology
    • Place of Presentation
      University of Aizu
    • Year and Date
      2016-10-07
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-15K00080
  • [Presentation] FPGA based Design of a Low Power Asynchronous MIPS Processor2016

    • Author(s)
      J. Furushima and H. Saito
    • Organizer
      International Conference on Applications in Information Technology
    • Place of Presentation
      University of Aizu
    • Year and Date
      2016-10-07
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-15K00080
  • [Presentation] Constraining Operation Delay for Dynamic Power Optimization of Asynchronous Circuits2015

    • Author(s)
      Shunya Hosaka, Hiroshi Saito
    • Organizer
      International Workshop on Applications in Information Technology (IWAIT-2015)
    • Place of Presentation
      Aizu-Wakamatsu, Japan
    • Year and Date
      2015-10-08
    • Data Source
      KAKENHI-PROJECT-15K00080
  • [Presentation] 束データ方式による非同期式回路のFPGA設計支援環境の構築2015

    • Author(s)
      滝澤恵多郎、齋藤寛
    • Organizer
      情報処理学会SLDM研究会
    • Place of Presentation
      北九州
    • Year and Date
      2015-05-14
    • Data Source
      KAKENHI-PROJECT-24700051
  • [Presentation] サイクルタイム制約を考慮した低消費電力な束データ方式による非同期式AVRプロセッサの設計2013

    • Author(s)
      岩崎翔太郎、齋藤寛
    • Organizer
      情報処理学会研究報告システムLSI設計技術(SLDM)
    • Place of Presentation
      鹿児島
    • Data Source
      KAKENHI-PROJECT-24700051
  • [Presentation] FPGAを対象とした束データ方式による非同期式回路の設計支援ツールセット2013

    • Author(s)
      滝澤恵多郎、齋藤寛
    • Organizer
      情報処理学会研究報告システムLSI設計技術(SLDM)
    • Place of Presentation
      鹿児島
    • Data Source
      KAKENHI-PROJECT-24700051
  • [Presentation] 非同期式AVRプロセッサの設計2011

    • Author(s)
      熊谷、飯塚、松浦、齋藤
    • Organizer
      第24回回路とシステムワークショップ
    • Data Source
      KAKENHI-PROJECT-21700062
  • [Presentation] A Behavioral Synthesis System forAsynchronous Circuits with Bundled-data Implementation (tool paper)2008

    • Author(s)
      Naohiro Hamada, Yuuki Shiga, Hiroshi Saito, Tomohiro Yeneda, Chris Myers, Takashi Nanya
    • Organizer
      8th International Conference on Application of Concurrency to System Design
    • Data Source
      KAKENHI-PROJECT-18700047
  • [Presentation] A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation (tool paper)2008

    • Author(s)
      Naohiro Hamada, Yuuki Shiga, Hiroshi Saito, Tomohiro Yoneda, Chris Myers, Takashi Nanya
    • Organizer
      8^<th> International Conference on Application of Concurrency to System Design
    • Place of Presentation
      中国西安市
    • Data Source
      KAKENHI-PROJECT-18700047
  • [Presentation] A Control Circuit Synthesis Methodfor Asynchronous Circuits in Bundled-Data Implementation2007

    • Author(s)
      Takao Konishi, Naohiro Hamada, Hiroshi Saito
    • Organizer
      International Conference on Compute and Information Technology
    • Data Source
      KAKENHI-PROJECT-18700047
  • [Presentation] A Control Circuit Synthesis Method for Asynchronous Circuits in Bundled-Data Implementation2007

    • Author(s)
      T.Konishi, N.Hamada, H.Saito
    • Organizer
      7th IEEE International Conference on Computer and Information Tcchnology
    • Place of Presentation
      University of Aizu,Japan
    • Data Source
      KAKENHI-PROJECT-18700047
  • [Presentation] ILP-Based Scheduling for Asynchonous Circuits in Bundled-Data Implementation2006

    • Author(s)
      Hiroshi Saito, Nattha Jindapetc, Tomohiro Yoneda, Cris Myers, Takashi Nanya
    • Organizer
      International Conference on Compute and Information Technology
    • Data Source
      KAKENHI-PROJECT-18700047
  • [Presentation] A design support tool set for asynchronous circuits with bundled-data implementation on FPGAs

    • Author(s)
      K. Takizawa, S. Hosaka, H. Saito
    • Organizer
      24th International Conference on Field Programmable Logic and Applications
    • Place of Presentation
      Munich, Germany
    • Year and Date
      2014-09-02 – 2014-09-04
    • Data Source
      KAKENHI-PROJECT-24700051
  • [Presentation] 高位合成ツールからの非同期式回路生成に関する研究

    • Author(s)
      小峰太一、齋藤寛
    • Organizer
      電子情報通信学会VLD研究会
    • Place of Presentation
      那覇
    • Year and Date
      2015-03-02 – 2015-03-04
    • Data Source
      KAKENHI-PROJECT-24700051
  • [Presentation] SystemCモデルから束データ方式による非同期式回路を合成する合成フローの提案

    • Author(s)
      小峰太一、齋藤寛
    • Organizer
      電子情報通信学会VLD研究会
    • Place of Presentation
      北九州
    • Year and Date
      2014-05-28 – 2014-05-29
    • Data Source
      KAKENHI-PROJECT-24700051
  • [Presentation] 演算の移動度を利用した束データ方式による非同期式回路の電力最適化手法の検討

    • Author(s)
      保坂隼也、齋藤寛
    • Organizer
      電子情報通信学会VLD研究会
    • Place of Presentation
      別府
    • Year and Date
      2014-11-26 – 2014-11-28
    • Data Source
      KAKENHI-PROJECT-24700051
  • 1.  JOHN Brine (60247624)
    # of Collaborated Projects: 2 results
    # of Collaborated Products: 0 results
  • 2.  Debopriyo ROY (30453020)
    # of Collaborated Projects: 2 results
    # of Collaborated Products: 0 results
  • 3.  Vazhenin A・P (10325970)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 4.  金子 恵美子 (30533624)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 5.  YONEDA Tomohiro (30182851)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 6.  羽生 貴弘 (40192702)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 7.  今井 雅 (70323665)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 8.  吉瀬 謙二 (50323887)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 9.  富岡 洋一 (10574072)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results

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