WATANABE TAKAHIRO 渡邊孝博

… Alternative Names

Researcher Number	70230969
Other IDs
External Links
Affiliation (based on the past Project Information) *help	2018 – 2020: 早稲田大学, 理工学術院(情報生産システム研究科・センター), 教授 2011 – 2013: 早稲田大学, 理工学術院, 教授 1998 – 1999: 山口大学, 工学部, 助教授 1995 – 1996: 山口大学, 工学部, 助教授
Review Section/Research Field	Principal Investigator Computer system/Network / 電子デバイス・機器工学 / Basic Section 60040:Computer system-related Except Principal Investigator 情報通信工学
Keywords	Principal Investigator NoC / ルーティング / LSI / CAD / MCM / ＳｏＣ / ＩＰ / アーキテクチャ / 低電力 / ＰＣＢ … More Except Principal Investigator CDMA / FPGA / スペクトル拡散通信 / シフト直交実数有限長系列 / 局間干渉 / 符号間干渉 / 高速相関 / ディジタル信号処理 / 高速相閲 / Spread spectrum communication / Orthogonal finite-length sequence / Interchannel interference / Intersymbol interference / Fast correlation / Digital signal processing Less

Research on NoC system robust to fluctuation of traffic patternsPrincipal Investigator
- Principal Investigator
  
  WATANABE TAKAHIRO
- Project Period (FY)
  2018 – 2020
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Waseda University
A Study of a Tile-based NoC System using IPs and its DesignPrincipal Investigator
- Principal Investigator
  
  WATANABE TAKAHIRO
- Project Period (FY)
  2011 – 2013
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system/Network
- Research Institution
  Waseda University
Research on Digitalized Spread Spectrum Communication System Using Real-Valued Sequences
- Principal Investigator
  
  TADANO Yoshihiro
- Project Period (FY)
  1998 – 1999
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  情報通信工学
- Research Institution
  Yamaguchi University
Computer-Aided-Design for Analog-Digital Mixed Large Scaled Integration CircuitsPrincipal Investigator
- Principal Investigator
  
  WATANABE Takahiro
- Project Period (FY)
  1995 – 1996
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  電子デバイス・機器工学
- Research Institution
  Yamaguchi University

All 2020 2019 2014 2013 2012 2011 Other

All Journal Article Presentation

[Journal Article] A Hotspot-Pattern-Aware Routing Algorithm for Networks-on-Chip2019
- Author(s)
  Y. Luo, M. C. Meyer, X. Jiang and T. Watanabe
- Journal Title
  
  2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)
  
  Volume: 2019 Pages: 229-235
- DOI
  10.1109/mcsoc.2019.00040
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18K11226
[Journal Article] Fault-Tolerant Traffic-Aware Routing Algorithm for 3-D Photonic Networks-on-Chip2019
- Author(s)
  M. C. Meyer, Y. Wang and T. Watanabe
- Journal Title
  
  2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)
  
  Volume: 2019 Pages: 172-179
- DOI
  10.1109/mcsoc.2019.00032
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18K11226
[Journal Article] Low-Cost Congestion Detection Mechanism for Networks-on-Chip2019
- Author(s)
  Z. Han, M. C. Meyer, X. Jiang and T. Watanabe
- Journal Title
  
  2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)
  
  Volume: 2019 Pages: 157-163
- DOI
  10.1109/mcsoc.2019.00030
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18K11226
[Journal Article] A Traffic-Robust Routing Algorithm for Network-on-Chip Systems.2019
- Author(s)
  S. Xu, M. C. Meyer, X. Jiang and T. Watanabe
- Journal Title
  
  2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)
  
  Volume: 2019 Pages: 209-216
- DOI
  10.1109/mcsoc.2019.00037
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18K11226
[Journal Article] A Sophisticated Routing Algorithm in 3D NoC with Fixed TSVs for Low Energy and Latency2014
- Author(s)
  Xin Jiang, Lian Zeng,Takahiro Watanabe
- Journal Title
  
  IPSJ Trans.SLDM
  
  Volume: 13 Pages: 1-9
- NAID
  130004705275
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23500069
[Journal Article] LVSの出力情報を活用したVLSI電源配線幅の高速検証システム2013
- Author(s)
  亀井智紀　渡邊孝博　川北真裕
- Journal Title
  
  電子情報通信学会　論文誌Ｄ
  
  Volume: J96-D Pages: 1330-1337
- NAID
  110009603597
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23500069
[Journal Article] LVSの出力情報を活用した VLSI 電源配線幅の高速検証システム2013
- Author(s)
  亀井智紀, 渡邊孝博, 川北真裕
- Journal Title
  
  電子情報通信学会論文誌D
  
  Volume: Vol.J96-D, No.5 Pages: 1330-1337
- NAID
  110009603597
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23500069
[Journal Article] An Efficient Algorithm for 3D NoC Architecture Optimization2013
- Author(s)
  Xin Jiang, Ran Zhang and Takahiro Watanabe
- Journal Title
  
  IPSJ Trans. System LSI Design Methodology (情報処理学会)
  
  Volume: 6 Pages: 34-41
- NAID
  130003369388
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23500069
[Journal Article] An Efficient Algorithm for 3D NoC Architecture Optimization2013
- Author(s)
  Xin Jiang, Ran Zhang, Takahiro Watanabe
- Journal Title
  
  IPSJ Trans. System LSI Design Methodology
  
  Volume: 6 Pages: 34-41
- NAID
  130003369388
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23500069
[Journal Article] Region-oriented Placement Algorithm for Coarse-grained Power-gating FPGA Architecture2012
- Author(s)
  C.Li, Y.Dong and T.Watanabe
- Journal Title
  
  IEICE Trans Information and Systems
  
  Volume: E95-D, 2 Pages: 314-323
- NAID
  10030610510
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23500069
[Journal Article] Region-Oriented Placement Algorithm for Coarse-Grained Power-Gating FPGA Architecture2012
- Author(s)
  C.Li, Y.Dong and T.Watanabe
- Journal Title
  
  IEICE Transactions on Information and Systems
  
  Volume: E９５－D、2 Issue: 2 Pages: 314-323
- DOI
  10.1587/transinf.e95.d.314
  10.1587/transinf.E95.D.314
- NAID
  10030610510
- ISSN
  0916-8532, 1745-1361
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23500069
[Journal Article] Region Oriented Routing FPGA Architecture for Dynamic Power Gating2012
- Author(s)
  Ce Li, Yiping Dong, Takahiro Watanabe
- Journal Title
  
  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
  
  Volume: E95-A/12 Issue: 12 Pages: 2199-2207
- DOI
  10.1587/transfun.e95.a.2199
  10.1587/transfun.E95.A.2199
- NAID
  10031161353
- ISSN
  0916-8508, 1745-1337
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23500069
[Journal Article] A Hybrid Layer- Multiplexing and Pipeline Architecture for Efficient FPGA-based Multilayer Neural Network2011
- Author(s)
  Y.P.Dong, C.Li, Z.Lin and Takahiro Watanabe
- Journal Title
  
  IEICE NOLTA
  
  Volume: E94-N, 10 Pages: 522-532
- NAID
  130001225021
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23500069
[Journal Article] A New Recovery Mechanism in Superscalar Microprocessors by Recovering Critical Misprediction2011
- Author(s)
  Jiongyao Ye, Yu Wan and Takahiro Watanabe
- Journal Title
  
  IEICE Trans. Fundamentals of Electoronics, Communications and Computer Sciences
  
  Volume: E94-A, 12 Pages: 2639-2648
- NAID
  10030533810
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23500069
[Journal Article] A Hybrid Layer-Multiplexing and Pipeline Architecture for Efficient FPGA-based Multilayer Neural Network2011
- Author(s)
  Y.P.Dong, C.Li, Z.Lin and Takahiro Watanabe
- Journal Title
  
  IEICE　NOLTA
  
  Volume: E94-N、10 Pages: 522-532
- NAID
  130001225021
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23500069
[Journal Article] Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture2011
- Author(s)
  C. Li, Y.P.Dong and T.Watanabe
- Journal Title
  
  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
  
  Volume: E94-A、12 Issue: 12 Pages: 2519-2527
- DOI
  10.1587/transfun.e94.a.2519
  10.1587/transfun.E94.A.2519
- NAID
  10030533568
- ISSN
  0916-8508, 1745-1337
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23500069
[Journal Article] Analysis Before Starting an Access : A New Power-Efficient Instruction Fetch Mechanism2011
- Author(s)
  Jiongyao Ye, Yingtao Hu, Takahiro Watanabe
- Journal Title
  
  IEICE
  
  Volume: E94-D 7 Pages: 1398-1408
- NAID
  10029805481
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23500069
[Journal Article] Analysis before Starting an Access: A New Power-Efficient Instruction Fetch Mechanism2011
- Author(s)
  Jiongyao Ye, Yingtao Hu, Hongfeng Ding and Takahiro Watanabe
- Journal Title
  
  IEICE Transactions on Information and Systems
  
  Volume: E94-D, 7 Issue: 7 Pages: 1398-1408
- DOI
  10.1587/transinf.e94.d.1398
  10.1587/transinf.E94.D.1398
- NAID
  10029805481
- ISSN
  0916-8532, 1745-1361
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23500069
[Journal Article] An Adaptive Various-width Data Cache for Low Power Design2011
- Author(s)
  Jiongyao Ye, Yu Wan, Takahiro Watanabe
- Journal Title
  
  IEICE
  
  Volume: E94-D Pages: 1539-1546
- NAID
  10030192385
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23500069
[Journal Article] A New Recovery Mechanism in Superscalar Microprocessors by Recovering Critical Misprediction2011
- Author(s)
  Jiongyao Ye, Yu Wan and Takahiro Watanabe
- Journal Title
  
  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
  
  Volume: E94-A、12 Issue: 12 Pages: 2639-2648
- DOI
  10.1587/transfun.e94.a.2639
  10.1587/transfun.E94.A.2639
- NAID
  10030533810
- ISSN
  0916-8508, 1745-1337
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23500069
[Journal Article] An Adaptive Various-Width Data Cache for Low Power Design2011
- Author(s)
  Jiongyao Ye, Yu Wan and Takahiro Watanabe
- Journal Title
  
  IEICE Transactions on Information and Systems
  
  Volume: E94-D、8 Issue: 8 Pages: 1539-1546
- DOI
  10.1587/transinf.e94.d.1539
  10.1587/transinf.E94.D.1539
- NAID
  10030192385
- ISSN
  0916-8532, 1745-1361
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23500069
[Journal Article] Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture
- Author(s)
  C. Li, Y.P.Dong and T.Watanabe
- Journal Title
  
  IEICE Trans. Fundamentals of Electronics Communications and Computer Sciences
  
  Volume: E94-A, 12 Pages: 2519-2527
- NAID
  10030533568
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23500069
[Journal Article] A Sophisticated Routing Algorithm in 3D NoC with Fixed TSVs for Low Energy and Latency
- Author(s)
  Xin Jiang, Lian Zeng, Takahiro Watanabe
- Journal Title
  
  IPSJ Trans.SLDM
  
  Volume: vol.13 (to appear)
- NAID
  130004705275
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23500069
[Journal Article] Region Oriented Routing FPGA Architecture for Dynamic Power Gating
- Author(s)
  Ce Li , Yiping Dong and Takahiro Watanabe
- Journal Title
  
  IEICE Trans.Fudamentals
  
  Volume: vol.E95-A 12 Pages: 2199-2207
- NAID
  10031161353
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-23500069
[Presentation] A Fault-Tolerant Hamiltonian-Based Odd-Even Routing Algorithm for Network-on-Chip2020
- Author(s)
  Cheng Hu, Michael Conrad Meyer, Xin Jiang, Takahiro Watanabe
- Organizer
  ITC-CSCC 2020
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11226
[Presentation] Multiple Factors Congestion Prediction Algorithm for Network-on-Chip2020
- Author(s)
  Zhenyu Hu, Michael Conrad Meyer, Xin Jiang, Takahiro Watanabe
- Organizer
  ITC-CSCC 2020
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11226
[Presentation] Efficient Delay-matching Bus Routing by using Multi-layers2014
- Author(s)
  Yang Tian, Ran Zhang, Takahiro Watanabe
- Organizer
  Int. Conf. on Electronics Packaging
- Place of Presentation
  Toyama
- Data Source
  KAKENHI-PROJECT-23500069
[Presentation] Flexible L1 Cache Optimization for a Low Power Embedded System2013
- Author(s)
  Huatao ZHAO, Jiongyao YE, Takahiro WATANABE
- Organizer
  情報処理学会第5回全国大会
- Place of Presentation
  仙台
- Data Source
  KAKENHI-PROJECT-23500069
[Presentation] Pseudo Dual Path Processing to Reduce the Branch Misprediction Penalty in Embedded Processors2013
- Author(s)
  Huatao ZHAO, Jiongyao YE, Yuxin Sun, Takahiro WATANABE
- Organizer
  The 10th Int. Conf. on ASIC
- Place of Presentation
  Shenzhen
- Data Source
  KAKENHI-PROJECT-23500069
[Presentation] Flexible L1 Cache Optimization for a Low Power Embedded System2013
- Author(s)
  Huatao ZHAO, Sijie YIN, Yuxin Sun, Takahiro WATANABE
- Organizer
  2013 Int .Conf. Mechatronic Sciences, Electric Engineering and Computer
- Place of Presentation
  Niiata
- Data Source
  KAKENHI-PROJECT-23500069
[Presentation] Adaptive Router with Predictor using Congestion Degree for 3D Network-on-Chip2013
- Author(s)
  Lian Zeng, Xin Jiang, Takahiro Watanabe
- Organizer
  Proc. 2013 Int. Soc Design Conf. (ISOCC)
- Place of Presentation
  Busan
- Data Source
  KAKENHI-PROJECT-23500069
[Presentation] A Parallel Routing Method for Fixed Pins using Virtual Boundary2013
- Author(s)
  Ran Zhang, Takahiro Watanabe
- Organizer
  Proc. IEEE 2013 TENCON-Spring
- Place of Presentation
  Sydney
- Data Source
  KAKENHI-PROJECT-23500069
[Presentation] A Sorting-Based IO Connection Assignment for Flip-Chip Designs2013
- Author(s)
  Ran Zhang, Xue Wei, Takahiro Watanabe
- Organizer
  the 10th Int. Conf. ASIC (ASICON 2013)
- Place of Presentation
  Shenzhen
- Data Source
  KAKENHI-PROJECT-23500069
[Presentation] A Parallel Routing Method for Fixed Pins using Virtual Boundary2013
- Author(s)
  Zhang Ran and Takahiro Watanabe
- Organizer
  TENCON Spring 2013
- Place of Presentation
  Sydney
- Data Source
  KAKENHI-PROJECT-23500069
[Presentation] Rotational Display Problem for Array Reference　in LSI Layout Data2012
- Author(s)
  Tomoki Kamei, Takahiro Watanabe
- Organizer
  ITC-CSCC 2012
- Place of Presentation
  Sapporo
- Data Source
  KAKENHI-PROJECT-23500069
[Presentation] A High Performance Digital Neural Processor Design by Network on Chip Architecture2011
- Author(s)
  Y.Dong, Y.Li and Takahiro Watanabe
- Organizer
  Proc. VLSI-DAT'11
- Place of Presentation
  Hsinchu
- Data Source
  KAKENHI-PROJECT-23500069
[Presentation] A High Performance Digital Neural Processor Design by Network on Chip Architecture2011
- Author(s)
  Y.Dong, Y.Li and Takahiro Watanabe
- Organizer
  VLSI-DAT'11
- Place of Presentation
  Hsinchu, Taiwan
- Data Source
  KAKENHI-PROJECT-23500069
[Presentation] New Power Efficient FPGA Design Combining with Region-Constrained Placement and Multiple Power Domains2011
- Author(s)
  C. Li, Y.P. Dong, Takahiro Watanabe
- Organizer
  Proc.IEEE NEWCAS'11 (IEEE 9th Int. Conf. New Circuits and Systems)
- Place of Presentation
  Paris
- Data Source
  KAKENHI-PROJECT-23500069
[Presentation] New Power-aware Placement for Region based FPGA Architecture combined with Dynamic Power Gating by PCHM2011
- Author(s)
  C.Li, Y.P.Dong and T. Watanabe
- Organizer
  Proc.ISLPED'11 (Int'l Symp. Low Power Electronics Design)
- Place of Presentation
  Fukuoka
- Data Source
  KAKENHI-PROJECT-23500069
[Presentation] An Efficient Design Algorithm for Exploring Flexible Topologies in Custom Adaptive 3D NoCs for High Performance and Low Power2011
- Author(s)
  Xin Jiang, Ran Zhang and Takahiro Watanabe
- Organizer
  Proc. 2011 IEEE 9th Int.Conf.on ASIC (ASICON 2011)
- Place of Presentation
  Beijin
- Data Source
  KAKENHI-PROJECT-23500069
[Presentation] New Power Efficient FPGA Design Combining with Region-Constrained Placement and Multiple Power Domains2011
- Author(s)
  C. Li, Y.P. Dong and Takahiro Watanabe
- Organizer
  IEEE　NEWCAS’１１　(IEEE 9th Int'l Conf. New Circuitｓ and Systems)
- Place of Presentation
  Bordeaux, France
- Data Source
  KAKENHI-PROJECT-23500069
[Presentation] New Power-aware Placement for Region based FPGA Architecture combined with Dynamic Power Gating by PCHM2011
- Author(s)
  C.Li, Y.P.Dong and T. Watanabe
- Organizer
  ISLPED'11 (Int'l Symp. Low Power Electronics Design)
- Place of Presentation
  Fukuoka, Japan
- Data Source
  KAKENHI-PROJECT-23500069
[Presentation] Flexible L1 Cache Optimization for a Low Power Embedded System
- Author(s)
  Huatao ZHAO, Sijie YIN, Yuxin Sun, Takahiro WATANABE
- Organizer
  2013 International Conference on Mechatronic Sciences, Electric Engineering and Computer
- Place of Presentation
  Harbin, China
- Data Source
  KAKENHI-PROJECT-23500069
[Presentation] A Sorting-Based IO Connection Assignment for Flip-Chip Designs
- Author(s)
  Ran Zhang, Xue Wei, Takahiro Watanabe
- Organizer
  the 10th International Conference on ASIC (ASICON 2013)
- Place of Presentation
  Shenzhen, China
- Data Source
  KAKENHI-PROJECT-23500069
[Presentation] Efficient Delay-matching Bus Routing by using Multi-layers
- Author(s)
  Yang Tian, Ran Zhang, Takahiro Watanabe
- Organizer
  Int.Conf.on Electronics Packaging (ICEP 2014)
- Place of Presentation
  Toyama
- Data Source
  KAKENHI-PROJECT-23500069
[Presentation] Adaptive Router with Predictor using Congestion Degree
- Author(s)
  Lian Zeng, Takahiro Watanabe
- Organizer
  電子情報通信学会 2013ソサイエティ大会
- Place of Presentation
  Fukuoka
- Data Source
  KAKENHI-PROJECT-23500069
[Presentation] A Parallel Routing Method for Fixed Pins using Virtual Boundary
- Author(s)
  Ran Zhang, Takahiro Watanabe
- Organizer
  IEEE 2013 TENCON-Spring
- Place of Presentation
  Sydney, Australia
- Data Source
  KAKENHI-PROJECT-23500069
[Presentation] A Stack-based Solution for Alias Problem in Branch Prediction
- Author(s)
  殷思杰，カドウチョ，渡邊孝博
- Organizer
  第76回情報処理学会全国大会
- Place of Presentation
  Tokyo
- Data Source
  KAKENHI-PROJECT-23500069
[Presentation] Adaptive routing with congestion estimation based on G-table
- Author(s)
  Zheng Gong，Lian Zeng，Takahiro Watanabe
- Organizer
  電子情報通信学会 2014総合大会
- Place of Presentation
  Niigata
- Data Source
  KAKENHI-PROJECT-23500069
[Presentation] Pseudo Dual Path Processing to Reduce the Branch Misprediction Penalty in Embedded Processors
- Author(s)
  Huatao ZHAO, Jiongyao YE, Yuxin Sun, Takahiro WATANABE
- Organizer
  10th International Conference on ASIC
- Place of Presentation
  Shenzhen, China
- Data Source
  KAKENHI-PROJECT-23500069
[Presentation] Adaptive Router with Predictor using Congestion Degree for 3D Network-on-Chip
- Author(s)
  Lian Zeng, Xin Jiang, Takahiro Watanabe
- Organizer
  2013 International Soc Design Conference (ISOCC)
- Place of Presentation
  Busan, Korea
- Data Source
  KAKENHI-PROJECT-23500069
[Presentation] Efficient Length-matching Bus Routing by using Multi-layers
- Author(s)
  Yang TIAN, Ran ZHANG, Takahiro WATANABE
- Organizer
  電気関係学会九州支部連合大会2013
- Place of Presentation
  Kumamoto
- Data Source
  KAKENHI-PROJECT-23500069

1. TADANO Yoshihiro (70033248)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
2. MATSUMOTO Takahiro (10304495)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results

WATANABE TAKAHIRO 渡邊 孝博

WATANABE Takahiro 渡邊 孝博

渡辺 孝博 ワタナベ タカヒロ

Research Projects

Research Products

Co-Researchers

Research on NoC system robust to fluctuation of traffic patternsPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Review Section

Research Institution

A Study of a Tile-based NoC System using IPs and its DesignPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Research on Digitalized Spread Spectrum Communication System Using Real-Valued Sequences

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

Computer-Aided-Design for Analog-Digital Mixed Large Scaled Integration CircuitsPrincipal Investigator

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

[Journal Article] A Hotspot-Pattern-Aware Routing Algorithm for Networks-on-Chip2019

Author(s)

Journal Title

DOI

Data Source

[Journal Article] Fault-Tolerant Traffic-Aware Routing Algorithm for 3-D Photonic Networks-on-Chip2019

Author(s)

Journal Title

DOI

Data Source

[Journal Article] Low-Cost Congestion Detection Mechanism for Networks-on-Chip2019

Author(s)

Journal Title

DOI

Data Source

[Journal Article] A Traffic-Robust Routing Algorithm for Network-on-Chip Systems.2019

Author(s)

Journal Title

DOI

Data Source

[Journal Article] A Sophisticated Routing Algorithm in 3D NoC with Fixed TSVs for Low Energy and Latency2014

Author(s)

Journal Title

NAID

Data Source

[Journal Article] LVSの出力情報を活用したVLSI電源配線幅の高速検証システム2013

Author(s)

Journal Title

NAID

Data Source

[Journal Article] LVSの出力情報を活用した VLSI 電源配線幅の高速検証システム2013

Author(s)

Journal Title

NAID

Data Source

[Journal Article] An Efficient Algorithm for 3D NoC Architecture Optimization2013

Author(s)

Journal Title

NAID

Data Source

[Journal Article] An Efficient Algorithm for 3D NoC Architecture Optimization2013

Author(s)

Journal Title

NAID

Data Source

[Journal Article] Region-oriented Placement Algorithm for Coarse-grained Power-gating FPGA Architecture2012

Author(s)

Journal Title

NAID

Data Source

WATANABE TAKAHIRO 渡邊孝博

WATANABE Takahiro 渡邊孝博

渡辺孝博ワタナベタカヒロ