Takagi Kazuyoshi 高木一義

… Alternative Names

TAKAGI Kazuyoshi 高木一義

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Researcher Number	70273844
Other IDs
External Links
Affiliation (Current)	2025: 三重大学, 工学研究科, 教授
Affiliation (based on the past Project Information) *help	2025: 三重大学, 工学研究科, 教授 2019 – 2020: 三重大学, 工学研究科, 教授 2012 – 2018: 京都大学, 情報学研究科, 准教授 2014: 京都大学, 大学院情報学研究科, 准教授 2007 – 2010: Nagoya University, 大学院・情報科学研究科, 准教授 … More 2008: Nagoya University, 大学院情報学研究科, 准教授 2006: 名古屋大学, 大学院情報科学研究科, 助教授 2004 – 2005: Nagoya University, Graduate School of Information Science, Assistant Professor, 大学院・情報科学研究科, 講師 2003: 名古屋大学, 情報科学研究科, 講師 1999 – 2002: 名古屋大学, 工学研究科, 講師 1999 – 2001: 名古屋大学, 大学院・工学研究科, 講師 1995 – 1998: 奈良先端科学技術大学院大学, 情報科学研究科, 助手 Less
Review Section/Research Field	Principal Investigator Basic Section 60040:Computer system-related / Computer system / Computer system/Network / Science and Engineering / Fundamental theory of informatics / 計算機科学 Except Principal Investigator 計算機科学 / Computer system/Network / Computer system / Science and Engineering
Keywords	Principal Investigator 論理回路 / 超伝導単一磁束量子デバイス / 論理関数 / 超伝導単一磁束量子回路 / 設計自動化 / 計算モデル / 分岐プログラム / 決定グラフ / パルス論理 / タイミング解析 … More / 論理回路設計 / 集積回路のテスト / 信頼性 / LSI設計技術 / タイミング故障 / テストパタン生成 / レイアウト設計 / タイミング設計 / 単一磁束量子論理回路 / タイミング検証 / クロック配信 / 論理設計支援 / 局在電磁波配線 / 単一磁束量子回路 / 超伝導論理回路 / 超電導論理回路 / 論理合成 / 関数分解 / グラフ配置問題 / LSIレイアウト … More Except Principal Investigator VLSI / 算術演算回路 / ハードウェアアルゴリズム / ソフトウェア協調設計 / ハードウェア / OBDD / hardware algorithm / High Level Synthesis / 論理合成 / FPGA / 高位合成 / 汎用コプロセッサ / Pocエディタ / 細胞プログラミング / 正弦・余弦関数計算 / 指数・対数関数計算 / ＦＰＧＡ / 逆三角関数 / 浮動小数点演算 / 関数計算 / 計算機システム / cryptosystem / modular reduction / integer Division / modular arithmetic / finite field arithmetic / 暗号化・復号 / 有限体上の除算 / 剰余系除算 / 乗算剰余算 / 暗号処理 / 剰余計算 / 整数除算 / 剰余系演算 / 有限体上の演算 / Quantum Computing / Timing Verification / Dynamical Re-construction / Re-configurability / Environmental Adaptability / 量子計算 / ハードウェアのタイミング検証 / 知識ベース / 能動形プログラム / 環境適用 / 量子アルゴリズム / アクティブソフトウェア / タイミング検証 / 動的変更機構 / 再構成可能性 / 環境適応 / modular division / division in GF (2^m) / powering / cube rooting / Euclidean norm computation / arithmetic circuit / 乗算 / 加算木 / 加算 / 三角関数計算 / 復号 / 符号化 / コンピュータグラフィクス / ノルム計算 / 剰余除算 / GF(2^m)上の除算 / べき乗算 / 立方根計算 / ユークリッドノルム計算 / ハート・ウェアアルゴリズム / 算術演算 / C compiler / General Purpose Co-processor / Field Programmable Gate Array (FPGA) / Hardware Accelerator / Reconfigurable System / Software Co-operation / Software Codesign / Hardware / コプロセッサ / エミュレーション / コデザイン / 並列化コンパイラ / ハードウェア記述言語 / 汎用コブロセッサ / Cコンパイラ / ハードウェアアクセラレータ / 再構成可能システム / ソフトウェア協調動作 / ソフトウェアコデザイン / (2)算術演算回路 / オンライン誤り検出 / 演算器アレイ / テスト容易化設計 / 加算器 / 乗算器 / VLSIのテスト / 計算複雑さ / 組合せ回路 / アルゴリズム / 再構成可能プロセッサ / 動的結合機構 / 能動関数 / 能動形計算モデル / 発展するソフトウェア構成法 / 手指動作記述文 / 前条件・後条件 / パターン細胞 / 発展的ソフトウェア構成法 Less

Studies on Operation Timing Optimization of Superconducting Single-Flux-Quantum CircuitsPrincipal Investigator
- Principal Investigator
  
  高木一義
- Project Period (FY)
  2025 – 2027
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Mie University
Researches on Testing and Reliable Design of Superconducting Rapid Single-Flux-Quantum CircuitsPrincipal Investigator
- Principal Investigator
  
  Takagi Kazuyoshi
- Project Period (FY)
  2018 – 2020
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Mie University
  Kyoto University
Studies on hardware assist of floating point function calculation
- Principal Investigator
  
  Takagi Naofumi
- Project Period (FY)
  2016 – 2019
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system
- Research Institution
  Kyoto University
Studies on Layout Design Methods for Logic Circuits using Superconducting DevicesPrincipal Investigator
- Principal Investigator
  
  Kazuyoshi Takagi
- Project Period (FY)
  2015 – 2017
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system
- Research Institution
  Kyoto University
Research on high-performance and highly-dependable floating-point arithmetic unit arrays by contriving data representation
- Principal Investigator
  
  TAKAGI Naofumi
- Project Period (FY)
  2012 – 2014
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Kyoto University
studies on high-reliability timing design methods for logic circuits using advanced devicesPrincipal Investigator
- Principal Investigator
  
  TAKAGI Kazuyoshi
- Project Period (FY)
  2012 – 2014
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system/Network
- Research Institution
  Kyoto University
Research on synthesis of easily-testable arithmetic circuits
- Principal Investigator
  
  TAKAGI Naofumi
- Project Period (FY)
  2008 – 2010
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Nagoya University
Studies on Logic Design and Design Automation of Single-Flux-Quantum Circuits based on Localized Electromagnetic WavesPrincipal Investigator
- Principal Investigator
  
  KAZUYOSHI Takagi (TAKAGI Kazuyoshi)
- Project Period (FY)
  2006 – 2009
- Research Category
  
  Grant-in-Aid for Scientific Research on Priority Areas
- Review Section
  
  Science and Engineering
- Research Institution
  Nagoya University
次世代集積回路設計のための決定グラフによる論理関数表現に関する研究Principal Investigator
- Principal Investigator
  
  高木一義
- Project Period (FY)
  2005 – 2007
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Fundamental theory of informatics
- Research Institution
  Nagoya University
ハードウェアアルゴリズムの性能評価に関する研究
- Principal Investigator
  
  NAOFUMI Takagi
- Project Period (FY)
  2004 – 2007
- Research Category
  
  Grant-in-Aid for Scientific Research on Priority Areas
- Review Section
  
  Science and Engineering
- Research Institution
  Nagoya University
Researches on hardware algorithms for arithmetic operations in finite fields.
- Principal Investigator
  
  TAKAGI Naofumi
- Project Period (FY)
  2002 – 2004
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  計算機科学
- Research Institution
  Nagoya University
種々の決定グラフを用いた論理関数表現とその回路合成への応用に関する研究Principal Investigator
- Principal Investigator
  
  高木一義
- Project Period (FY)
  2000 – 2001
- Research Category
  
  Grant-in-Aid for Encouragement of Young Scientists (A)
- Research Field
  
  計算機科学
- Research Institution
  Nagoya University
Implementation of Adaptable Hardware and Software for Changing Environment
- Principal Investigator
  
  WATANABE Katsumasa
- Project Period (FY)
  1999 – 2001
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  計算機科学
- Research Institution
  NARA INSTITUTE OF SCIENCE AND TECHNOLOGY
Studies on hardware algorithms for high-performance arithmetic circuits
- Principal Investigator
  
  TAKAGI Naofumi
- Project Period (FY)
  1998 – 2000
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  計算機科学
- Research Institution
  Nagoya University
コンテンフに適応する発展的ソフトウェアの構成法
- Principal Investigator
  
  WATANABE Katsumasa
- Project Period (FY)
  1997
- Research Category
  
  Grant-in-Aid for Scientific Research on Priority Areas
- Research Institution
  Nara Institute of Science and Technology
コンテンツに適応する発展的ソフトウェアの構成法
- Principal Investigator
  
  渡邉勝正
- Project Period (FY)
  1997 – 1998
- Research Category
  
  Grant-in-Aid for Scientific Research on Priority Areas (A)
- Research Institution
  Nara Institute of Science and Technology
Research on Reconfigurable General Purpose Co-processor Systems and Their Optimized Hardware/Software Codesign Compiler
- Principal Investigator
  
  WATANABE Katsumasa
- Project Period (FY)
  1995 – 1997
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  計算機科学
- Research Institution
  Nara Institute of Science and Technology

[Journal Article] Layout Design Flow for RSFQ Circuits Based on Cell Clustering and Mixed Wiring of JTLs and PTLs2020
- Author(s)
  Takashi Dejima, Kazuyoshi Takagi, and Naofumi Takagi
- Journal Title
  
  IEEE Transactions on Applied Superconductivity
  
  Volume: 30-7 Issue: 7 Pages: 1302506-1302506
- DOI
  10.1109/tasc.2020.3014928
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18H05211, KAKENHI-PROJECT-18K11213
[Journal Article] Splitter-Aware Multi-Terminal Routing with Length Matching Constraint for RSFQ Circuits2020
- Author(s)
  M. Kou, P.-Y. Cheng, J. Zeng, T.-Y. Ho, K. Takagi, H. Yao
- Journal Title
  
  IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems
  
  Volume: (early access) Issue: 11 Pages: 1-14
- DOI
  10.1109/tcad.2020.3042159
- Peer Reviewed / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11213
[Journal Article] Logic simulation tool for RSFQ circuits accepting arrivals of multiple pulses in a clock period2020
- Author(s)
  Kito Nobutaka、Udatsu Shohei、Takagi Kazuyoshi
- Journal Title
  
  Journal of Physics: Conference Series
  
  Volume: 1590 Issue: 1 Pages: 012041-012041
- DOI
  10.1088/1742-6596/1590/1/012041
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-19K11888, KAKENHI-PROJECT-18K11213
[Journal Article] A Two-Step Routing Method with Wire Length Budgeting for PTL Routing of SFQ Logic Circuits2020
- Author(s)
  Kei Kitamura, Kazuyoshi Takagi, and Naofumi Takagi
- Journal Title
  
  Journal of Physics
  
  Volume: 1590 Issue: 1 Pages: 012043-012043
- DOI
  10.1088/1742-6596/1590/1/012043
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-18H05211, KAKENHI-PROJECT-18K11213
[Journal Article] Concurrent Error Detectable Carry Select Adder with Easy Testability2019
- Author(s)
  Nobutaka Kito, Naofumi Takagi
- Journal Title
  
  IEEE Transactions on Computers
  
  Volume: 68 Issue: 7 Pages: 1105-1110
- DOI
  10.1109/tc.2019.2895074
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-16H02795
[Journal Article] A Fast Wire-Routing Method and an Automatic Layout Tool for RSFQ Digital Circuits Considering Wire-Length Matching2018
- Author(s)
  Kito Nobutaka、Takagi Kazuyoshi、Takagi Naofumi
- Journal Title
  
  IEEE Transactions on Applied Superconductivity
  
  Volume: 28 Issue: 4 Pages: 1-5
- DOI
  10.1109/tasc.2018.2793203
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-15K00075, KAKENHI-PROJECT-16K16029
[Journal Article] Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis2014
- Author(s)
  Akihiro Suda, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi
- Journal Title
  
  IEICE Trans. Fundamentals
  
  Volume: E97.A Issue: 12 Pages: 2498-2506
- DOI
  10.1587/transfun.E97.A.2498
- NAID
  130004706413
- ISSN
  0916-8508, 1745-1337
- Language
  English
- Peer Reviewed / Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-24300019, KAKENHI-PROJECT-26870303
[Journal Article] Low-Overhead Fault-Secure Parallel Prefix Adder by Carry-Bit Duplication2013
- Author(s)
  Nobutaka Kito, Naofumi Takagi
- Journal Title
  
  IEICE Trans. Inf. & Syst.
  
  Volume: E96.D Issue: 9 Pages: 1962-1970
- DOI
  10.1587/transinf.E96.D.1962
- NAID
  130003370984
- ISSN
  0916-8532, 1745-1361
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-24300019, KAKENHI-PROJECT-25730033
[Journal Article] A C-Testable 4-2 Adder Tree for an Easily Testable High-Speed Multiplier2010
- Author(s)
  Nobutaka Kito, Kensuke Hanai, Naofumi Takagi
- Journal Title
  
  IEICE Trans.on Information and Systems
  
  Volume: E93-D Pages: 2783-2791
- NAID
  10027641210
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300016
[Journal Article] A C-Testable 4-2 Adder Tree for an Easily Testable High-Speed Multiplier2010
- Author(s)
  Nobutaka Kito、Kensuke Hanai、Naofumi Takagi
- Journal Title
  
  IEICE Transactions on Information and Systems vol.E93-D、no.10
  
  Pages: 2783-2791
- NAID
  10027641210
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300016
[Journal Article] けた上げ保存加算器で構成された部分積加算部をもつ乗算器のテスト2009
- Author(s)
  鬼頭信貴、高木直史
- Journal Title
  
  電子情報通信学会論文誌D J92-D巻、7号
  
  Pages: 994-1002
- NAID
  110007331954
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300016
[Journal Article] Bipartite modular multiplication method2008
- Author(s)
  M. E. Kaihara and N. Takagi
- Journal Title
  
  IEEE Transactions on Computers Vol. 57, No. 2
  
  Pages: 157-164
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-16092210
[Journal Article] A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits2008
- Author(s)
  Koji Obata, Kazuyoshi Takagi, Naofumi Takagi
- Journal Title
  
  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E91-A
  
  Pages: 3772-3782
- NAID
  10026854486
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18080008
[Journal Article] A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits2008
- Author(s)
  Koji Obata, Kazuyoshi Takagi, Naofumi Takagi
- Journal Title
  
  IEICE Trans. Fundamentals Vol.E91-A
  
  Pages: 3772-3782
- NAID
  10026854486
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18080008
[Journal Article] 種々の部分積加算構造をもつテスト容易な乗算器の設計手法2008
- Author(s)
  鬼頭信貴、高木直史
- Journal Title
  
  電子情報通信学会論文誌D J91-D巻、10号
  
  Pages: 2478-2486
- NAID
  110007380919
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300016
[Journal Article] A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits2008
- Author(s)
  Koji Obata, Kazuyoshi Takagi, Naofumi Takagi
- Journal Title
  
  IEICE Trans. Fundamentals E91-A
  
  Pages: 3772-3782
- NAID
  10026854486
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18080008
[Journal Article] 種々の部分積加算構造をもっテスト容易な乗算器の設計手法2008
- Author(s)
  鬼頭信貴, 高木直史
- Journal Title
  
  電子情報通信学会論文誌D J91-D, No. 10
  
  Pages: 2478-2486
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300016
[Journal Article] A method of sequential circuit synthesis using one-hot encoding for single-flux-quantum digital circuits2007
- Author(s)
  Koji Obata, Kazuyoshi Takagi, Naofumi Takagi
- Journal Title
  
  IEICE Trans. Electron. E90-C
  
  Pages: 2278-2284
- NAID
  110007538875
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18080008
[Journal Article] A method of sequential circuit synthesis using one-hot encoding for sing le-flux-quantum digital circuits2007
- Author(s)
  K. Obata, K. Takagi, N. Takagi
- Journal Title
  
  IEICE Trans. Electron. E90-C
  
  Pages: 2278-2284
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18080008
[Journal Article] 拡張ユークリッド法に基づくGF(2m)上の乗算・逆元計算のための複合回路2007
- Author(s)
  小林克希, 高木直史
- Journal Title
  
  電子情報通信学会技術研究報告 VLD2006-142
  
  Pages: 13-18
- NAID
  110006248801
- Data Source
  KAKENHI-PROJECT-16092210
[Journal Article] An algorithm for inversion in GF(2^m)suitable for implementation using a polynomial multiply instruction on GF(2)2007
- Author(s)
  K. Kobayashi, N. Takagi and K. Takagi
- Journal Title
  
  Proc. of the 18th IEEE Symposium on Computer Arithmetic
  
  Pages: 105-112
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-16092210
[Journal Article] Logic Synthesis Method for Dual-Rail RSFQ Digital Circuits Using Root-Shared Binary Decision Diagrams2007
- Author(s)
  K.Obata, K.Takagi, N.Takagi
- Journal Title
  
  IEICE Trans. Fundamentals Vol. E90-A,No. 1
  
  Pages: 257-266
- Data Source
  KAKENHI-PROJECT-17700010
[Journal Article] 配線層数の乗算器の回路面積への影響について2007
- Author(s)
  川島裕崇, 高木直史, 高木一義
- Journal Title
  
  電子情報通信学会技術研究報告 VLD2006-141
  
  Pages: 7-12
- NAID
  110006248800
- Data Source
  KAKENHI-PROJECT-16092210
[Journal Article] Design of a combined circuit for multiplication and inversion in GF(2^m)2007
- Author(s)
  K. Kobayashi and N. Takagi
- Journal Title
  
  Proc. of the Workshop on Synthesis and System Integration of Mixed Information Technologies 2007
  
  Pages: 15-20
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-16092210
[Journal Article] A Method of Sequential Circuit Synthesis using One-hot Encoding for Single-Flux-Quantum Digital Circuits2007
- Author(s)
  Koji Obata, Kazuyoshi Takagi, Naofumi Takagi
- Journal Title
  
  IEICE Trans. Electron. Vol.E90-C
  
  Pages: 2278-2284
- NAID
  110007538875
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18080008
[Journal Article] Hardware algorithm for computing reciprocal of Euclidean norm of a 3-D vector2006
- Author(s)
  F.Kumazawa, N.Takagi
- Journal Title
  
  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A, 6
  
  Pages: 1799-1806
- NAID
  110007502924
- Data Source
  KAKENHI-PROJECT-16092210
[Journal Article] 部分順序付き1回読み分岐プログラムのサイズの下界2006
- Author(s)
  篠原信仁, 高木一義, 高木直史
- Journal Title
  
  電子情報通信学会技術研究報告コンピュテーション研究会 COMP2006-41
  
  Pages: 1-8
- NAID
  110006163293
- Data Source
  KAKENHI-PROJECT-17700010
[Journal Article] A transduction-based Framework to Synthesize RSFQ Circuits2006
- Author(s)
  S.Yamashita, K.Tanaka, H.Takada, K.Obata, K.Takagi
- Journal Title
  
  Proceedings of the Asia and South Pacific Design Automation Conference 2006
  
  Pages: 266-272
- NAID
  110004082734
- Data Source
  KAKENHI-PROJECT-17700010
[Journal Article] A hardware algorithm for integer division using the SD2 representation2006
- Author(s)
  N.Takagi, S.Kadowaki, K Takagi
- Journal Title
  
  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A, 10
  
  Pages: 2874-2881
- NAID
  110007537767
- Data Source
  KAKENHI-PROJECT-16092210
[Journal Article] A VLSI algorithm for integer square-rooting2006
- Author(s)
  N.Takagi, K Takagi
- Journal Title
  
  Proc. 2006 International Symposium on Intelligent Signal Processing and Communication Systems
  
  Pages: 626-629
- Data Source
  KAKENHI-PROJECT-16092210
[Journal Article] Pipelined bipartite modular multiplication2005
- Author(s)
  M.E.Kaihara, N.Takagi
- Journal Title
  
  電子情報通信学会技術研究報告 VLD2005-67
  
  Pages: 37-42
- NAID
  110004018526
- Data Source
  KAKENHI-PROJECT-16092210
[Journal Article] A hardware algorithm for integer division2005
- Author(s)
  N.Takagi, S.Kadowaki, K.Takagi
- Journal Title
  
  Proceedings of the 17th IEEE Symposium on Computer Arithmetic
  
  Pages: 140-146
- Data Source
  KAKENHI-PROJECT-16092210
[Journal Article] Karatsubaアルゴリズムに基づく小面積並列乗算器2005
- Author(s)
  柴岡雅之, 高木直史, 高木一義
- Journal Title
  
  2005年電子情報通信学会総合大会講演論文集基礎・境界
- NAID
  110004737800
- Data Source
  KAKENHI-PROJECT-16092210
[Journal Article] Hardware algorithm for modular multiplication/division based on the extended Euclidean algorithm2005
- Author(s)
  M.E.Kaihara, N.Takagi
- Journal Title
  
  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A,12
  
  Pages: 3610-3617
- NAID
  110004019470
- Data Source
  KAKENHI-PROJECT-16092210
[Journal Article] A hardware algorithm for modular multiplication/division2005
- Author(s)
  M.E.Kaihara, N.Takagi
- Journal Title
  
  IEEE Transactions on Computers Vol.54, no.1
  
  Pages: 12-21
- NAID
  120000978657
- Data Source
  KAKENHI-PROJECT-14380142
[Journal Article] 部分順序付き1回読み分岐プログラム2005
- Author(s)
  篠原信仁, 高木一義, 高木直史
- Journal Title
  
  2005年度夏のLAシンポジウム
- Data Source
  KAKENHI-PROJECT-17700010
[Journal Article] A hardware algorithm for integer division2005
- Author(s)
  N.Takagi, S.Kadowaki
- Journal Title
  
  Proc.of 17th IEEE Symposium on Computer Arithmetic (発表予定)
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14380142
[Journal Article] 算術演算のための減算シフト型ハードウェアアルゴリズムの自動合成ツールの構築2005
- Author(s)
  熊澤文雄, 高木直史
- Journal Title
  
  情報処理学会「DAシンポジウム2005」論文集
  
  Pages: 213-236
- Data Source
  KAKENHI-PROJECT-16092210
[Journal Article] A hardware algorithm for modular multiplication/division2005
- Author(s)
  M.E.Kaihara, N.Takagi
- Journal Title
  
  IEEE Transactions on Computers Vol.54,no.1
  
  Pages: 12-21
- NAID
  120000978657
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14380142
[Journal Article] A hardware algorithm for integer division2005
- Author(s)
  N.Takagi, S.Kadowaki
- Journal Title
  
  Proc.of 17th IEEE Symposium on Computer Arithmetic (発表予定)
- Data Source
  KAKENHI-PROJECT-16092210
[Journal Article] A hardware algorithm for modular multiplication/division2005
- Author(s)
  M.E.Kaihara, N.Takagi
- Journal Title
  
  IEEE Trans.Computers vol.54, no.1
  
  Pages: 12-21
- NAID
  120000978657
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-14380142
[Journal Article] Bipartite modular multiplication2005
- Author(s)
  M.E.Kaihara, N.Takagi
- Journal Title
  
  Springer LNCS3659: Proceedings of 7th International Workshop on Cryptographic Hardware and Embedded Systems -CHES 2005
  
  Pages: 201-210
- NAID
  120000982145
- Data Source
  KAKENHI-PROJECT-16092210
[Journal Article] A hardware algorithm for integer division2005
- Author(s)
  N.Takagi, S.Kadowaki
- Journal Title
  
  Proc.17th IEEE Symp.on Computer Arithmetic (to appear)
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-14380142
[Journal Article] 算術演算のための減算シフト型ハードウェアアルゴリズムの自動合成2004
- Author(s)
  熊澤文雄, 高木直史
- Journal Title
  
  電子情報通信学会技術研究報告 VLD2004-90
  
  Pages: 175-178
- NAID
  110003318205
- Data Source
  KAKENHI-PROJECT-16092210
[Journal Article] A multiplier/divider for modular arithmetic based on the extended Euclidean algorithm2004
- Author(s)
  M.E.Kaihara, N.Takagi
- Journal Title
  
  IEICE Technical Report VLD2004-1
  
  Pages: 1-6
- NAID
  110003294338
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-14380142
[Journal Article] GF(2^m)上の逆元算出のための拡張ユークリッド法に基づくテーブルを用いたアルゴリズム2004
- Author(s)
  小林克希, 高木直史, 高木一義
- Journal Title
  
  電子情報通信学会技術研究報告 VLD2004-2
  
  Pages: 7-12
- NAID
  110003294339
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14380142
[Journal Article] 冗長2進表現の絶対値計算を用いた整数除算回路2004
- Author(s)
  門脇俊介, 高木直史, 高木一義
- Journal Title
  
  電子情報通信学会技術研究報告 VLD2004-3
  
  Pages: 13-18
- Data Source
  KAKENHI-PROJECT-14380142
[Journal Article] An algorithm using look-up table based on extended Euclid's algorithm for computing inversion in GF(2^m)2004
- Author(s)
  K.Kobayashi, N.Takagi, K.Takagi
- Journal Title
  
  IEICE Technical Report VLD2004-2
  
  Pages: 7-12
- NAID
  110003294339
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-14380142
[Journal Article] 拡張ユークリッド法に基づく剰余系乗除算回路2004
- Author(s)
  カイハラマルセロ, 高木直史
- Journal Title
  
  電子情報通信学会技術研究報告 VLD2004-1
  
  Pages: 1-6
- NAID
  110003294338
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14380142
[Journal Article] A VLSI algorithm for modular multiplication/division2003
- Author(s)
  M.E.Kaihara, N.Takagi
- Journal Title
  
  Proc.16th IEEE Symp.on Computer Arithmetic
  
  Pages: 220-227
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-14380142
[Journal Article] A VLSI algorithm for modular multiplication/division2003
- Author(s)
  M.E.Kaihara, N.Takagi
- Journal Title
  
  Proc.of 16th IEEE Symposium on Computer Arithmetic
  
  Pages: 220-227
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14380142
[Journal Article] A VLSI algorithm for division in GF(2^m) based on extended binary GCD algorithm2002
- Author(s)
  Y.Watanabe, N.Takagi, K.Takagi
- Journal Title
  
  IEICE Transactions on Fundamentals vol.E85-A, no.5
  
  Pages: 994-999
- NAID
  110003209115
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14380142
[Journal Article] A VLSI algorithm for division in GF(2m) based on extended binary GCD algorithm2002
- Author(s)
  Y.Watanabe, N.Takagi, K.Takagi
- Journal Title
  
  IEICE Trans.Fundamentals vol.E85-A, no.5
  
  Pages: 994-999
- NAID
  110003209115
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-14380142
[Patent] 剰余系の計算方法及び装置2006
- Inventor(s)
  高木直史, カイハラマルセロ
- Industrial Property Rights Holder
  名古屋大学
- Industrial Property Number
  2006-040859
- Filing Date
  2006-02-17
- Data Source
  KAKENHI-PROJECT-16092210
[Patent] 剰余系の計算方法及び装置並びにプログラム2005
- Inventor(s)
  高木直史, カイハラマルセロ
- Industrial Property Rights Holder
  名古屋大学
- Industrial Property Number
  2005-242956
- Filing Date
  2005-08-24
- Data Source
  KAKENHI-PROJECT-16092210
[Presentation] Static Timing Analysis of an RSFQ Circuit Considering Timing Jitter2020
- Author(s)
  S. Nakamura, K. Takagi, N. Kito, N. Takagi
- Organizer
  33nd International Symposium on Superconductivity (ISS2020)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11213
[Presentation] A Routing Method with Wire Length Matching for RSFQ Logic Circuits using Thin PTLs2020
- Author(s)
  K. Kitamura, K. Takagi, N. Takagi
- Organizer
  13th Superconducting SFQ VLSI Workshop (SSV 2020)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11213
[Presentation] IEEE754 binary64における指数関数の丸め困難ケースについて2020
- Author(s)
  高木直史、高木一義
- Organizer
  2020年電子情報通信学会総合大会
- Data Source
  KAKENHI-PROJECT-16H02795
[Presentation] 逆正弦の高基数CORDICアルゴリズムのFPGA上での実現2020
- Author(s)
  松岡裕志、高木直史、高木一義
- Organizer
  電子情報通信学会VLSI設計技術研究会（2020-01）
- Data Source
  KAKENHI-PROJECT-16H02795
[Presentation] 逆正弦・逆余弦計算の高基数CORDICアルゴリズム2019
- Author(s)
  松岡裕志、高木直史
- Organizer
  電子情報通信学会VLSI設計技術研究会（2019-11）
- Data Source
  KAKENHI-PROJECT-16H02795
[Presentation] Logic Simulation Tool for RSFQ Circuits Accepting Arrivals of Multiple Pulses in a Clock Period2019
- Author(s)
  N. Kito, S. Udatsu, K. Takagi
- Organizer
  32nd International Symposium on Superconductivity (ISS2019)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11213
[Presentation] Test Pattern Generation for Timing Faults in Rapid Single-Flux-Quantum Circuits2019
- Author(s)
  K. Takagi, M. Ono, N. Kito, N.Takagi
- Organizer
  22nd Workshop on Synthesis And System Integration Mixed Information technologies (SASIMI 2019)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11213
[Presentation] A Global Routing Method with Wire Length Budgeting for PTL Routing of SFQ Logic Circuits2019
- Author(s)
  K. Kitamura, K. Takagi, N. Takagi
- Organizer
  32nd International Symposium on Superconductivity (ISS2019)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11213
[Presentation] A Global Routing Method with Wire Length Budgeting for SFQ Logic Circuits2019
- Author(s)
  K. Kitamura, K. Takagi, and N. Takagi
- Organizer
  12th Superconducting SFQ VLSI Workshop (SSV 2019)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11213
[Presentation] Placement and Routing Methods Based on Mixed Wiring of JTLs and PTLs for RSFQ Circuits2019
- Author(s)
  T. Dejima, K. Takagi, N. Takagi
- Organizer
  International Superconducting Electronics Conference (ISEC 2019)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11213
[Presentation] Multi-terminal routing with length-matching for rapid single flux quantum circuits2018
- Author(s)
  Pei-Yi Cheng, Kazuyoshi Takagi, and Tsung-Yi Ho
- Organizer
  International Conference on Computer-Aided Design (ICCAD2018)
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11213
[Presentation] 大規模SFQ論理回路のパルス到着タイミングを最適化する配置手法2018
- Author(s)
  北村圭、高木一義、高木直史
- Organizer
  電子情報通信学会2018年ソサイエティ大会
- Data Source
  KAKENHI-PROJECT-18K11213
[Presentation] 倍精度浮動小数点正弦・余弦関数のＦＰＧＡ向き計算法2018
- Author(s)
  豊島悠紀夫、高木直史
- Organizer
  電子情報通信学会　コンピュータシステム研究会
- Data Source
  KAKENHI-PROJECT-16H02795
[Presentation] 超伝導単一磁束量子（SFQ）回路設計のためのタイミング制約を考慮した自動配置アルゴリズム2018
- Author(s)
  出島貴史、高木直史、高木一義
- Organizer
  DAシンポジウム2018
- Data Source
  KAKENHI-PROJECT-18K11213
[Presentation] SFQディジタル集積回路の設計自動化2018
- Author(s)
  高木一義
- Organizer
  日本学術振興会超伝導エレクトロニクス第146委員会通信・情報処理分科会第16回研究会
- Invited
- Data Source
  KAKENHI-PROJECT-18K11213
[Presentation] 大規模SFQ論理回路の配線修正によるタイミング最適化2018
- Author(s)
  北村圭、高木一義、高木直史
- Organizer
  2018年電子情報通信学会総合大会
- Data Source
  KAKENHI-PROJECT-15K00075
[Presentation] 配線長マッチングを考慮した自動配置によるRSFQ回路のレイアウト面積削減2017
- Author(s)
  鬼頭信貴, 高木一義, 高木直史
- Organizer
  2017年電子情報通信学会総合大会
- Place of Presentation
  名城大学
- Data Source
  KAKENHI-PROJECT-15K00075
[Presentation] A fast wire-routing method and an automatic layout tool for RSFQ digital circuits considering wire-length matching2017
- Author(s)
  N. Kito, K. Takagi, N. Takagi
- Organizer
  13th European Conference on Applied Superconductivity (EUCAS 2017)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K00075
[Presentation] 倍精度浮動小数点対数関数のＦＰＧＡ向き計算法2017
- Author(s)
  藤原康史、高木一義、高木直史
- Organizer
  電子情報通信学会コンピュータシステム研究会
- Place of Presentation
  具志川農村環境改善センター（沖縄県島尻郡久米島町）
- Year and Date
  2017-03-09
- Data Source
  KAKENHI-PROJECT-16H02795
[Presentation] 高基数ＳＴＬ法を用いたＦＰＧＡ向き指数関数計算法2017
- Author(s)
  藤原康史、高木一義、高木直史
- Organizer
  電子情報通信学会　リコンフィギャラブルシステム研究会
- Data Source
  KAKENHI-PROJECT-16H02795
[Presentation] 高基数ＳＴＬ法を用いたＦＰＧＡ向き対数関数計算法2017
- Author(s)
  藤原康史、高木一義、高木直史
- Organizer
  情報処理学会　ＤＡシンポジウム
- Data Source
  KAKENHI-PROJECT-16H02795
[Presentation] Development of CAD Tools for SFQ Logic Circuits and Design of Data Path Circuits for SFQ Bit-slice Processors2017
- Author(s)
  N.Takagi, K.Takagi, and N.Kito
- Organizer
  10th Superconducting SFQ VLSI Workshop (SSV2017)
- Place of Presentation
  Nagoya University
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K00075
[Presentation] Extension of a Logic Simulation System for Simulation -Based Verification of RSFQ Logic Circuits2016
- Author(s)
  N.Kito, G.Matsumoto, K.Takagi, N.Takagi
- Organizer
  9th Superconducting SFQ VLSI Workshop (SSV2016)
- Place of Presentation
  Yokohama National University
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K00075
[Presentation] Fast Length-Matching Routing for Rapid Single Flux Quantum Circuits2016
- Author(s)
  N.Kito, K.Takagi, N.Takagi
- Organizer
  20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016)
- Place of Presentation
  Kyoto Research Park
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-15K00075
[Presentation] 3入力多数決ゲートを用いた5変数論理関数の最小段数回路2015
- Author(s)
  守家大雄、高木一義、高木直史
- Organizer
  2014年冬のLAシンポジウム
- Place of Presentation
  京都大学吉田キャンパス北部構内数理解析研究所、京都府京都市
- Year and Date
  2015-01-28
- Data Source
  KAKENHI-PROJECT-24500061
[Presentation] 単一磁束量子回路のパルス到着タイミングを最適化する配置配線手法2015
- Author(s)
  西村翔、高木一義、高木直史
- Organizer
  電子情報通信学会総合大会
- Place of Presentation
  立命館大学びわこ・くさつキャンパス、滋賀県草津市
- Year and Date
  2015-03-11
- Data Source
  KAKENHI-PROJECT-24500061
[Presentation] Minimum Depth Logic Circuits for Five-Variable Logic Functions Using Three-Input Majority Gates2014
- Author(s)
  M.Moriya, K.Takagi, N.Takagi
- Organizer
  Superconducting SFQ VLSI Workshop (SSV 2014)
- Place of Presentation
  National Institute of Information and Communications Technology (NICT), Kobe, Japan
- Year and Date
  2014-12-01
- Data Source
  KAKENHI-PROJECT-24500061
[Presentation] プログラマブルＳｏＣのためのシステム設計環境におけるフロントエンドの実装と事例評価2014
- Author(s)
  東遼平、高瀬英希、高木一義、高木直史
- Organizer
  ＥＴＮＥＴ２０１４
- Place of Presentation
  沖縄県石垣市　ＩＣＴ文化ホール
- Data Source
  KAKENHI-PROJECT-24300019
[Presentation] 部分二重化を用いた微小誤りを許容するオンライン誤り検出可能な浮動小数点乗算器2014
- Author(s)
  鬼頭信貴、秋元一志、高木直史
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  東京都港区　機械振興会館
- Year and Date
  2014-06-20
- Data Source
  KAKENHI-PROJECT-24300019
[Presentation] プログラマブルＳｏＣのためのシステム設計環境の検討とＳＷ－ＨＷインタフェース生成手法の実装2014
- Author(s)
  東遼平、高瀬英希、高木一義、高木直史
- Organizer
  情報処理学会システムＬＳＩ設計技術研究会
- Place of Presentation
  横浜市　慶応義塾大学日吉キャンパス
- Data Source
  KAKENHI-PROJECT-24300019
[Presentation] 行列多項式 I+A+A^2+…+A^{N-1} の計算における乗算回数について2014
- Author(s)
  松本耕太郎、高木直史、高木一義
- Organizer
  電子情報通信学会コンピュテーション研究会
- Place of Presentation
  豊橋市　豊橋技術科学大学
- Year and Date
  2014-09-02
- Data Source
  KAKENHI-PROJECT-24300019
[Presentation] Automatic Placement and Routing of a Pipelined Module in an RSFQ Logic Circuit with Timing Constraints2014
- Author(s)
  S.Nishimura, K.Takagi, N.Takagi
- Organizer
  Superconducting SFQ VLSI Workshop for Young Scientists (SSV2014-YS)
- Place of Presentation
  Nagoya University
- Data Source
  KAKENHI-PROJECT-24500061
[Presentation] 組込みマルチコアシステムにおけるタスク割付およびスクラッチパッドメモリ割当の同時最適化2013
- Author(s)
  松本耕太朗、高瀬英希、高木一義、高木直史
- Organizer
  情報処理学会　ＤＡシンポジウム
- Place of Presentation
  岐阜県下呂市　ホテル水明館
- Data Source
  KAKENHI-PROJECT-24300019
[Presentation] 組込みシステム向けＤＶＦＳアルゴリズムのリアルタイムＯＳへの実装および比較評価2013
- Author(s)
  岩田淳、高瀬英希、高木一義、高木直史
- Organizer
  第１２回情報科学技術フォーラム
- Place of Presentation
  鳥取市　鳥取大学
- Data Source
  KAKENHI-PROJECT-24300019
[Presentation] ＩＥＥＥ７５４標準丸めに対応した斜辺計算のためのＶＬＳＩアルゴリズム2013
- Author(s)
  矢高裕之、高木直史
- Organizer
  デザインガイア２０１３
- Place of Presentation
  鹿児島市　鹿児島県文化センター
- Data Source
  KAKENHI-PROJECT-24300019
[Presentation] 高位合成における非一様依存性を持つ入れ子ループ向けのバッファ構成法2013
- Author(s)
  須田瑛太、高瀬英希、高木一義、高木直史
- Organizer
  デザインガイア２０１３
- Place of Presentation
  鹿児島市　鹿児島県文化センター
- Data Source
  KAKENHI-PROJECT-24300019
[Presentation] 桁上げビットの二重化によるセルフチェッキング桁上げ先見加算器2013
- Author(s)
  三苫晃弘、鬼頭信貴、高木直史
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  対馬市交流センター(長崎県対馬市)
- Year and Date
  2013-03-14
- Data Source
  KAKENHI-PROJECT-24300019
[Presentation] 浮動小数点演算器アレイの構成のための評価環境2013
- Author(s)
  伊藤勇也、高木一義、高木直史, 他
- Organizer
  電子情報通信学会コンピュータシステム研究会
- Place of Presentation
  対馬市交流センター(長崎県対馬市)
- Year and Date
  2013-03-14
- Data Source
  KAKENHI-PROJECT-24300019
[Presentation] 剰余符号を用いたオンライン誤り検出可能な浮動小数点乗算器2013
- Author(s)
  山口大樹、鬼頭信貴、高木直史
- Organizer
  第６９回ＦＴＣ研究会
- Place of Presentation
  山口市　かんぽの宿湯田
- Data Source
  KAKENHI-PROJECT-24300019
[Presentation] 部分二重化を用いたオンライン誤り検出可能な乗算器2013
- Author(s)
  秋元一志、鬼頭信貴、高木直史
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  対馬市交流センター(長崎県対馬市)
- Year and Date
  2013-03-14
- Data Source
  KAKENHI-PROJECT-24300019
[Presentation] High-Level Synthesis for Nested Loop Kernels with Non-Uniform Dependencies2013
- Author(s)
  Akihiro Suda, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi
- Organizer
  SASIMI2013
- Place of Presentation
  札幌市　ホテル札幌ガーデンパレス
- Data Source
  KAKENHI-PROJECT-24300019
[Presentation] 剰余検査によるオンライン誤り検出可能な浮動小数点乗算器2013
- Author(s)
  山口大樹、鬼頭信貴、高木直史
- Organizer
  情報処理学会　ＤＡシンポジウム
- Place of Presentation
  岐阜県下呂市　ホテル水明館
- Data Source
  KAKENHI-PROJECT-24300019
[Presentation] 桁上げ生成二重化によるフォールドセキュアな並列プレフィクス加算器の構成法2012
- Author(s)
  鬼頭信貴、高木直史
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  九州大学医学部百周年講堂(福岡市)
- Year and Date
  2012-11-28
- Data Source
  KAKENHI-PROJECT-24300019
[Presentation] Timing Optimization Methods for Superconducting SFQ Circuits2010
- Author(s)
  Kazuyoshi Takagi, Shota Takeshima, Motoki Sato, Masamitsu Tanaka, Naofumi Takagi
- Organizer
  Superconducting SFQ VLSI Workshop (SSV 2010)
- Place of Presentation
  Yokohama National University.
- Year and Date
  2010-01-12
- Data Source
  KAKENHI-PROJECT-18080008
[Presentation] Timing Optimization Methods for Superconducting SFQ Circuits2010
- Author(s)
  Kazuyoshi Takagi, Shota Takeshima, Motoki Sato, Masamitsu Tanaka, Naofumi Takagi
- Organizer
  Superconducting SFQ VLSI Workshop (SSV 2010)
- Place of Presentation
  横浜市
- Year and Date
  2010-01-12
- Data Source
  KAKENHI-PROJECT-18080008
[Presentation] A Verification Method for Pipeline Processing Behavior of Single-Flux-Quantum Circuits by Equivalence Checking of Timed Logic Formulae2010
- Author(s)
  Motoki Sato, Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi
- Organizer
  Superconducting SFQ VLSI Workshop (SSV 2010)
- Place of Presentation
  Yokohama National University
- Year and Date
  2010-01-12
- Data Source
  KAKENHI-PROJECT-18080008
[Presentation] A Verification Method for Pipeline Processing Behavior of Single-Flux-Quantum Circuits by Equivalence Checking of Timed Logic Formulae2010
- Author(s)
  Motoki Sato, Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi
- Organizer
  Superconducting SFQ VLSI Workshop (SSV 2010)
- Place of Presentation
  横浜市
- Year and Date
  2010-01-12
- Data Source
  KAKENHI-PROJECT-18080008
[Presentation] Verification Method of Pipeline Processing Behavior of SFQ Circuits2009
- Author(s)
  Motoki Sato, Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi
- Organizer
  Superconducting SFQ VLSI Workshop (SSV 2009)
- Place of Presentation
  福岡市
- Year and Date
  2009-06-15
- Data Source
  KAKENHI-PROJECT-18080008
[Presentation] SFQ回路のためのレイアウトを考慮したスキューのあるクロック木の構成法2009
- Author(s)
  伊藤祐喜、高木一義、高木直史
- Organizer
  電子情報通信学会総合大会
- Place of Presentation
  愛媛大学
- Year and Date
  2009-03-20
- Data Source
  KAKENHI-PROJECT-18080008
[Presentation] 単一磁束量子回路のためのパイプライン検証手法2009
- Author(s)
  佐藤元紀、田中雅光、高木一義、高木直史
- Organizer
  2009年電子情報通信学会エレクトロニクスソサイエティ大会
- Place of Presentation
  新潟市
- Year and Date
  2009-09-18
- Data Source
  KAKENHI-PROJECT-18080008
[Presentation] パイプライン動作を考慮した単一磁束量子回路のための論理設計検証手法2009
- Author(s)
  佐藤元紀、田中雅光、高木一義、高木直史
- Organizer
  電子情報通信学会SCE研究会
- Place of Presentation
  東京都
- Year and Date
  2009-10-20
- Data Source
  KAKENHI-PROJECT-18080008
[Presentation] A Method for Layout-Driven Skewed Clock Tree Synthesis for SFQ Circuits2009
- Author(s)
  Kazuyoshi Takagi, Yuki Ito, Masamitsu Tanaka, Naofumi Takagi
- Organizer
  Superconducting SFQ VLSI Workshop (SSV 2009)
- Place of Presentation
  福岡市
- Year and Date
  2009-06-15
- Data Source
  KAKENHI-PROJECT-18080008
[Presentation] Computer-Aided Design of Superconducting SFQ Digital Circuits2008
- Author(s)
  K. Takagi, N. Takagi, M. Tanaka, K. Obata, Y. Ito
- Organizer
  Superconducting SFQ VLSI Workshop (SSV 2008)
- Place of Presentation
  Yokohama National University, Yokohama, Japan
- Year and Date
  2008-03-17
- Data Source
  KAKENHI-PROJECT-17700010
[Presentation] 多層配線単三磁束量子回路のための自動配線手法2008
- Author(s)
  竹島将太、田中雅光、高木三義、高木直史
- Organizer
  電子情報通信学会超伝導エレクトロニクス研究会
- Place of Presentation
  産業技術総合研究所
- Year and Date
  2008-10-30
- Data Source
  KAKENHI-PROJECT-18080008
[Presentation] Level-testability of multi-operand adders2008
- Author(s)
  Nobutaka Kito, Naofumi Takagi
- Organizer
  17th Asia Test Symposium
- Place of Presentation
  京王プラザホテル札幌(札幌市)
- Year and Date
  2008-11-26
- Data Source
  KAKENHI-PROJECT-20300016
[Presentation] Test generation for multi-operand adders consisting of full adders2008
- Author(s)
  鬼頭信貴, 高木直史
- Organizer
  電子情報通信学会ディペンダブルコンピューティング研究会
- Place of Presentation
  機械振興会館(東京都港区)
- Year and Date
  2008-06-20
- Data Source
  KAKENHI-PROJECT-20300016
[Presentation] Computer-Aided Design of Superconducting SFQ Digital Circuits2008
- Author(s)
  Kazuyoshi Takagi, Naofumi Takagi, Masamitsu Tanaka, Koji Obata, Yuki Ito
- Organizer
  Superconducting SFQ VLSI Workshop (SSV 2008)
- Place of Presentation
  Yokohama National University
- Year and Date
  2008-03-17
- Data Source
  KAKENHI-PROJECT-18080008
[Presentation] 多層配線単一磁束量子回路のための自動配線手法2008
- Author(s)
  竹島将太、田中雅光、高木一義、高木直史
- Organizer
  電子情報通信学会超伝導エレクトロニクス研究会
- Place of Presentation
  産業技術総合研究所
- Year and Date
  2008-10-30
- Data Source
  KAKENHI-PROJECT-18080008
[Presentation] 単一磁束量子回路による冗長2進表現を用いたシストリック開平器の設計2007
- Author(s)
  田中雅光、小畑幸嗣、高木一義、高木直史
- Organizer
  電子情報通信学会エレクトロニクスソサイエティ大会
- Place of Presentation
  鳥取大学
- Year and Date
  2007-09-11
- Data Source
  KAKENHI-PROJECT-18080008
[Presentation] 配線遅延を考慮したハードウェアアルゴリズムの評価2007
- Author(s)
  長瀬哲也, 高木一義, 高木直史
- Organizer
  電子情報通信学会コンピュテーション研究会
- Place of Presentation
  広島大学(東広島市)
- Year and Date
  2007-12-14
- Data Source
  KAKENHI-PROJECT-16092210
[Presentation] シストリックアーキテクチャに基づく高スループットsfqビットシリアル浮動小数点乗算器2007
- Author(s)
  小畑幸嗣、古田卓也、高木一義、高木直史
- Organizer
  電子情報通信学会エレクトロニクスソサイエティ大会
- Place of Presentation
  鳥取市
- Year and Date
  2007-09-11
- Data Source
  KAKENHI-PROJECT-18080008
[Presentation] シストリックアーキテクチャに基づく高スループットSFQビットシリアル浮動小数点乗算器2007
- Author(s)
  小畑幸嗣、古田卓也、高木一義、高木直史
- Organizer
  電子情報通信学会エレクトロニクスソサイエティ大会
- Place of Presentation
  鳥取市
- Year and Date
  2007-09-11
- Data Source
  KAKENHI-PROJECT-18080008
[Presentation] ２つの浮動小数点積和演算器を用いた複素数乗算器
- Author(s)
  高田雄平、高木直史、高木一義
- Organizer
  デザインガイア2014（電子情報通信学会コンピュータシステム研究会）
- Place of Presentation
  別府市　ビーコンプラザ（別府国際コンベンションセンター）
- Year and Date
  2014-11-26 – 2014-11-28
- Data Source
  KAKENHI-PROJECT-24300019
[Presentation] 部分二重化を用いたオンライン誤り検出可能な浮動小数点乗算器の設計と評価
- Author(s)
  鬼頭信貴、秋元一志、高木直史
- Organizer
  ETNET2015（電子情報通信学会ディペンダブルコンピューティング研究会）
- Place of Presentation
  奄美市　奄美社会福祉協議会
- Year and Date
  2015-03-06 – 2015-03-07
- Data Source
  KAKENHI-PROJECT-24300019
[Presentation] ２つの浮動小数点倍精度加算器を用いた仮数部104ビット拡張倍精度加算器
- Author(s)
  矢高裕之、高木直史、高木一義
- Organizer
  デザインガイア2014（電子情報通信学会コンピュータシステム研究会）
- Place of Presentation
  別府市　ビーコンプラザ（別府国際コンベンションセンター）
- Year and Date
  2014-11-26 – 2014-11-28
- Data Source
  KAKENHI-PROJECT-24300019
[Presentation] 単一磁束量子回路向けの論理ゲート配置手法
- Author(s)
  西村翔, 高木一義, 高木直史
- Organizer
  2013年電子情報通信学会総合大会
- Place of Presentation
  岐阜大学
- Data Source
  KAKENHI-PROJECT-24500061

1. NAOFUMI Takagi (10171422)

# of Collaborated Projects: 7 results

# of Collaborated Products: 87 results
2. WATANABE Katsumasa (60026078)

# of Collaborated Projects: 4 results

# of Collaborated Products: 0 results
3. KIMURA Shinji (20183303)

# of Collaborated Projects: 4 results

# of Collaborated Products: 0 results
4. KUNISHIMA Takeo (20263436)

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
5. NAKAMURA Kazuhiro (90335076)

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
6. HORIYAMA Takashi (60314530)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
7. NAKANISHI Masaki (40324967)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
8. NISHINAGA Nozomu

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
9. 鬼頭信貴

# of Collaborated Projects: 0 results

# of Collaborated Products: 1 results

Takagi Kazuyoshi 高木 一義

TAKAGI Kazuyoshi 高木 一義

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Studies on Operation Timing Optimization of Superconducting Single-Flux-Quantum CircuitsPrincipal Investigator

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Researches on Testing and Reliable Design of Superconducting Rapid Single-Flux-Quantum CircuitsPrincipal Investigator

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Studies on Layout Design Methods for Logic Circuits using Superconducting DevicesPrincipal Investigator

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studies on high-reliability timing design methods for logic circuits using advanced devicesPrincipal Investigator

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Studies on Logic Design and Design Automation of Single-Flux-Quantum Circuits based on Localized Electromagnetic WavesPrincipal Investigator

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次世代集積回路設計のための決定グラフによる論理関数表現に関する研究Principal Investigator

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種々の決定グラフを用いた論理関数表現とその回路合成への応用に関する研究Principal Investigator

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Takagi Kazuyoshi 高木一義

TAKAGI Kazuyoshi 高木一義