KANEKO Mineo 金子峰雄

Researcher Number	00185935
Other IDs
Affiliation (based on the past Project Information) *help	2016 – 2023: 北陸先端科学技術大学院大学, 先端科学技術研究科, 教授 2014 – 2015: 北陸先端科学技術大学院大学, 情報科学研究科, 教授 2010 – 2012: 北陸先端科学技術大学院大学, 情報科学研究科, 教授 2007 – 2008: Japan Advanced Institute of Science and Technology, 情報科学研究科, 教授 2002 – 2005: Japan Advanced Institute of Science and Technology, School of Information Science, Professor, 情報科学研究科, 教授 … More 1997 – 2001: JAIST,School of Information Science, Associate Professor, 情報科学研究科, 助教授 1992: Tokyo Institute of Technology 1988 – 1989: 東京工業大学, 工学部, 講師 Less
Review Section/Research Field	Principal Investigator Electron device/Electronic equipment / System engineering / Basic Section 60040:Computer system-related / 電子デバイス・機器工学 Except Principal Investigator 情報通信工学 / 科学教育(含教育工学) / 電子通信系統工学 / Computer system/Network
Keywords	Principal Investigator 高位合成 / 集積回路 / VLSI / 資源割り当て / データパス合成 / ASIC / EDA / 配線遅延 / 信号伝搬遅延 / クロックスキュー … More / 製造ばらつき / 遅延変動 / データパス回路 / 制約グラフ / 同期式回路 / 線形モデル / 混合整数線形計画問題 / クロック分配 / 混合整数線形計画法 / 温度依存性 / 同期式デジタル回路 / 組合せ最適化 / ホールド条件 / セットアップ条件 / 遅延回路 / 温度特性 / 信号遅延 / Statistical delay analysis / Control skew / Asynchronous circuit / Clock signal / Datapath synthesis / 制御回路 / アプリケーション特化専用LSI / 遅延スキュー / 非同期データパス / 統計的遅延解析 / 制御スキュー / 非同期回路 / クロック信号 / Design automation / RTL architecture / Interconnection delay / Floorplan / Layout design / resource binding / Scheduling / VLSI design / RTレベルアーキテクチャ / 設計自動化 / RTLアーキテクチャ / フロアプラン / レイアウト設計 / スケジューリング / VLSI設計 / multiplication / diagnosis / fault detection / systolic array / parallel computation / multi-processor / error correction / reconfiguration / fault tolerance / ウエハ-スケール集積回路 / ウエハースケール集積回路 / 並列計算処理 / 故障診断 / 故障検出 / 集積回路システム / 多重化 / 故障検出・診断 / シストリックアレイ / 並列計算 / マルチプロセッサ / 誤り訂正 / 再構成 / 耐故障 / 製造歩留まり / 製造歩留り / 設計最適化 / デジタル回路 / 最適化 / セットアップ条件・ホールド条件 / 基盤バイアス / クロック周波数 / ILP / 順序彩色 / クロック・スキュー / タイミングばらつき / 製造後チューニング / PDE / PDE調整 / タイミングテスト / タイミング・スキュー / セットアップ・ホールド / 最小遅延補正 / 信号電播遅延 / 順序クロッキング / 資源割当 / 微細化 / 信号伝播遅延 / レジスタ割当 / データパス / 遅延ばらつき / CAD / 同型判定 / 高速計算法 / パイプライン実行 / 再構成可能システム / 計算構造 / VLSI計算 / 計算アルゴリズム / データフローグラフ / 高速算法 / 数値計算 … More Except Principal Investigator digital substrate noise / automatic analog circuit design / switched-capacitor amplifier / A-D converte / analog basic building block / 低歪み / 低消費電力 / OTA / スイッチトカレント回路 / 電圧平均回路 / アナログ集積回路 / Companding積分器 / 電圧フォロワ / スイッチトキャパシタ回路 / Rail-to-Rail OTA / 雑音 / 再利用 / 遺伝的アルゴリズム / 自動合成 / ディジタル基板雑音 / アナログ回路自動合成 / スイッチトキャパシタ増幅回路 / A-Dコンバータ / アナログ基本機能ブロック / key distribution mechanism / symmetric key cryptosystem / ciphertext / cryptosystem / decryption / encryption / 自己解凍 / 暗号プラットホーム / 情報セキュリティ / 暗号 / Scientific and technological text books for reading comprehenshion / Lecturs on science and technology in Japanese / Discourse analysis / Syntactic analysis / Particles equivalents / Frequency of c hinese characters / Vocabulary survey / Text data base of science and technology / CAI / 学習行動分析 / ニ-ズアナリシス / 頻度解析プログラム / デ-タベ-ス入力 / 専門日本語講義 / 形態素解析 / 理工系大学テキスト / ディスコーテ分析 / 科学技術文章読解教科書 / 科学技術日本語講義 / ディスコース分析 / 構文解析 / 助詞相当句 / 漢字頻度 / 語彙調査 / 理工系大学テキストデータベース / Hardware Algorithm / Processor Array / Parallel Signal Processing / VLSI ( Very Large Scale Integrated circuits ) / ハ-ドウエア・アルゴリズム / プロセッサ・アレイ / 並列信号処理 / VLSI / 命令コード生成 / マルチプロセッサシステム / 信号処理 / 非線形フィルタ / 画像信号 / 積和演算 / 命令コ-ド / シストリックアレイ / マルチプロセッサ / シグナルプロセッサ / ディジタルフィルタ / 2次元フィルタ / 画像信号処理 / インターネット配信 / 音楽ファイル / ライセンシング / 電子透かし / ハミング距離 / LSH / 音楽電子指紋 / インターネット / Staged LSH / ハッシュ / データベース / 音楽検索 / 電子指紋 / FPGA / リコンフィギャラブル Less

Study on Autonomous Timing Correction and Design Optimization for Next Generation LSI SystemsPrincipal Investigator
- Principal Investigator
  
  Kaneko Mineo
- Project Period (FY)
  2018 – 2023
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Japan Advanced Institute of Science and Technology
Theory and Design of Post-Silicon Multi-Way Tuning for New Generation LSI CircuitsPrincipal Investigator
- Principal Investigator
  
  Kaneko Mineo
- Project Period (FY)
  2014 – 2017
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  Japan Advanced Institute of Science and Technology
Ultra High Speed Audio Fingerprint Detection and Search
- Principal Investigator
  
  INOGUCHI Yasushi
- Project Period (FY)
  2012 – 2014
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Japan Advanced Institute of Science and Technology
Robustness against delay variations and design optimization for datapath circuits with post silicon timing tuning mechanismPrincipal Investigator
- Principal Investigator
  
  KANEKO Mineo
- Project Period (FY)
  2010 – 2012
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  Japan Advanced Institute of Science and Technology
Theory and Optimization of Reliable Datapath Circuits having Robustness against Delay VariationPrincipal Investigator
- Principal Investigator
  
  KANEKO Mineo
- Project Period (FY)
  2007 – 2008
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  Japan Advanced Institute of Science and Technology
Theory and Design Method of Clock-less Datapath for Next Generation VLSIsPrincipal Investigator
- Principal Investigator
  
  KANEKO Mineo
- Project Period (FY)
  2004 – 2005
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Electron device/Electronic equipment
- Research Institution
  Japan Advanced Institute of Science and Technology
Three Dimensional Dapapath Synthesis for Nanotechnology VLSIsPrincipal Investigator
- Principal Investigator
  
  KANEKO Mineo
- Project Period (FY)
  2002 – 2003
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  電子デバイス・機器工学
- Research Institution
  Japan Advanced Institute of Science and Technology
超大規模計算の高速算法自動合成の理論Principal Investigator
- Principal Investigator
  
  金子峰雄
- Project Period (FY)
  1999 – 2001
- Research Category
  
  Grant-in-Aid for Exploratory Research
- Research Field
  
  System engineering
- Research Institution
  Japan Advanced Institute of Science and Technology
Design System for Next-Generation High-Performance Analog Integrated Circuits
- Principal Investigator
  
  FUJII Nobuo
- Project Period (FY)
  1999 – 2002
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  情報通信工学
- Research Institution
  Tokyo Institute of Technology
Theory and design of fault tolerant integrated systemsPrincipal Investigator
- Principal Investigator
  
  KANEKO Mineo
- Project Period (FY)
  1997 – 1999
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  System engineering
- Research Institution
  Japan Advanced Institute of Science and Technology
Research of Self-protection Mechanism for Information
- Principal Investigator
  
  OKAMOTO Eiji
- Project Period (FY)
  1995 – 1997
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  情報通信工学
- Research Institution
  Japan Advanced Institute of Science and Technology (JAIST)
Development of Japanese textbooks for Science and Technology
- Principal Investigator
  
  NISHINA Kikuko
- Project Period (FY)
  1990 – 1992
- Research Category
  
  Grant-in-Aid for Developmental Scientific Research (B)
- Research Field
  
  科学教育(含教育工学)
- Research Institution
  Education Center for Foreign Student;Tokyo Institute of Technology
Performance and Software Design of Signal Processing Hardwares
- Principal Investigator
  
  ONODA Mahoki
- Project Period (FY)
  1989
- Research Category
  
  Grant-in-Aid for Overseas Scientific Survey.
- Research Institution
  Tokyo Institute of Technology
二次元画像信号フィルタリグの高精度化・高速化に関する基礎的研究
- Principal Investigator
  
  ONODA Mahoki
- Project Period (FY)
  1988 – 1989
- Research Category
  
  Grant-in-Aid for General Scientific Research (C)
- Research Field
  
  電子通信系統工学
- Research Institution
  Tokyo Institute of Technology

[Journal Article] タイミング調整に優れたデータパス回路のための高位合成手法2024
- Author(s)
  金子峰雄
- Journal Title
  
  電子情報通信学会 VLSI設計技術研究会技術報告
  
  Volume: VLD2023-101 Pages: 12-17
- Data Source
  KAKENHI-PROJECT-18K11211
[Journal Article] 資源割当と遅延量分布の関係を考慮したスキュー調整型高位合成2023
- Author(s)
  金子峰雄
- Journal Title
  
  電子情報通信学会 VLSI設計技術研究会技術報告
  
  Volume: VLD2022-89 Pages: 97-102
- Data Source
  KAKENHI-PROJECT-18K11211
[Journal Article] 温度依存タイミングスキューを考慮したデータパス高位合成手法2022
- Author(s)
  金子峰雄
- Journal Title
  
  電子情報通信学会 VLSI設計技術研究会技術報告
  
  Volume: VLD2021-79 Pages: 19-24
- Data Source
  KAKENHI-PROJECT-18K11211
[Journal Article] ばらつきと戦う集積回路設計―仕掛けと最適化―2021
- Author(s)
  金子峰雄
- Journal Title
  
  電子情報通信学会CAS研究会技術報告
  
  Volume: CAS2020-76 Pages: 23-28
- Data Source
  KAKENHI-PROJECT-18K11211
[Journal Article] ２グラフ制約表現による温度依存クロック・スキュースケジュール2020
- Author(s)
  金子峰雄
- Journal Title
  
  電子情報通信学会 VLSI設計技術研究会技術報告
  
  Volume: VLD2019-104 Pages: 59-64
- Data Source
  KAKENHI-PROJECT-18K11211
[Journal Article] Two-Graph Approach to Temperature Dependent Skew Scheduling2020
- Author(s)
  Mineo Kaneko
- Journal Title
  
  Proceedings of International Symposium on Quality Electronic Design
  
  Volume: ISQED2020 Pages: 432-437
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18K11211
[Journal Article] Insertion-Based Procedural Construction and Optimization of Parallel Prefix Adders2020
- Author(s)
  Mineo Kaneko
- Journal Title
  
  Proceedings of IEEE International Symposium on Circuits and Systems
  
  Volume: ISCAS2020 Pages: 1-5
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-18K11211
[Journal Article] 制限付温度依存クロックスキューによるタイミング補正2019
- Author(s)
  金子峰雄
- Journal Title
  
  電子情報通信学会ＶＬＳＩ設計技術研究会技術報告
  
  Volume: VLD2018-103 Pages: 61-66
- Data Source
  KAKENHI-PROJECT-18K11211
[Journal Article] Register Binding in Datapath Synthesis Considering Post-Silicon Skew Tunability2018
- Author(s)
  Kazuho Katsumata, Junghoon Oh, Mineo Kaneko
- Journal Title
  
  Proceedings of the Workshop on Synthesis And System Integration of Mixed Information Technologies
  
  Volume: SASIMI2018 Pages: 232-237
- Data Source
  KAKENHI-PROJECT-26420303
[Journal Article] Margin Aware Timing Test and Tuning Algorithm for Post-Silicon Skew Tuning2017
- Author(s)
  Mineo Kaneko
- Journal Title
  
  Proceedings of IEEE 60th International Widwest Symposium on Circuits and Systems
  
  Volume: MWSCAS2017 Pages: 1244-1247
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-26420303
[Journal Article] 回路動作温度範囲に対する最適スキュー温度特性2017
- Author(s)
  曽我慎, 金子峰雄
- Journal Title
  
  電子情報通信学会VLSI設計技術研究会技術報告
  
  Volume: VLD2016 Pages: 91-96
- Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-26420303
[Journal Article] スキュー調整を考慮した高位合成のMILP定式化2017
- Author(s)
  志村甲斐, 金子峰雄
- Journal Title
  
  電子情報通信学会VLSI設計技術研究会技術報告
  
  Volume: VLD2016 Pages: 97-102
- Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-26420303
[Journal Article] A General Model of Timing Correction by Temperature Dependent Clock Skew2017
- Author(s)
  Mineo Kaneko
- Journal Title
  
  IEICE Technical report on VLSI Design Technology
  
  Volume: VLD2017 Pages: 183-188
- Data Source
  KAKENHI-PROJECT-26420303
[Journal Article] マルチ・ドメイン・スキュー割り当てを考慮した資源割り当てとドメイン分割2017
- Author(s)
  李暁光, 金子峰雄
- Journal Title
  
  電子情報通信学会VLSI設計技術研究会技術報告
  
  Volume: VLD2016 Pages: 85-90
- Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-26420303
[Journal Article] Optimization of Temperature Dependent Intentional Skew for Temperature Aware Timing Design2016
- Author(s)
  Makoto Soga, Mineo Kaneko
- Journal Title
  
  Proceedings of 20th Workshop on Synthesis and System Integration of Mixed Information Technologies
  
  Volume: - Pages: 119-124
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-26420303
[Journal Article] A Novel Framework for Temperature Dependence Aware Clock Skew Scheduling2015
- Author(s)
  Mineo Kaneko
- Journal Title
  
  Proceedings of ACM Great Lakes Symposium on VLSI
  
  Volume: 2015 Pages: 367-372
- Peer Reviewed / Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-26420303
[Journal Article] 製造後スキュー調整による動作速度最大化のためのデータパス資源割り当て2015
- Author(s)
  勝又一穂, 金子峰雄
- Journal Title
  
  電子情報通信学会VLSI設計技術研究会技術報告
  
  Volume: VLD2015 Pages: 173-178
- Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-26420303
[Journal Article] Timing-Test Scheduling for PDE Tuning Considering Multiple-Path Testability2014
- Author(s)
  金子峰雄
- Journal Title
  
  電子情報通信学会信学技報
  
  Volume: VLS2014-94 Pages: 149-154
- NAID
  110009971340
- Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-26420303
[Journal Article] Timing-Test Scheduling for Constraint-Graph Based Post-Silicon Skew Tuning2012
- Author(s)
  Mineo Kaneko
- Journal Title
  
  Proceedings of IEEE International Conference on Computer Design
  
  Volume: - Pages: 460-465
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22560326
[Journal Article] Optimal Register-Type Selection during Resource Binding in Flip-Flop/Latch-Based High-Level Synthesis2012
- Author(s)
  Keisuke Inoue, Mineo Kaneko
- Journal Title
  
  Proceedings of ACM/IEEE Great Lakes Symposium on VLSI
  
  Volume: - Pages: 79-82
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22560326
[Journal Article] Statistical Timing-Yield Driven Scheduling and FU Binding in Latch-Based Datapath Synthesis2012
- Author(s)
  Keisuke Inoue, Mineo Kaneko
- Journal Title
  
  Proceedings of IEEE Mid-West Symposium on Circuits and Systems
  
  Volume: - Pages: 631-634
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22560326
[Journal Article] Reliable and Low-Power Clock Distribution Using Pre- and Post-Silicon Delay Adaptation in High-Level Synthesis2012
- Author(s)
  Keisuke Inoue, Mineo Kaneko
- Journal Title
  
  Proceedings of IEEE International Symposium on Circuits and Systems
  
  Volume: - Pages: 1664-1667
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22560326
[Journal Article] Performance-Driven Register Write Inhibition in High-Level Synthesis under Strict Maximum-Permissible Clock Latency Range2012
- Author(s)
  Keisuke Inoue, Mineo Kaneko
- Journal Title
  
  Proceedings of 17th Asia-South-Pacific Design Automation Conference
  
  Pages: 239-244
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22560326
[Journal Article] Post-Silicon Skew Tuning Algorithm Utilizing Setup and Hold Timing Tests2012
- Author(s)
  Mineo Kaneko, Li Jiang
- Journal Title
  
  Proceedings of IEEE International Symposium on Circuits and Systems
  
  Volume: - Pages: 125-128
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22560326
[Journal Article] Register Binding and Domain Assignment for Multi-Domain Clock Skew Scheduling-Aware High-Level Synthesis2012
- Author(s)
  Keisuke Inoue, Mineo Kaneko
- Journal Title
  
  Proceedings of International Symposium on Quality Electronic Design
  
  Pages: 778-783
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22560326
[Journal Article] A Formal Approach to Optimal Register Binding with Ordered Clocking for Clock-Skew Tolerant Datapaths2012
- Author(s)
  Keisuke Inoue, Mineo Kaneko
- Journal Title
  
  EICE Trans. Fundamentals
  
  Volume: Vol.E95-A, No.12 Pages: 2330-2337
- NAID
  10031161367
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22560326
[Journal Article] A Formal Approach to Optimal Register Binding with Ordered Clocking for Clock-Skew Tolerant Datapaths2012
- Author(s)
  Keisuke Inoue, Mineo Kaneko
- Journal Title
  
  IEICE Trans. Fundamentals
  
  Volume: E95-A Pages: 2330-2337
- NAID
  10031161367
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22560326
[Journal Article] Variable-Duty-Cycle Scheduling in Double-Edge-Triggered Flip-Flop-Based High-Level Synthesis2011
- Author(s)
  Keisuke Inoue, Mineo Kaneko
- Journal Title
  
  Proceedings of IEEE International Symposium on Circuits and Systems
  
  Pages: 550-553
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22560326
[Journal Article] Ordered Coloring-Based Resource Binding for Datapaths with Improved Skew-Adjustability2011
- Author(s)
  Mineo Kaneko, Keisuke Inoue
- Journal Title
  
  Proceedings of ACM Great Lakes Symposium on VLSI
  
  Pages: 307-312
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22560326
[Journal Article] Flexible Test Scheduling for an Asynchronous On-chip Interconnect Through Special Data Transfer2011
- Author(s)
  Tsuyoshi Iwagaki, Eiri Takeda, Mineo Kaneko
- Journal Title
  
  IEICE Trans. Fundamentals
  
  Volume: Vol. E94-A, No. 12 Pages: 2563-2570
- NAID
  10030533654
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22560326
[Journal Article] Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis2011
- Author(s)
  Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
- Journal Title
  
  IEICE Transactions on Fundamentals
  
  Volume: Vol.E94-A Pages: 1067-1081
- NAID
  10029503424
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22560326
[Journal Article] Backward Data Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis2011
- Author(s)
  Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
- Journal Title
  
  IEICE Trans. Fundamentals
  
  Volume: Vol.E94-A, No.4 Pages: 1067-1081
- NAID
  10029503424
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22560326
[Journal Article] Early Planning for RT-Level Delay Insertion during Clock Skew Aware Register Binding2011
- Author(s)
  Keisuke Inoue, Mineo Kaneko
- Journal Title
  
  Proceedings of IFIP/IEEE International Conference on Very Large Scale Integration and System-on-Chip
  
  Pages: 154-159
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22560326
[Journal Article] A Complete Framework of Simultaneous Functional Unit and Register Binding with Skew Scheduling2011
- Author(s)
  Mineo Kaneko
- Journal Title
  
  Proceedings of International Symposium on Quality Electronic Design
  
  Pages: 189-195
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22560326
[Journal Article] peration Scheduling Considering Time Borrowing for High-Performance Latch-Based Circuits2011
- Author(s)
  Keisuke Inoue, Mineo Kaneko
- Journal Title
  
  Proceedings of 9th IEEE International NEW Circuits and System Conference
  
  Pages: 245-248
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22560326
[Journal Article] Framework for Latch-Based High-Level Synthesis using Minimum-Delay Compensation2011
- Author(s)
  Keisuke Inoue, Mineo Kaneko
- Journal Title
  
  IPSJ Transactions on System LSI Design Methodology
  
  Volume: Vol. 4 Pages: 232-244
- NAID
  130002073517
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22560326
[Journal Article] ILP Approach to Extended Ordered Coloring for Skew Adjustability-Aware Resource Binding2010
- Author(s)
  Mineo Kaneko
- Journal Title
  
  電子情報通信学会VLSI設計技術研究会技術報告
  
  Volume: VLD2010-75 Pages: 131-136
- NAID
  110008152357
- Data Source
  KAKENHI-PROJECT-22560326
[Journal Article] 速度性能とタイミングスキュー調整特性に優れたデータパスの合成手法2010
- Author(s)
  党羽, 金子峰雄
- Journal Title
  
  電子情報通信学会VLSI設計技術研究会技術報告
  
  Volume: VLD2010-133 Pages: 99-104
- NAID
  110008689550
- Data Source
  KAKENHI-PROJECT-22560326
[Journal Article] Ordered Coloring for Skew Adjustability-Aware Resource Binding2010
- Author(s)
  Mineo Kaneko
- Journal Title
  
  電子情報通信学会VLSIgx計技術研究会技術報告
  
  Volume: VLS2010-42 Pages: 1-6
- NAID
  110008107081
- Data Source
  KAKENHI-PROJECT-22560326
[Journal Article] A Conjecture on the Number of Extra Registers in Safe Clocking-Based Register Assignment2009
- Author(s)
  Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
- Journal Title
  
  The 15th Workshop on Synthesis And System Integration of Mixed Information technology
  
  Pages: 131-136
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19560340
[Journal Article] Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths2009
- Author(s)
  Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
- Journal Title
  
  IEICE Transactions on Fundamentals Vol. E92-A, No. 4
  
  Pages: 1096-1105
- NAID
  10026857065
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19560340
[Journal Article] Safe Clocking for the Setup and Hold Timing Constraints in Datapath Synthesis2009
- Author(s)
  Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
- Journal Title
  
  Proceedings of ACM Great Lakes Symposium on VLSI
  
  Pages: 27-32
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19560340
[Journal Article] Solvability of Simultaneous Control Step and Timing Skew Assignments in High Level Synthesis2009
- Author(s)
  Takayuki Obata, Mineo Kaneko
- Journal Title
  
  Proceedings of IEEE International Symposium on Circuits and Systems
  
  Pages: 1521-1524
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19560340
[Journal Article] Optimal Resigster Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths2009
- Author(s)
  Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
- Journal Title
  
  IEICE Trans. Fundamentals E92-A
  
  Pages: 1096-1105
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19560340
[Journal Article] Concurrent Skew and Control Step Assignments in RT-Level Datapath Synthesis2008
- Author(s)
  Takayuki Obata, Mineo Kaneko
- Journal Title
  
  Proceedings of IEEE International Symposium on Circuits and Systems
  
  Pages: 2018-2021
- NAID
  120006674337
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19560340
[Journal Article] Simultaneous Optimization of Skew and Control Step Assignment in RT-Datapath Synthesis2008
- Author(s)
  Takayuki Obata, Mineo Kaneko
- Journal Title
  
  IEICE Trans. Fundamentals E92-A
  
  Pages: 3585-3595
- NAID
  10026854071
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19560340
[Journal Article] データパス合成における最小遅延補正演算器数の最小化手法2008
- Author(s)
  Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
- Journal Title
  
  電子情報通信学会技術報告VLSI設計技術研究会 VLD2007-140
  
  Pages: 19-24
- NAID
  110006885191
- Data Source
  KAKENHI-PROJECT-19560340
[Journal Article] A Conjecture on the Number of Extra Registers in Safe Clocking-Based Register Assignment2008
- Author(s)
  Keisuke Inoue, MineoKaneko, Tsuyoshi Iwagaki
- Journal Title
  
  The 15th Workshop on Synthesis And System Integration of Mixed Information technology
  
  Pages: 131-136
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19560340
[Journal Article] Safe Clocking Register Assignment in Datapath Synthesis2008
- Author(s)
  Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
- Journal Title
  
  Proceedings of IEEE International Conference on Computer Design
  
  Pages: 120-127
- NAID
  120006674352
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19560340
[Journal Article] Novel Register Sharing in Datapath for Structural Robustness against Delay Variation2008
- Author(s)
  Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
- Journal Title
  
  IEICE Trans. Fundamentals E91-A
  
  Pages: 1044-1053
- NAID
  10026848623
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19560340
[Journal Article] Novel Register Sharing in Datapath for Structural Robustness against Delay Variation2008
- Author(s)
  Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
- Journal Title
  
  IEICE Transactions on Fundamentals Vol. E91-A, No. 4
  
  Pages: 1044-1053
- NAID
  10026848623
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19560340
[Journal Article] Novel Register Sharing in Datapath for Structural Robustness against Delay Variation2008
- Author(s)
  Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
- Journal Title
  
  IEICE Transactions on Fundamentals E91-A
  
  Pages: 1044-1053
- NAID
  10026848623
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19560340
[Journal Article] データパス合成における最小遅延補正演算器数の最小化手法2008
- Author(s)
  井上恵介, 金子峰雄, 岩垣剛
- Journal Title
  
  電子情報通信学会回路とシステム軽井沢ワークショップ論文集
  
  Pages: 623-628
- NAID
  110006885191
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19560340
[Journal Article] Safe Clocking Register Assignment in Datapath Synthesis2008
- Author(s)
  Keisuke Inoue, MineoKaneko, Tsuyoshi Iwagaki
- Journal Title
  
  Proceedings of IEEE InternationalConference on Computer Design
  
  Pages: 120-127
- NAID
  120006674352
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19560340
[Journal Article] Minimizing Minimum Delay Compensations for Timing Variation-Aware Datapath Synthesis2008
- Author(s)
  Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
- Journal Title
  
  Proceedings of IEEE Midwest Symposium on Circuits and Systems
  
  Pages: 97-100
- NAID
  120006674351
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19560340
[Journal Article] Minimizing Minimum Delay Compensations for Timing Variation-Aware Datapaths Synthesis2008
- Author(s)
  Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
- Journal Title
  
  Proceedings of IEEE Midwest Symposium on Circuits and Systems
  
  Pages: 97-100
- NAID
  120006674351
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19560340
[Journal Article] Rescheduling with Skew Optimization in RT-Datapath Synthesis2007
- Author(s)
  Takayuki Obata, Mineo Kaneko
- Journal Title
  
  電子情報通信学会技術報告回路とシステム研究会 CAS2007-24
  
  Pages: 31-36
- NAID
  110006343384
- Data Source
  KAKENHI-PROJECT-19560340
[Journal Article] Computational Complexity of Simultaneous Optimization of Skew, Schedule and Clock in High-Level Synthesis2007
- Author(s)
  Takayuki Obata, Mineo Kaneko
- Journal Title
  
  IEICE Technical report (to appear)
- NAID
  110006202404
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] A Schedule Improvement with Skew Control in Datapath Synthesis2007
- Author(s)
  Takayuki Obata, Mineo Kaneko
- Journal Title
  
  電子情報通信学会技術報告VLSI設計技術研究会 VLD2007-94
  
  Pages: 31-36
- NAID
  110006533277
- Data Source
  KAKENHI-PROJECT-19560340
[Journal Article] Extended Register-Sharing in the Synthesis of Dual-Rail Two-Phase Asynchronous Datapath2007
- Author(s)
  Koji Ohashi, Mineo Kaneko
- Journal Title
  
  Proceedings of GLSVLSI2007 (印刷中)
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Computational Complexity of Simultaneous Optimization of Skew, Schedule and Clock in High-Level Synthesis2007
- Author(s)
  Takayuki Obata, Mineo Kaneko
- Journal Title
  
  電子情報通信学会技術報告 (印刷中)
- NAID
  110006202404
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Extended Register-Sharing in the Synthesis of Dual-Rail Two-Phase Asynchronous Datapath2007
- Author(s)
  Koji Ohashi, Mineo Kaneko
- Journal Title
  
  Proceedings of GLSVLSI2007 (accepted)
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Complexities and Algorithms of Minmum-Delay Compensation Problems in Datapath Synthesis2007
- Author(s)
  Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
- Journal Title
  
  電子情報通信学会技術報告VLSI設計技術研究会 VLD2007-93
  
  Pages: 25-30
- Data Source
  KAKENHI-PROJECT-19560340
[Journal Article] Structural Robustness of Datapaths against Delay-Variations2007
- Author(s)
  Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
- Journal Title
  
  Proceedings of the 14th Workshop on Synthesis and System Integration of Mixed Information Technology
  
  Pages: 272-279
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19560340
[Journal Article] Minimal Set of Essential Resource Disjoint Pairs for Exploring Feasible 3D Schedules2006
- Author(s)
  Mineo Kaneko
- Journal Title
  
  Proceedings of IEEE Asia Pacific Conference on Circuits and Systems
  
  Pages: 335-338
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Simultaneous Control-step and Skew Assignment for Control Signals in RT-Level Datapath Synthesis2006
- Author(s)
  Takayuki Obata, Mineo Kaneko
- Journal Title
  
  IEICE Technical Report CAS2005-92
  
  Pages: 31-36
- NAID
  110004082732
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Minimal Set of Essential Resource Disjoint Pairs for Exploring Feasible 3D Schedules2006
- Author(s)
  Mineo Kaneko
- Journal Title
  
  Proceedings of IEEE Asia Pacific Conference on Circuits and Systems (CD-ROM) ISBN:1-4244-0387-1
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Analysis and Optimization of Statistical Performance for Asynchronous Datapaths2006
- Author(s)
  Koji Ohashi, Mineo Kaneko
- Journal Title
  
  WSEAS Transactions on Circuits and Systems Vol.5, No.7
  
  Pages: 895-902
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Dual-Rail Two-Phase Asynchronous Datapath Synthesis Based on Aggressive Register Sharing Model2006
- Author(s)
  Koji Ohashi, Mineo Kaneko
- Journal Title
  
  IEICE Proceedings of 19th Circuits and System Karuizawa Workshop
  
  Pages: 589-594
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Dual-Rail Two-Phase Asynchronous Datapath Synthesis Based on Aggressive Register Sharing Model2006
- Author(s)
  Koji Ohashi, Mineo Kaneko
- Journal Title
  
  第19回回路とシステム軽井沢ワークショップ論文集
  
  Pages: 589-594
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Statistical Makespan Analysis in Asynchronous Datapath Synthesis2006
- Author(s)
  Koji Ohashi, Mineo Kaneko
- Journal Title
  
  Proceedings of the 10th WSEAS International Conference on Circuits (CD-ROM) ISBN:960-8457-47-5
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Computational Complexity of Simultaneous Optimization of Control Schedule and Skew in Datapath Synthesis2006
- Author(s)
  Takayuki Obata, Mineo Kaneko
- Journal Title
  
  電子情報通信学会技術報告 VLD2006-65
  
  Pages: 83-88
- NAID
  110005717342
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Analysis and Optimization of Statistical Performance for Asynchronous Datapaths2006
- Author(s)
  Koji Ohashi, Mineko Kaneko
- Journal Title
  
  WSEAS Transactions on Circuits and Systems 5・7
  
  Pages: 895-902
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Simultaneous Control-Step and Skew Assignment for Control Signals in RT-Level Datapath Synthesis2006
- Author(s)
  Takayuki Obata, Mineo Kaneko
- Journal Title
  
  Proc.of Workshop on Synthesis And System Integration on Mixed Information Technologies
  
  Pages: 314-321
- NAID
  110004082732
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Simultaneous Control-step and Skew Assignment for Control Signals in RT-Level Datapath Synthesis2006
- Author(s)
  Takayuki Obata, Mineo Kaneko
- Journal Title
  
  Proceedings of the Workshop on Synthesis And System Integration of Mixed Information Technologies SASIMI2006
  
  Pages: 314-321
- NAID
  110004082732
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Simultaneous Control-Step and Skew Assignment for Control Signals in RT-Level Datapath Synthesis2006
- Author(s)
  Takayuki Obata, Mineo Kaneko
- Journal Title
  
  電子情報通信学会技術報告 CAS2005-92
  
  Pages: 31-36
- NAID
  110004082732
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Simultaneous Control-step and Skew Assignment for Control Signals in RT-Level Datapath Synthesis2006
- Author(s)
  Takayuki Obata, Mineo Kaneko
- Journal Title
  
  Proc. of the Workshop on Synthesis And System Integration of Mixed Information Technologies
  
  Pages: 314-321
- NAID
  110004082732
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Resource Sharing in Dual-Rail Two-Phase Asynchronous Datapath Synthesis2006
- Author(s)
  Koji Ohashi, Mineo Kaneko
- Journal Title
  
  電子情報通信学会技術報告 CAS2005-93
  
  Pages: 37-42
- NAID
  110004082733
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Statistical Makespan Analysis in Asynchronous Datapath Synthesis2006
- Author(s)
  Koji Ohashi, Mineo Kaneko
- Journal Title
  
  Proceedings of the 10th WSEAS International Conference on Circuits
  
  Pages: 318-323
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Resource Sharing in Dual-Rail Two-Phase Asynchronous Datapath Synthesis2006
- Author(s)
  Koji Ohashi, Mineo Kaneko
- Journal Title
  
  IEICE Technical Report CAS2005-93
  
  Pages: 37-42
- NAID
  110004082733
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Computational Complexity of Simultaneous Optimization of Control Schedule and Skew in Datapath Synthesis2006
- Author(s)
  Takayuki Obata, Mineo Kaneko
- Journal Title
  
  IEICE Technical report VLD2006-65, DC2006-52
  
  Pages: 83-88
- NAID
  110005717342
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Dual-Rail Two-Phase Asynchronous Datapath Synthesis Based on Aggressive Register Sharing Model2006
- Author(s)
  Koji Ohashi, Mineo Kaneko
- Journal Title
  
  IEICE 回路とシステム軽井沢ワークショップ論文集
  
  Pages: 589-594
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Control Signal Skew Scheduling in Rt Level Datapath Synthesis2005
- Author(s)
  Takayuki Obata, Mineo Kaneko
- Journal Title
  
  Proc. of IEEE International Midwest Symposium on Circuits and Systems (CD-ROM)
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Control Signal Skew Scheduling for RT Level Datapaths2005
- Author(s)
  Takayuki Obata, Mineo Kaneko
- Journal Title
  
  IEICE 回路とシステム軽井沢ワークショップ論文集
  
  Pages: 521-526
- NAID
  10015530975
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Simultaneous Schedule and Skew Assignment for Multiplexer Control in Placed Datapaths2005
- Author(s)
  Takayuki Obata, Mineo Kaneko
- Journal Title
  
  IEICE Technical Report CAS2004-74
  
  Pages: 13-18
- NAID
  110003206061
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Control Signal Skew Scheduling for RT Level Datapaths2005
- Author(s)
  Takayuki Obata, Mineo Kaneko
- Journal Title
  
  電子情報通信学会コンピュータシステム研究会技術報告 CPSY2004-107
  
  Pages: 13-17
- NAID
  10015530975
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Statistical Analysis Driven Synthesis of Asynchronous Systems2005
- Author(s)
  Koji Ohashi, Mineko Kaneko
- Journal Title
  
  Proc. of International Conference on Computer Design
  
  Pages: 200-205
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Minimal Set of Essential Lifetime Overlaps for Exploring 3D Schedule2005
- Author(s)
  Mineo Kaneko
- Journal Title
  
  電子情報通信学会技術報告 VLD2005-64
  
  Pages: 19-24
- NAID
  110004018523
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Simultaneous Schedule and Skew Assignment for Multiplexer Control in Placed Datapaths2005
- Author(s)
  Takayuki Obata, Mineo kaneko
- Journal Title
  
  電子情報通信学会回路とシステム研究会技術報告 CAS2004-74
  
  Pages: 13-18
- NAID
  110003206061
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] A Finite Solution Space for Recurrent Placements2005
- Author(s)
  Mineo Kaneko, Tomoyuki Ogawa
- Journal Title
  
  電子情報通信学会回路とシステム研究会技術報告 CAS2004-73
  
  Pages: 7-12
- NAID
  110003206060
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Control Signal Skew Scheduling in RT Level Datapath Synthesis2005
- Author(s)
  Takayuki Obata, Mineo Kaneko
- Journal Title
  
  Proc.of IEEE International Midwest Symposium on Circuits and Systems (CD-ROM)
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Minimal Set of Essential Lifetime Overlaps for Exploring 3D Schedule2005
- Author(s)
  Mineo Kaneko
- Journal Title
  
  IEICE Technical Report VLD2005-64, ICD2005-159, DC2005-41
  
  Pages: 19-24
- NAID
  110004018523
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Statistical Scheduling Length Analysis in Asynchronous Datapath Synthesis2005
- Author(s)
  Koji Ohashi, Mineo Kaneko
- Journal Title
  
  IEICE Technical Report CAS2004-72
  
  Pages: 1-6
- NAID
  110003206059
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Statistical Scheduling Length Analysis In Asynchronous Datapath Synthesis2005
- Author(s)
  Koji Ohashi, Mineko Kaneko
- Journal Title
  
  Proc. of IEEE International Symposium on Circuits and Systems
  
  Pages: 700-703
- NAID
  110003206059
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Minimal Set of Essential Lifetime Overlaps for Exploring 3D Schedule2005
- Author(s)
  Mineo Kaneko
- Journal Title
  
  IEICE Technical Report VLD2005-64
  
  Pages: 19-24
- NAID
  110004018523
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Control Signal Skew Scheduling for RT Level Datapaths2005
- Author(s)
  Takayuki Oata, Mineo Kaneko
- Journal Title
  
  第18回回路とシステム軽井沢ワークショップ論文集
  
  Pages: 521-526
- NAID
  10015530975
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Statistical Schedule Length Analysis in Asynchronous Datapath Synthesis2005
- Author(s)
  Koji Ohashi, Mineo Kaneko
- Journal Title
  
  電子情報通信学会回路とシステム研究会技術報告 CAS2004-72
  
  Pages: 1-6
- NAID
  110003206059
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Simultaneous Scheduling and Binding for Asynchronous System with Statistical Makespan Analysis2005
- Author(s)
  Koji Ohashi, Mineo Kaneko
- Journal Title
  
  第18回回路とシステム軽井沢ワークショップ論文集
  
  Pages: 587-592
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Control Signal Skew Scheduling for RT Level Datapaths2005
- Author(s)
  Takayuki Obata, Mineo Kaneko
- Journal Title
  
  IEICE Technical Report CPSY2004-107
  
  Pages: 13-17
- NAID
  10015530975
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Simultaneous Scheduling and Binding for Asynchronous System with Statistical Makespan Analysis2005
- Author(s)
  Koji Ohashi, Mineo Kaneko
- Journal Title
  
  IEICE Proceedings of 18th Circuits and System Karuizawa Workshop
  
  Pages: 587-592
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Statistical Scheduling Length Analysis in Asynchronous Datapath Synthesis2005
- Author(s)
  Koji Ohashi, Mineo Kaneko
- Journal Title
  
  Proc.of IEEE International Symposium on Circuits and Systems
  
  Pages: 700-703
- NAID
  110003206059
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Statistical Scheduling Length Analysis In Asynchronous Datapath Synthesis2005
- Author(s)
  Koji Ohashi, Mineo Kaneko
- Journal Title
  
  Proc.of IEEE International Symposium on Circuits and Systems
  
  Pages: 700-703
- NAID
  110003206059
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Control Signal Skew Scheduling for RT Level Datapaths2005
- Author(s)
  Takayuki Obata, Mineo Kaneko
- Journal Title
  
  IEICE Proceedings of 18th Circuits and System Karuizawa Workshop
  
  Pages: 521-526
- NAID
  10015530975
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Simultaneous Scheduling and Binding for Asynchronous System with Statistical Makespan Analysis2005
- Author(s)
  Koji Ohashi, Mineo Kaneko
- Journal Title
  
  IEICE 回路とシステム軽井沢ワークショップ論文集
  
  Pages: 587-592
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Control Signal Skew Scheduling in RT Level Datapath Synthesis2005
- Author(s)
  Takayuki Obata, Mineo Kaneko
- Journal Title
  
  Proc.of IEEE International Midwest Symposium on Circuits and Systems (CD-ROM) ISBN:0-7803-9198-5
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Statistical Analysis Driven Synthesis of Asynchronous Systems2005
- Author(s)
  Koji Ohashi, Mineo Kaneko
- Journal Title
  
  Proc.of International Conference on Computer Design
  
  Pages: 200-205
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Asynchronous Datapath Synthesis Enhancing Graceful Graceful Degradation for Delay Faults2004
- Author(s)
  Koji Ohashi, Mineo Kaneko
- Journal Title
  
  Proceedings of the Workshop on Synthesis and System Integration of Mixed Information Technologies
  
  Pages: 303-309
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Assignment Constrained Scheduling under Max/Min Logic/Interconnect Delays for Placed Datapath2004
- Author(s)
  Mineo Kaneko, Koji Ohashi
- Journal Title
  
  Proc.IEEE Asia-Pacific Conference on Circuits and Systems Vol.1
  
  Pages: 545-548
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Assignment Constrained Scheduling under Max / Min Logic / Interconnect Delays for Placed Datapath2004
- Author(s)
  Mineko Kaneko, Koji Ohashi
- Journal Title
  
  Proc. IEEE Asia--Pacific Conference on Circuits and Systems 1
  
  Pages: 545-548
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Asynchronous Datapath Synthesis Based on Binding Space Exploration2004
- Author(s)
  Koji Ohashi, Mineo Kaneko
- Journal Title
  
  Proceedings of the 17th Workshop on Circuits and Systems in Karuizawa
  
  Pages: 549-554
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-14550321
[Journal Article] Asynchronous Datapath Synthesis Enhancing Graceful Degradation for Delay Faults2004
- Author(s)
  Koji Ohashi, Mineo Kaneko
- Journal Title
  
  Proc.of the Workshop on Synthesis and System Integration of Mixed Information Technologies
  
  Pages: 303-309
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Assignment Constrained Scheduling Under Max/Min Logic/ Interconnect Delays for Placed Datapath2004
- Author(s)
  Mineo kaneko, Koji Ohashi
- Journal Title
  
  Proceedings of the 2004 IEEE Asia-Pacific Conference on Circuits and Systems
  
  Pages: 545-548
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Asynchronous Datapath Synthesis Enhancing Graceful Degradation for Delay Faults2004
- Author(s)
  Koji Ohashi, Mineko Kaneko
- Journal Title
  
  Proc. of the Workshop on Synthesis and System Integration of Mixed Information Technologies
  
  Pages: 303-309
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Asynchronous Datapath Synthesis Based on Binding Space Exploration2004
- Author(s)
  Koji Ohashi, Mineo Kaneko
- Journal Title
  
  電子情報通信学会第17回回路とシステム軽井沢ワークショップ論文集
  
  Pages: 549-554
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14550321
[Journal Article] Post-Floorplan Control Schedule under Ma x/Min Logic/Interconnect Delays2003
- Author(s)
  Mineo Kaneko, Koji Ohashi
- Journal Title
  
  電子情報通信学会第16回回路とシステム軽井沢ワークショップ論文集
  
  Pages: 195-200
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14550321
[Journal Article] Automatic Register to Register Transfer Insertion in Assignment Driven Scheduling2003
- Author(s)
  Takayuki Obata, Mineo Kaneko, Satoshi Tayu
- Journal Title
  
  Technical Report of the Institute of Electronics, Information and Communication Engineers Vol.VLD2003-2
  
  Pages: 7-12
- NAID
  110003294197
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-14550321
[Journal Article] 回路階層構造の動的再構築を伴う力学的手法に基づくフロアプラン合成2003
- Author(s)
  小原正寛, 高島康裕, 金子峰雄
- Journal Title
  
  電子情報通信学会VLSI設計技術研究会技術報告 VLD2002-148
  
  Pages: 13-18
- NAID
  110003316144
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14550321
[Journal Article] 計算アルゴリズムの局所的類似性とそのデータパス合成への応用2003
- Author(s)
  厚見吉彦, 大橋功治, 金子峰雄
- Journal Title
  
  電子情報通信学会VLSI設計技術研究会技術報告 VLD2003-3
  
  Pages: 13-18
- NAID
  110003294198
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14550321
[Journal Article] Binding Constrained Scheduling for Iterative Algorit hm with Conditional Branches2003
- Author(s)
  Koji Ohashi, Mineo Kaneko
- Journal Title
  
  Proceedings of the Workshop on Synthesis and System Integration of Mixed Information Technologies
  
  Pages: 144-151
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14550321
[Journal Article] Binding Constrained Scheduling for Iterative Algorithm with Conditional Branches2003
- Author(s)
  Koji Ohashi, Mineo Kaneko
- Journal Title
  
  Proceedings of the Workshop on Synthesis and System Integration of Mixed Information Technologies
  
  Pages: 144-151
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-14550321
[Journal Article] Post-Floorplan Control Schedule under Max/Min Logic/Interconnect Delays2003
- Author(s)
  Mineo Kaneko, Koji Ohashi
- Journal Title
  
  Proceedings of 16th Workshop on Circuits and Systems in Karuizawa
  
  Pages: 195-200
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-14550321
[Journal Article] 資源割り当て駆動スケジューリングにおけるレジスタ転送の自動挿入2003
- Author(s)
  小畑貴之, 金子峰雄
- Journal Title
  
  電子情報通信学会VLSI設計技術研究会技術報告 VLD2003-2
  
  Pages: 7-12
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14550321
[Journal Article] Local Similarity in Computation Algorithm and Its Application to Data-path Synehsis2003
- Author(s)
  Yoshihiko Atsumi, Koji Ohashi, Mineo Kaneko
- Journal Title
  
  Technical Report of the Institute of Electronics, Information and Communication Engineers Vol.VLD2003-3
  
  Pages: 13-18
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-14550321
[Journal Article] 幅制約モジュール配置問題のSAを用いた最適化手法2002
- Author(s)
  田湯智, 金子峰雄
- Journal Title
  
  電子情報通信学会VLSI設計技術研究会技術報告 VLD2002-100
  
  Pages: 109-114
- NAID
  110003173553
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14550321
[Journal Article] Force-Directed Floorplan Synthesis with Rearrangement of Hierarchical Structure2002
- Author(s)
  Masahiro Obara, Yasuhiro Takashima, Mineo Kaneko
- Journal Title
  
  Technical Report of the Institute of Electronics, Information and Communication Engineers Vol.VLD2002-148
  
  Pages: 13-18
- NAID
  110003316144
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-14550321
[Journal Article] The Width Constrained Placement by the Simulated Annealing with the Sequence Pair Encoding2002
- Author(s)
  Satoshi Tayu, Mineo Kaneko
- Journal Title
  
  Technical Report of the Institute of Electronics, Information and Communication Engineers Vol.VLD2002-100
  
  Pages: 109-114
- NAID
  110003173553
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-14550321
[Journal Article] Loop Pipeline Scheduling for Assignment Constrained Iteration Period Minimization
- Author(s)
  Koji Ohashi, Mineko Kaneko
- Journal Title
  
  WSEAS Trans. on Circuits and Systems (印刷中)
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Statistical Analysis Driven Synthesis of Application Specific Asynchronous Systems
- Author(s)
  Koji Ohashi, Mineko Kaneko
- Journal Title
  
  IEICE Trans. Fundamentals (印刷中)
- NAID
  110007519118
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Heuristic and Exact Resource Binding Algorithms for Storage Optimization Using Flip-flops and Latches
- Author(s)
  Keisuke Inoue, Mineo Kaneko
- Journal Title
  
  IEICE Trans. Fundamentals
- NAID
  130003370707
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-22560326
[Journal Article] Statistical Analysis Driven Synthesis of Application Specific Asynchronous Systems
- Author(s)
  Koji Ohashi, Mineo Kaneko
- Journal Title
  
  IEICE Trans.Fundamentals (to appear)
- NAID
  110007519118
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Journal Article] Loop Pipeline Scheduling for Assignment Constrained Iteration Period Minimization
- Author(s)
  Koji Ohashi, Mineo Kaneko
- Journal Title
  
  WSEAS Transactions on Circuits and Systems (to appear)
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-16560294
[Presentation] Macro Construction Rules and Optimization for Long Bit Parallel Prefix Adders2023
- Author(s)
  Mineo Kaneko
- Organizer
  IEEE International Symposium on Circuits and Systems
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11211
[Presentation] ２グラフ制約表現による温度依存クロック・スキュースケジュール2020
- Author(s)
  金子峰雄
- Organizer
  電子情報通信学会 VLSI設計技術研究会
- Data Source
  KAKENHI-PROJECT-18K11211
[Presentation] Two-Graph Approach to Temperature Dependent Skew Scheduling2020
- Author(s)
  Mineo Kaneko
- Organizer
  International Symposium on Quality Electronic Design
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11211
[Presentation] A Novel Framework for Temperature Dependence Aware Clock Skew Scheduling2015
- Author(s)
  Mineo Kaneko
- Organizer
  ACM Great Lakes Symposium on VLSI
- Place of Presentation
  米国ピッツバーグ
- Year and Date
  2015-05-20
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-26420303
[Presentation] Test Planning for Post-Silicon Skew Tuning Based on Graph Partitioning2013
- Author(s)
  Mineo Kaneko
- Organizer
  電子情報通信学会 VLSI 設計技術研究会
- Place of Presentation
  沖縄県那覇市
- Year and Date
  2013-03-06
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] Test Planning for Post-Silicon Skew Tuning Based on Graph Partitioning2013
- Author(s)
  Mineo Kaneko
- Organizer
  電子情報通信学会 VLSI設計技術研究会
- Place of Presentation
  沖縄県那覇市青年会館
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] Register Binding and Domain Assignment for Multi-Domain Clock Skew Scheduling-Aware High-Level Synthesis2012
- Author(s)
  Keisuke Inoue, Mineo Kaneko
- Organizer
  Proceedings of International Symposium on Quality Electronic Design (ISQED)
- Place of Presentation
  Santa Clara, California, USA
- Year and Date
  2012-03-21
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] Timing-Test Scheduling for Constraint-Graph Based Post-Silicon Skew Tuning2012
- Author(s)
  Mineo Kaneko
- Organizer
  IEEE International Conference on Computer Design
- Place of Presentation
  カナダモントリオール
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] Timing-Test Scheduling for Constraint-Graph Based Post-Silicon Skew Tuning2012
- Author(s)
  Mineo Kaneko
- Organizer
  Proceedings of IEEE International Conference on Computer Design (ICCD)
- Place of Presentation
  Montreal, CANADA
- Year and Date
  2012-10-03
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] 製造後スキュー調整性を最大化するRTL資源割当法2012
- Author(s)
  春田洋佑, 金子峰雄
- Organizer
  電子情報通信学会VLSI設計技術研究会,VLD2011-127,pp.43-48
- Place of Presentation
  ビーコンプラザ(大分県別府市)
- Year and Date
  2012-03-06
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] Performance-Driven Register Write Inhibition in High-Level Synthesis under Strict Maximum-Permissible Clock Latency Range2012
- Author(s)
  Keisuke Inoue, Mineo Kaneko
- Organizer
  Proceedings of 17th Asia-South-Pacific Design Automation Conference (ASP-DAC 2012)
- Place of Presentation
  Sydney, Australia
- Year and Date
  2012-01-30
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] 製造後スキュー調整性を最大化するRTL 資源割当法2012
- Author(s)
  春田洋佑, 金子峰雄
- Organizer
  電子情報通信学会 VLSI 設計技術研究会
- Place of Presentation
  大分県別府市
- Year and Date
  2012-03-06
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] Statistical Timing-Yield Driven Scheduling and FU Binding in Latch-Based Datapath Synthesis2012
- Author(s)
  Keisuke Inoue, Mineo Kaneko
- Organizer
  IEEE Mid-West Symposium on Circuits and Systems
- Place of Presentation
  米国アイダホ
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] Optimal Register-Type Selection during Resource Binding in Flip-Flop/Latch-Based High-Level Synthesis2012
- Author(s)
  Keisuke Inoue, Mineo Kaneko
- Organizer
  ACM/IEEE Great Lakes Symposium on VLSI
- Place of Presentation
  米国ソルトレイクシティ
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] Post Silicon Skew Tuning Algorithm Utilizing Setup and Hold Timing Tests2012
- Author(s)
  Mineo Kaneko, Li Jiang
- Organizer
  Proceedings of IEEE International Symposium on Circuits and Systems
- Place of Presentation
  Seoul, Korea
- Year and Date
  2012-05-21
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] Dynamic Timing-Test Scheduling for Post-Silicon Skew Tuning2012
- Author(s)
  Mineo Kaneko
- Organizer
  電子情報通信学会 VLSI設計技術研究会
- Place of Presentation
  福岡県福岡市九州大学
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] Reliable and Low-Power Clock Distribution Using Pre- and Post-Silicon Delay Adaptation in High-Level Synthesis2012
- Author(s)
  Keisuke Inoue, Mineo Kaneko
- Organizer
  IEEE International Symposium on Circuits and Systems
- Place of Presentation
  韓国ソウル
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] Optimal Register-Type Selection during Resource Binding in Flip-Flop/ Latch-Based High-Level Synthesis2012
- Author(s)
  Keisuke Inoue, Mineo Kaneko
- Organizer
  Proceedings of ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI)
- Place of Presentation
  Salt Lake City, Utah, USA
- Year and Date
  2012-05-03
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] Post-Silicon Skew Tuning Algorithm Utilizing Setup and Hold Timing Tests2012
- Author(s)
  Mineo Kaneko, Li Jiang
- Organizer
  IEEE International Symposium on Circuits and Systems
- Place of Presentation
  韓国ソウル
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] Dynamic Timing-Test Scheduling for Post-Silicon Skew Tuning2012
- Author(s)
  Mineo Kaneko
- Organizer
  電子情報通信学会 VLSI 設計技術研究会
- Place of Presentation
  福岡県福岡市
- Year and Date
  2012-11-27
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] Reliable and Low-Power Clock Distribution Using Pre- and Post-Silicon Delay Adaptation in High-Level Synthesis2012
- Author(s)
  Keisuke Inoue, Mineo Kaneko
- Organizer
  Proceedings of IEEE International Symposium on Circuits and Systems
- Place of Presentation
  Seoul, Korea
- Year and Date
  2012-05-22
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] Register Binding and Domain Assignment for Multi-Domain Clock Skew Optimization2011
- Author(s)
  Keisuke Inoue, Mineo Kaneko
- Organizer
  電子情報通信学会VLSI設計技術研究会,VLD2011-51,pp.61-66
- Place of Presentation
  会津大学(福島県)
- Year and Date
  2011-09-27
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] Operation Scheduling Considering Time Borrowing for High-Performance Latch Based Circuits2011
- Author(s)
  Keisuke Inoue, Mineo Kaneko
- Organizer
  Proceedings of 9th IEEE International NEW Circuits and System Conference (NEWCAS 2011)
- Place of Presentation
  Bordeaux,France
- Year and Date
  2011-06-28
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] A Complete Framework of Simultaneous Functional Unit and Register Binding with Skew Scheduling2011
- Author(s)
  Mineo Kaneko
- Organizer
  International Symposium on Quality Electronic Design
- Place of Presentation
  米国サンタクララ
- Year and Date
  2011-03-15
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] Register Binding and Domain Assignment for Multi-Domain Clock Skew Optimization2011
- Author(s)
  Keisuke Inoue, Mineo Kaneko
- Organizer
  電子情報通信学会 VLSI 設計技術研究会
- Place of Presentation
  福島県会津市
- Year and Date
  2011-09-27
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] タイミングテストを利用するLSI製造後スキュー調整アルゴリズム2011
- Author(s)
  李健, 金子峰雄
- Organizer
  電子情報通信学会基礎・境界ソサイエティ大会,講演A-3-17,基礎・境界講演論文集p.91
- Place of Presentation
  北海道大学(北海道)
- Year and Date
  2011-09-16
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] Early Planning for RT-Level Delay Insertion during Clock Skew-Aware Register Binding2011
- Author(s)
  Keisuke Inoue, Mineo Kaneko
- Organizer
  Proceedings of IFIP/IEEE International Conference on Very Large Scale Integration and System-on-Chip (VLSI-SoC) 2011
- Place of Presentation
  Kowloon, Hong Kong
- Year and Date
  2011-10-03
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] Ordered Coloring-Based Resource Binding for Datapaths with Improved Skew Adjustability2011
- Author(s)
  Mineo Kaneko, Keisuke Inoue
- Organizer
  Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI 2011)
- Place of Presentation
  Lausanne, Switzerland
- Year and Date
  2011-05-04
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] 速度性能とタイミングスキュー調整特性に優れたデータパスの合成手法2011
- Author(s)
  党羽, 金子峰雄
- Organizer
  電子情報通信学会VLSI設計技術研究会
- Place of Presentation
  沖縄県那覇市
- Year and Date
  2011-03-03
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] A Basic Study on Timing-Test Scheduling for Post-Silicon Skew Tuning2011
- Author(s)
  Mineo Kaneko
- Organizer
  電子情報通信学会 VLSI 設計技術研究会
- Place of Presentation
  宮崎県宮崎市
- Year and Date
  2011-11-29
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] On the NP-Hardness of Minimum-Period Register Binding2011
- Author(s)
  Keisuke Inoue, Mineo Kaneko
- Organizer
  電子情報通信学会基礎・境界ソサイエティ大会
- Place of Presentation
  北海道札幌市
- Year and Date
  2011-09-15
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] A Basic Study on Timing-Test Scheduling for Post-Silicon Skew Tuning2011
- Author(s)
  Mineo Kaneko
- Organizer
  電子情報通信学会VLSI設計技術研究会,VLD2011-79,DC2011-55 pp.159-164
- Place of Presentation
  ニューウェルシティ宮崎(宮崎県宮崎市)
- Year and Date
  2011-11-29
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] 速度性能とタイミングスキュー調整特性に優れたデータパスの合成手法2011
- Author(s)
  党羽, 金子峰雄
- Organizer
  電子情報通信学会 VLSI 設計技術研究会
- Place of Presentation
  沖縄県那覇市
- Year and Date
  2011-03-02
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] Variable-Duty-Cycle Scheduling in Double Edge Triggered Flip-Flop-Based High-Level Synthesis2011
- Author(s)
  Keisuke Inoue, Mineo Kaneko
- Organizer
  Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS)
- Place of Presentation
  Rio de Janeiro, Brazil
- Year and Date
  2011-05-15
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] タイミングテストを利用するLSI 製造後スキュー調整アルゴリズム2011
- Author(s)
  李健, 金子峰雄
- Organizer
  電子情報通信学会基礎・境界ソサイエティ大会
- Place of Presentation
  北海道札幌市
- Year and Date
  2011-09-16
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] On the NP-Hardness of Minimum-Period Register Binding2011
- Author(s)
  Keisuke Inoue, Mineo Kaneko
- Organizer
  電子情報通信学会基礎・境界ソサイエティ大会講演A-1-15,基礎・境界講演論文集p.15
- Place of Presentation
  北海道大学(北海道)
- Year and Date
  2011-09-15
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] LSI設計技術の最前線--タイミングばらつきを克服する--2011
- Author(s)
  金子峰雄
- Organizer
  電気関係学会北陸支部連合大会
- Place of Presentation
  福井大学(福井県)(招待講演)
- Year and Date
  2011-09-17
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] A Complete Framework of Simultaneous Functional Unit and Register Binding with Skew Scheduling2011
- Author(s)
  Mineo Kaneko
- Organizer
  Proceedings of International Symposium on Quality Electronic Design (ISQED), IEEE Catalog No. CFP11250-CDR
- Place of Presentation
  Santa Clara, CA, USA
- Year and Date
  2011-03-15
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] ILP Approach to Extended Ordered Coloring for Skew Adjustability-Aware Resource Binding2010
- Author(s)
  Mineo Kaneko
- Organizer
  電子情報通信学会VLSI設計技術研究会
- Place of Presentation
  福岡県福岡市
- Year and Date
  2010-12-01
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] Ordered Coloring for Skew Adjustability-Aware Resource Binding2010
- Author(s)
  Mineo Kaneko
- Organizer
  電子情報通信学会 VLD 研究会
- Place of Presentation
  京都府京都市
- Year and Date
  2010-09-27
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] ILP Approach to Extended Ordered Coloring for Skew Adjustably-Aware Resource Binding2010
- Author(s)
  Mineo Kaneko
- Organizer
  電子情報通信学会 VLSI 設計技術研究会
- Place of Presentation
  福岡県福岡市
- Year and Date
  2010-12-01
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] Optimal Register Assignment with Minimum-Delay Compensation for Latch-Based Design2010
- Author(s)
  Keisuke Inoue, Mineo Kaneko
- Organizer
  Proceedings of 2010 IEEE Asia Pacific Conference on Circuits and Systems
- Place of Presentation
  Kuala Lumpur, Malaysia
- Year and Date
  2010-12-06
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] 耐遅延変動データパス合成における性能を考慮した可変式順序制約付レジスタ割り当て2010
- Author(s)
  井上恵介,金子峰雄
- Organizer
  情報処理学会 DA シンポジウム
- Place of Presentation
  愛知県豊橋市
- Year and Date
  2010-09-03
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] An Approach to Test Scheduling for Asynchronous On-Chip Interconnects Using Integer Programming2010
- Author(s)
  Tsuyoshi Iwagaki, Eiri Takeda, Mineo Kaneko
- Organizer
  Proceedings of IEEE Eleventh Workshop on RTL and High Level Testing (WRTLT'10)
- Place of Presentation
  Shanghai, P.R. China
- Year and Date
  2010-12-05
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] Ordered Coloring for Skew Adjustability-Aware Resource Binding2010
- Author(s)
  Mineo Kaneko
- Organizer
  電子情報通信学会VLSI設計技術研究会
- Place of Presentation
  京都府京都市
- Year and Date
  2010-09-27
- Data Source
  KAKENHI-PROJECT-22560326
[Presentation] Adjustable Safe Clocking and Relevant Register Assignment in Datapath Synthesis2009
- Author(s)
  Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
- Organizer
  IEICE Technical Report
- Place of Presentation
  沖縄
- Year and Date
  2009-03-11
- Data Source
  KAKENHI-PROJECT-19560340
[Presentation] 制御のタイミングスキューおよびストールに基づくLSIチューニング2009
- Author(s)
  上原八弓, 金子峰雄
- Organizer
  電子情報通信学会VLSI 設計技術研究会
- Place of Presentation
  東京
- Year and Date
  2009-01-29
- Data Source
  KAKENHI-PROJECT-19560340
[Presentation] Safe Clocking Based Datapath Synthesis for the Setup and Hold Timing Constraints2009
- Author(s)
  Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
- Organizer
  IEICE Circuits and Systems KARUIZAWA Workshop
- Place of Presentation
  軽井沢(発表決定)
- Year and Date
  2009-04-20
- Data Source
  KAKENHI-PROJECT-19560340
[Presentation] A Note on the Number of Extra Registers in Safe Clocking-Based Register Assignment2009
- Author(s)
  Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
- Organizer
  IEICE Technical Report
- Place of Presentation
  宮崎
- Year and Date
  2009-01-22
- Data Source
  KAKENHI-PROJECT-19560340
[Presentation] 高位合成における順序制約付レジスタ割り当て2008
- Author(s)
  井上恵介, 金子峰雄, 岩垣剛
- Organizer
  電子情報通信学会VLSI設計技術研究会
- Place of Presentation
  札幌
- Year and Date
  2008-06-26
- Data Source
  KAKENHI-PROJECT-19560340
[Presentation] データパス合成における最小遅延補正演算器数の最小化手法2008
- Author(s)
  井上恵介, 金子峰雄, 岩垣剛
- Organizer
  電子情報通信学会回路とシステム軽井沢ワークショップ
- Place of Presentation
  軽井沢
- Year and Date
  2008-04-21
- Data Source
  KAKENHI-PROJECT-19560340
[Presentation] Delay Variation-Aware Datapath Synthesis Based on Register Clustering2008
- Author(s)
  Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
- Organizer
  IEICE Technical Report
- Place of Presentation
  金沢
- Year and Date
  2008-09-29
- Data Source
  KAKENHI-PROJECT-19560340
[Presentation] Delay Variability-Aware Datapath Synthesis Based on Safe Clocking for Setup and Hold Timing Constraints2008
- Author(s)
  Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
- Organizer
  IEICE Technical Report
- Place of Presentation
  福岡
- Year and Date
  2008-11-17
- Data Source
  KAKENHI-PROJECT-19560340
[Presentation] データパス合成における最小遅延補正演算器数の最小化手法2008
- Author(s)
  井上恵介, 金子峰雄, 岩垣剛
- Organizer
  電子情報通信学会技術報告VLSI設計技術研究会
- Place of Presentation
  沖縄
- Year and Date
  2008-03-05
- Data Source
  KAKENHI-PROJECT-19560340
[Presentation] 先端LSIのための高位合成問題2008
- Author(s)
  金子峰雄
- Organizer
  電子情報通信学会
- Place of Presentation
  北陸先端科学技術大学院大学
- Year and Date
  2008-06-16
- Data Source
  KAKENHI-PROJECT-19560340
[Presentation] スキュー最適化を前提とするデータパス合成におけるスケジュール可能解空間の拡大2008
- Author(s)
  小畑貴之, 金子峰雄
- Organizer
  電子情報通信学会技術報告
- Place of Presentation
  福岡
- Year and Date
  2008-11-17
- Data Source
  KAKENHI-PROJECT-19560340
[Presentation] スキュー最適化を前提とした実行可能な資源割り当て及び演算順序2008
- Author(s)
  Takayuki Obata, Mineo Kaneko
- Organizer
  IEICE Technical Report
- Place of Presentation
  金沢
- Year and Date
  2008-09-29
- Data Source
  KAKENHI-PROJECT-19560340
[Presentation] データパス合成における順序制約付レジスタ割り当て問題の解法2008
- Author(s)
  井上恵介, 金子峰雄, 岩垣剛
- Organizer
  DAシンポジウム
- Place of Presentation
  静岡
- Year and Date
  2008-08-26
- Data Source
  KAKENHI-PROJECT-19560340
[Presentation] A Schedule Improvement with Skew Control in Datapath Synthesis2007
- Author(s)
  Takayuki Obata, Mineo Kaneko
- Organizer
  電子情報通信学会技術報告VLSI 設計技術研究会
- Place of Presentation
  福岡
- Year and Date
  2007-11-20
- Data Source
  KAKENHI-PROJECT-19560340
[Presentation] Complexities and Algorithms of Minimum-Delay Compensation Problems in Datapath Synthesis2007
- Author(s)
  Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
- Organizer
  電子情報通信学会技術報告VLSI設計技術研究会
- Place of Presentation
  福岡
- Year and Date
  2007-11-20
- Data Source
  KAKENHI-PROJECT-19560340
[Presentation] Timing-Test Scheduling for PDE Tuning Considering Multiple-Path Testability
- Author(s)
  金子峰雄
- Organizer
  電子情報通信学会ＶＬＤ研究会
- Place of Presentation
  別府国際コンベンションセンター（大分県別府市）
- Year and Date
  2014-11-26 – 2014-11-28
- Data Source
  KAKENHI-PROJECT-26420303

1. ONODA Mahoki (00016312)

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
2. KUNIEDA Hiroaki (50126273)

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
3. INOGUCHI Yasushi (90293406)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
4. FUKUSHI Masaru (50345659)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
5. SATOU Yukinori (30452113)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
6. NISHINA Kikuko (40198479)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
7. KAGAWA Toshiharu (50108221)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
8. SEKINE Mitsuo (40111679)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
9. NAKAHAMA Seiich (90016410)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
10. KUMURA Tsutomu (40016506)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
11. OKAMOTO Eiji (60242567)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
12. KUROSAWA Kaoru (60153409)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
13. MAMBO Masahiro (60251972)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
14. SHINODA Youichi (50206108)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
15. UEMATSU Tomohiko (60168656)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
16. TAYU Satoshi (20293392)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
17. FUJII Nobuo (00016601)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
18. TAKAGI Shigetaka (10187932)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
19. NISHIHARA Akinori (90114884)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
20. TAKAKUBO Kawori (40282834)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
21. ISHIKAWA Masayuki (50143665)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
22. 貴家仁志 (40157110)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
23. 谷口すみ子 (30217129)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
24. 和田和千 (00302943)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
25. ZHANG Renyuan

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
26. OH Junghoon

# of Collaborated Projects: 1 results

# of Collaborated Products: 1 results
27. KATSUMATA Kazuho

# of Collaborated Projects: 1 results

# of Collaborated Products: 2 results
28. SOGA Makoto

# of Collaborated Projects: 1 results

# of Collaborated Products: 2 results
29. SHIMURA Kai

# of Collaborated Projects: 1 results

# of Collaborated Products: 1 results
30. HANDAYANI Tj

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
31. SAMAUN Samad

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
32. KIYA Hitoshi

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
33. SAMADIKUN Samaun

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
34. TJANDRASA Handayani

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
35. KIMOTO Haruo

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results

KANEKO Mineo 金子 峰雄

Research Projects

Research Products

Co-Researchers

Study on Autonomous Timing Correction and Design Optimization for Next Generation LSI SystemsPrincipal Investigator

Principal Investigator

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Review Section

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Theory and Design of Post-Silicon Multi-Way Tuning for New Generation LSI CircuitsPrincipal Investigator

Principal Investigator

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Ultra High Speed Audio Fingerprint Detection and Search

Principal Investigator

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Robustness against delay variations and design optimization for datapath circuits with post silicon timing tuning mechanismPrincipal Investigator

Principal Investigator

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Theory and Optimization of Reliable Datapath Circuits having Robustness against Delay VariationPrincipal Investigator

Principal Investigator

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Theory and Design Method of Clock-less Datapath for Next Generation VLSIsPrincipal Investigator

Principal Investigator

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Three Dimensional Dapapath Synthesis for Nanotechnology VLSIsPrincipal Investigator

Principal Investigator

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超大規模計算の高速算法自動合成の理論Principal Investigator

Principal Investigator

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Design System for Next-Generation High-Performance Analog Integrated Circuits

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Theory and design of fault tolerant integrated systemsPrincipal Investigator

Principal Investigator

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Research of Self-protection Mechanism for Information

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Development of Japanese textbooks for Science and Technology

Principal Investigator

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Performance and Software Design of Signal Processing Hardwares

Principal Investigator

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KANEKO Mineo 金子峰雄