Matsunaga Yusuke 松永裕介

… Alternative Names

松永裕介マツナガユウスケ

MATSUNAGA Yusuke 松永裕介

MATSUNAGA Yuusuke 松永裕介

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Researcher Number	00336059
Other IDs
Affiliation (Current)	2025: 九州大学, システム情報科学研究院, 准教授
Affiliation (based on the past Project Information) *help	2018 – 2021: 九州大学, システム情報科学研究院, 准教授 2009 – 2010: 九州大学, システム情報科学研究院, 准教授 2008 – 2010: Kyushu University, 大学院・システム情報科学研究院, 准教授 2007: 九州大学, システム情報科学研究院, 准教授 2004: 九州大学, システム情報科学研究院, 助教授 2002 – 2004: 九州大学, システムLSI研究センター, 助教授 2001 – 2004: Kyushu University, Department of Computer Science and Communication Engineering, Associate Professor, 大学院・システム情報科学研究院, 助教授
Review Section/Research Field	Principal Investigator Computer system/Network / Basic Section 60040:Computer system-related Except Principal Investigator 計算機科学 / Medium-sized Section 60:Information science, computer engineering, and related fields / Science and Engineering / 電子デバイス・機器工学 / Computer system/Network
Keywords	Principal Investigator 論理合成 / BDD / FPGA / ＳＡＴ / ハードウェアセキュリティ / SAT(充足可能性判定問題) / セキュリティ / LSI設計 / SAT / 論理暗号化 … More / DAG-covering / logic function manipulation / technology mapping / ブーリアン・マッチング / 二分決定グラフ / 関数分解 / DAG被覆 / 論理関数処理 / テクノロジマッピング / テストパタン生成 / システムレベル検証 / システムLSI … More Except Principal Investigator システムLSI / アーキテクチャ / プロセッサ / System on a Chip / 基本ソフトウェア / 低消費エネルギー / dynamic optimization / computer architecture / low power design / system LSI / 動的最適化 / HW / 計算機アーキテクチャ / 低消費電力化 / BIST / マイクロプロセッサ / 超伝導コンピューティング / コンピュータアーキテクチャ / Social Infrastructure System / Low Power Technique / Computer System / Secure Network / ディジタルネーミング / 無線通信ネットワーク / 暗号回路 / 情報セキュリティ / 個人認証 / RFID / ディジタルメーミング / 社会基盤システム / 低消費電力技術 / 計算機システム / システムオンチップ / セキュアネットワーク / circuit design / adaptive control / optimizing compiler / profiling / 回路設計 / 適応制御 / 最適化コンパイラ / プロファイリング / Dynamic control of memory access bits / Dynamic control of data-bus / Dynamic control of pipeline depth / Datapath width optimization / High-performance Low-power / システム設計 / 組込みシステム / 特定用途向け / 低消費電力 / 高性能 / 動的メモリアクセスビット幅制御 / 動的データパス幅制御 / 有効ビット幅解析 / 可変電源電圧プロセッサ / 低消費電力プロセッサ / 動的メモリアクセスビット制御 / 動的データバス制御 / 動的パイプライン段数制御 / データパス幅最適化 / 高性能低消費電力化 / Memory / Architecture / Processor / System Software / Embedded System / Variable Voltage / Low Energy / メモリ / 組み込みシステム / 可変電源電圧 / SW codesign / design optimization / design methodology / IP core / SWコデザイン / 設計最適化 / 設計支援技術 / IPコア / Dispersion of delay / Performance Test / External Testing / Testing Time / Testing / System LSIs / Core-Based Design / CBET / コアベースシステム / 遅延時間のばらつき / 性能テスト / 外部テスト / テスト時間 / テスト / コアベース設計 / 悪意ある攻撃 / 人為的な誤り / LSI設計フロー / ディペンダブル / 電子マネー / セキュリティ / ICカード / 社会情報基盤 / LSIテスト / LSIアーキテクチャ / LSI設計 / ディペンダブルLSI Less

Over 100 GHz Time-Space Superconductor Computing for Post-Moore Era
- Principal Investigator
  
  Inoue Koji
- Project Period (FY)
  2019 – 2021
- Research Category
  
  Grant-in-Aid for Scientific Research (A)
- Review Section
  
  Medium-sized Section 60:Information science, computer engineering, and related fields
- Research Institution
  Kyushu University
Developing robust algorithms for logic encryption protecting against piracy of logic IPPrincipal Investigator
- Principal Investigator
  
  Matsunaga Yusuke
- Project Period (FY)
  2018 – 2020
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Kyushu University
Model abstraction for accelerating TLM verification and test pattern generationPrincipal Investigator
- Principal Investigator
  
  MATSUNAGA Yusuke
- Project Period (FY)
  2008 – 2010
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Kyushu University
Research on Design Methodology of Dependable LSI Loading Value and Trust
- Principal Investigator
  
  YASUURA Hiroto
- Project Period (FY)
  2007 – 2009
- Research Category
  
  Grant-in-Aid for Scientific Research (A)
- Research Field
  
  Computer system/Network
- Research Institution
  Kyushu University
Development of a Technology Mapper for FPGA using Boolean Function Manipulation TechniquesPrincipal Investigator
- Principal Investigator
  
  MATSUNAGA Yusuke
- Project Period (FY)
  2003 – 2004
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  KYUSHU UNIVERSITY
Research on System LSI Design Methodology for Social Infrastructure
- Principal Investigator
  
  HIROTO Yasuura
- Project Period (FY)
  2002 – 2006
- Research Category
  
  Grant-in-Aid for Creative Scientific Research
- Research Institution
  Kyushu University
Development of "Hardware Morphing" Technology for Dynamic Optimization of Hardware Configuration
- Principal Investigator
  
  MURAKAMI Kazuaki
- Project Period (FY)
  2001 – 2003
- Research Category
  
  Grant-in-Aid for Scientific Research (A)
- Research Field
  
  計算機科学
- Research Institution
  Kyushu University
Development of Architectures and Design Methodologies of Customizable IP Cores for System-LSI's
- Principal Investigator
  
  MURAKAMI Kazuaki
- Project Period (FY)
  2000 – 2002
- Research Category
  
  Grant-in-Aid for Scientific Research (A)
- Research Field
  
  計算機科学
- Research Institution
  Kyushu University
The Development of Basic Software Techniques for Variable-Voltage Processors Targeting Low-Energy Consumption
- Principal Investigator
  
  YASUURA Hiroto
- Project Period (FY)
  2000 – 2001
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  計算機科学
- Research Institution
  Kyushu University
Development of High-performance Low-power Processor Systems
- Principal Investigator
  
  YASUURA Hiroto
- Project Period (FY)
  2000 – 2002
- Research Category
  
  Grant-in-Aid for Scientific Research on Priority Areas
- Review Section
  
  Science and Engineering
- Research Institution
  kyushu University
A Study on Delay and Function Test for Core-Based System LSIs
- Principal Investigator
  
  YASUURA Hiroto
- Project Period (FY)
  1999 – 2001
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  電子デバイス・機器工学
- Research Institution
  Kyushu University

All 2021 2019 2018 2010 2009 2008 2007 2005 2004 2003

All Journal Article Presentation

[Journal Article] Framework for Parallel Prefix Adder Synthesis Considering Switching Activities2009
- Author(s)
  Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
- Journal Title
  
  IPSJ Transactions on System LSI Design Methodology Vol.2
  
  Pages: 212-221
- NAID
  110009598037
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300020
[Journal Article] Area Recovery under Depth Constraint for Technology Mapping for LUT-based FPGAs2009
- Author(s)
  Taiga Takata, Yusuke Matsunaga
- Journal Title
  
  IPSJ Transactions on System LSI Design Methodology Vol.2
  
  Pages: 200-211
- NAID
  110009598036
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300020
[Journal Article] Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAs2009
- Author(s)
  Taiga Takata, Yusuke Matsunaga
- Journal Title
  
  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
  
  Volume: Vol.E92.A, No.12 Pages: 3268-3275
- NAID
  10026861820
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300020
[Journal Article] Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-based FPGAs2009
- Author(s)
  Taiga Takata, Yusuke Matsunaga
- Journal Title
  
  IFICE Trans.on Fundamentals Vol. E92-A,No.12
- NAID
  10026861820
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300020
[Journal Article] Binding Refinement for Multiplexer Reduction2009
- Author(s)
  Sho Kodama, Yusuke Matsunaga
- Journal Title
  
  Transcations on System LSI Design Methodology Vol.2
  
  Pages: 43-52
- NAID
  130000120664
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300020
[Journal Article] Binding Refinement for Multiplexer Reduction2009
- Author(s)
  Sho Kodama, Yusuke Matsunaga
- Journal Title
  
  Transactions on System LSI Design Methodology Vol.2,No.2
  
  Pages: 43-52
- NAID
  130000120664
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300020
[Journal Article] Area Recovery under Depth Constraint for Technology Mapping for LUT-based FPGAs2009
- Author(s)
  Taiga Takata, Yusuke Matsunaga
- Journal Title
  
  IPSJ Transactions on System LSI Design Methodology
  
  Volume: Vol.2 Pages: 200-211
- NAID
  110009598036
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300020
[Journal Article] An Efficient Performance Improvement Method Utilizing Specialized Functional Units in Behavioral Synthesis2008
- Author(s)
  Tsuyoshi Sadakata and Yusuke Matsunaga
- Journal Title
  
  Proceedings of 13th Asia and South Pacific Design Automation Conference(ASP-DAC 2008)
  
  Pages: 32-35
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19200004
[Journal Article] A Behavioral Synthesis Method with Special Functional Units2008
- Author(s)
  Tsuyoshi Sadakata, Yusuke Matsunaga
- Journal Title
  
  IEICE Trans.On Fundamentals Vol.E91-A
  
  Pages: 1084-1091
- NAID
  10026848672
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20300020
[Journal Article] Lingのキャリー計算に基づくparallel prefix adder合成について2007
- Author(s)
  松永多苗子, 木村晋二, 松永裕介
- Journal Title
  
  情報処理学会研究報告2007-SLDM-132
  
  Pages: 163-168
- NAID
  110006533280
- Data Source
  KAKENHI-PROJECT-19200004
[Journal Article] A Simultaneous Module Selection, Scheduling, and Allocation Method Considering Operation Chaining with Multi-Functional Units2007
- Author(s)
  Tsuyoshi Sadakata and Yusuke Matsunaga
- Journal Title
  
  IEICE Transactions on Fundamentals E90-A(4)
  
  Pages: 792-799
- NAID
  110007519136
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19200004
[Journal Article] 消費電力を考慮したprefix graph合成手法について2007
- Author(s)
  松永多苗子, 松永裕介
- Journal Title
  
  情報処理学会研究報告2007-SLDM-130
  
  Pages: 63-68
- NAID
  110006290352
- Data Source
  KAKENHI-PROJECT-19200004
[Journal Article] Tim-Constrained Area Minimization Algorithm for parallel Adders2007
- Author(s)
  Taeko Matsunaga and Yusuke Matsunaga
- Journal Title
  
  IEICE Trans.Fundamentals E90-A(12)
  
  Pages: 2770-2777
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19200004
[Journal Article] Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders2007
- Author(s)
  Taeko Matsunaga, Yusuke Matsunaga
- Journal Title
  
  IEICE Transactions on Fundamentals E90-A(12
  
  Pages: 2770-2777
- NAID
  110007538023
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19200004
[Journal Article] Performance Improvement Methods Utilizing Complex Functional Units in Behavioral Synthesis2007
- Author(s)
  Tsuyoshi Sadakata and Yusuke Matsunaga
- Journal Title
  
  Proceedings of 2007 1FIP International Conference on Very Large Scale Integration(VLSI-SoC 2007)
  
  Pages: 6-7
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19200004
[Journal Article] A Simultaneous Module Selection, Scheduling, and Allocation Method Considering Operation Chaining with Multi-Functional Units2007
- Author(s)
  Tsuyoshi Sadakata, Yusuke Matsunaga
- Journal Title
  
  IEICE Transactions on Fundamentals E90-A(4)
  
  Pages: 792-799
- NAID
  110007519136
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19200004
[Journal Article] Power-Conscious Synthesis of Parallel Prefix Adders under Bitwise Timing Constraints2007
- Author(s)
  Taeko Matsunaga, Shinji Kimura, and Yusuke Matsunaga
- Journal Title
  
  The 14th Workshop on Synthesis And System Integration of Mixed Information technologies(SASIMI)
  
  Pages: 7-14
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19200004
[Journal Article] 専用演算器と演算のチェイニングのトレードオフを考慮した動作合成手法2007
- Author(s)
  貞方毅, 松永裕介
- Journal Title
  
  第20回回路とシステム軽井沢ワークショップ
  
  Pages: 655-660
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19200004
[Journal Article] Timing-constrained Area Minimization Algorithm for Parallel Prefix Adders2007
- Author(s)
  Taeko Matsunaga and Yusuke Matsunaga
- Journal Title
  
  International Workshop on Logic and Synthesis(IWLS)
  
  Pages: 150-157
- NAID
  110007538023
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19200004
[Journal Article] Parallel Prefix Adder合成を用いた乗算器の最適化手法について2007
- Author(s)
  松永多苗子, 松永裕介
- Journal Title
  
  第20回回路とシステム軽井沢ワークショップ
  
  Pages: 349-354
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-19200004
[Journal Article] LUT型FPGA向けテクノロジ・マッピングにおける深さ制約下のLUT数削減手法2007
- Author(s)
  高田大河, 松永裕介
- Journal Title
  
  電子情報通信学会技術研究報告 VLD2007-101
  
  Pages: 73-78
- NAID
  110006533284
- Data Source
  KAKENHI-PROJECT-19200004
[Journal Article] 専用演算器の使用を考慮した効率的な動作合成手法2007
- Author(s)
  貞方毅, 松永裕介
- Journal Title
  
  電子情報通信学会技術研究報告 VLD2007-89
  
  Pages: 55-59
- NAID
  110006533281
- Data Source
  KAKENHI-PROJECT-19200004
[Journal Article] DAGカバリング問題の下限とそれを用いた厳密アルゴリズムについて2007
- Author(s)
  松永裕介
- Journal Title
  
  情報処理学会研究報告2007-SLDM-130
  
  Pages: 39-44
- NAID
  110006290348
- Data Source
  KAKENHI-PROJECT-19200004
[Journal Article] 非順序式バックトラック手法を用いたテストパタン生成における矛盾の解析2007
- Author(s)
  吉村正義, 松永裕介
- Journal Title
  
  DAシンポジウム2007 2007(7)
  
  Pages: 211-214
- Data Source
  KAKENHI-PROJECT-19200004
[Journal Article] 動作合成におけるチェイニングに関する考察2005
- Author(s)
  貞方毅, 松永裕介
- Journal Title
  
  情報処理学会研究報告 2005-SLDM-122
  
  Pages: 67-72
- NAID
  110004018524
- Data Source
  KAKENHI-PROJECT-14GS0218
[Journal Article] コンテクストを考慮した parallel prefix adder 合成手法2005
- Author(s)
  松永多苗子, 松永裕介
- Journal Title
  
  電子情報通信学会技術報告 No.VLD2005-2 (2005-05)
  
  Pages: 7-12
- NAID
  110003295452
- Data Source
  KAKENHI-PROJECT-14GS0218
[Journal Article] コンテクストを考慮したparallel prefix adder合成手法2005
- Author(s)
  松永多苗子 and 松永裕介
- Journal Title
  
  電子情報通信学会技術報告 No.VLD2005-2(2005-05)
  
  Pages: 7-12
- NAID
  110003295452
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14GS0218
[Journal Article] 動作合成におけるチェイニングに関する考察2005
- Author(s)
  貞方毅 and 松永裕介
- Journal Title
  
  情報処理学会研究報告 2005-SLDM-122
  
  Pages: 67-72
- NAID
  110004018524
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14GS0218
[Journal Article] A Behavioral Synthesis Method Considering Chaining2005
- Author(s)
  Tsuyoshi Sadakata, Yusuke Matsunaga
- Journal Title
  
  IPSJ SIG Technical Report 2005-SLDM-119
  
  Pages: 19-24
- NAID
  110003206357
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300019
[Journal Article] Enhancing the Performance of Multi-Cycle Path Analysis in an Industrial Setting2004
- Author(s)
  Hiroyuki Higuchi, Yusuke Matsunaga
- Journal Title
  
  Asia and South Pacific Design Automation Conference 2004
  
  Pages: 192-197
- NAID
  120006655285
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300019
[Journal Article] Customizable Framework for Arithmetic Synthesis2004
- Author(s)
  Taeko Matsunaga, et al.
- Journal Title
  
  SASIMI2004
  
  Pages: 315-318
- NAID
  120006655315
- Data Source
  KAKENHI-PROJECT-14GS0218
[Journal Article] A Behavioral Synthesis Method Considering Complex Operations2004
- Author(s)
  Tsuyoshi Sadakata, Yusuke Matsunaga
- Journal Title
  
  DA Symposium 2004
  
  Pages: 301-306
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300019
[Journal Article] On a Boolean matching algorithm for LUT trees2004
- Author(s)
  Yusuke Matsunaga
- Journal Title
  
  IEICE Technical Report VLD2003-128, CPSY2003-37(2004-01)
  
  Pages: 19-24
- NAID
  110003178649
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300019
[Journal Article] Customizable Framework for Arithmetic Synthesis2004
- Author(s)
  Taeko Matsunaga, et al.
- Journal Title
  
  SASIMI2004
  
  Pages: 315-331
- NAID
  120006655315
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-15300019
[Journal Article] Practical test architecture optimization for system-on-a-chip under floorplanning constraints2004
- Author(s)
  Makoto Sugihara, Kazuaki Murakami, Yusuke Matsunaga
- Journal Title
  
  IEEE Computer Society Symposium on VLSI
  
  Pages: 179-184
- NAID
  120006655286
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300019
[Journal Article] LUTの木構造に対するブーリアンマッチングアルゴリズムについて2004
- Author(s)
  松永裕介
- Journal Title
  
  電子情報通信学会技術研究報告 VLD2003-128, CPSY2003-37(2004-01)
  
  Pages: 19-24
- NAID
  110003178649
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-15300019
[Journal Article] テクノロジマッピングにおけるDAG被覆アルゴリズムについて2004
- Author(s)
  松永裕介
- Journal Title
  
  電子情報通信学会技術研究報告,VLD2004-7
  
  Pages: 1-6
- NAID
  110003294344
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-15300019
[Journal Article] Customizable Framework for Arithmetic Synthesis2004
- Author(s)
  Taeko Matsunaga, et. al.
- Journal Title
  
  SASIMI2004
  
  Pages: 315-318
- NAID
  120006655315
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14GS0218
[Journal Article] Hardware Design Course in Kyushu University useing FPGA2004
- Author(s)
  Takanori Hayashida, Kiichirou Ota, Sozo Inoue, Yusuke Matsunaga, Ryo Kurazume, Tsuneo Nakasnishi, Hiroshi Fujita, Takanori Matsuzaki
- Journal Title
  
  DA Synposium 2004
  
  Pages: 49-54
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300019
[Journal Article] 関数分解に基づくLUT型FPGA用ブーリアンマッチングアルゴリズムについて2004
- Author(s)
  松永裕介
- Journal Title
  
  情報処理学会論文誌 VLD2004-7
  
  Pages: 1300-1310
- NAID
  110002712179
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14GS0218
[Journal Article] テクノロジマッピングにおけるDAG被覆アルゴリズムについて2004
- Author(s)
  松永裕介
- Journal Title
  
  電子情報通信学会技術研究報告 VLD2004-7
  
  Pages: 1-6
- NAID
  110003294344
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-14GS0218
[Journal Article] 関数分解に基づくLUT型FPGA用ブーリアンマッチングアルゴリズムについて2004
- Author(s)
  松永裕介
- Journal Title
  
  情報処理学会論文誌 45
  
  Pages: 1300-1310
- NAID
  110002712179
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-15300019
[Journal Article] On a DAG-covering algorithm for technology mapping2004
- Author(s)
  Yusuke Matsunaga
- Journal Title
  
  IEICE Technical Report VLD2004-7
  
  Pages: 1-6
- NAID
  110003294344
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300019
[Journal Article] Customizable Framework for Arithmetic Synthesis2004
- Author(s)
  Taeko Matsunaga, Yusuke Matsunaga
- Journal Title
  
  SASIMI2004
  
  Pages: 315-318
- NAID
  120006655315
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300019
[Journal Article] 関数分解に基づくLUT型FPGA用ブーリアンマッチングアルゴリズムについて2004
- Author(s)
  松永裕介他
- Journal Title
  
  情報処理学会論文誌 Vol.45-No.5
  
  Pages: 1300-1310
- NAID
  110002712179
- Data Source
  KAKENHI-PROJECT-15300019
[Journal Article] An Evaluation on the Processor Archtecture for Programable Controller2004
- Author(s)
  Daisuke Yamaguchi, Yuji Katsuki, Yusuke Matsunaga
- Journal Title
  
  IPSJ SIG Technical Report 2004-ARC-157
  
  Pages: 91-96
- NAID
  110002774604
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300019
[Journal Article] A Behavioral Synthesis Method Considering Complex Operations2004
- Author(s)
  Tsuyoshi Sadakata, Yusuke Matsunaga
- Journal Title
  
  The 12th Workshop on Synthesis And System Integration of Mixed Information technologies Vol.1
  
  Pages: 303-309
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300019
[Journal Article] Customizable Framework for Arithmetic Synthesis2004
- Author(s)
  Taeko Matsunaga, et al.
- Journal Title
  
  The 12th Workshop on Synthesis And System Integration of Mixed Information technologies(SASIMI2004)
  
  Pages: 315-318
- NAID
  120006655315
- Data Source
  KAKENHI-PROJECT-15300019
[Journal Article] On Boolean Matching Algorithm for LUI-type FPGA Based on Functional Decomposition2004
- Author(s)
  Yusuke Matsunaga
- Journal Title
  
  IPSJ Journal Vol.45, No.5
  
  Pages: 1300-1310
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300019
[Journal Article] 高位合成技術の基礎2003
- Author(s)
  松永裕介
- Journal Title
  
  電子情報通信学会ソサイエティ大会
- NAID
  120006655273
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-15300019
[Journal Article] Basic techniques for high-level synthesis2003
- Author(s)
  Yusuke Matsunaga
- NAID
  110003321605
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300019
[Journal Article] About the input vector determining method for low standby leakage current2003
- Author(s)
  Kazuhiko Hirashima, Yusuke Matsunaga
- Journal Title
  
  IEICE Technical Report 2003-VLD-103
  
  Pages: 7-12
- NAID
  110003294203
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-15300019
[Presentation] 論理施錠の施錠強度と攻撃耐性についての新たな評価の手法2021
- Author(s)
  南　周作・松永　裕介
- Organizer
  電子情報通信学会VLSI設計技術研究会
- Data Source
  KAKENHI-PROJECT-18K11219
[Presentation] アフィン変換を用いた論理暗号化手法について2019
- Author(s)
  松永　裕介
- Organizer
  電子情報通信学会VLD研究会
- Data Source
  KAKENHI-PROJECT-18K11219
[Presentation] 誤り修正論理合成を用いた論理暗号化手法2019
- Author(s)
  松永　裕介
- Organizer
  情報処理学会DAシンポジウム
- Data Source
  KAKENHI-PROJECT-18K11219
[Presentation] 誤り修正論理合成を用いた論理暗号化手法について2019
- Author(s)
  松永　裕介
- Organizer
  FTC研究会
- Data Source
  KAKENHI-PROJECT-18K11219
[Presentation] An efficient SAT-attack algorithm against logic encryption2019
- Author(s)
  Yusuke Matsunaga, Masayoshi Yoshimura
- Organizer
  IOLTS
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11219
[Presentation] An Efficient SAT-Attack Algorithm Against Logic Encryption2019
- Author(s)
  Yusuke Matsunaga
- Organizer
  International Symposium on On-Line Testing and Robust System Design (IOLTS)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19H01105
[Presentation] 論理暗号化に対する効率的なSAT攻撃アルゴリズムの評価2019
- Author(s)
  松永　裕介，　吉村　正義
- Organizer
  電子情報通信学会VLD研究会
- Data Source
  KAKENHI-PROJECT-18K11219
[Presentation] An Efficient SAT-Attack Algorithm Against Logic Encryption2019
- Author(s)
  Yusuke Matsunaga and Masayoshi Yoshimura
- Organizer
  IOLTS2019
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-18K11219
[Presentation] 論理暗号化に対するSAT攻撃アルゴリズムの高速化2019
- Author(s)
  松永　裕介，　吉村　正義
- Organizer
  FTC研究会
- Data Source
  KAKENHI-PROJECT-18K11219
[Presentation] アフィン変換を用いた論理暗号化手法の評価2019
- Author(s)
  松永　裕介
- Organizer
  電子情報通信学会VLD研究会
- Data Source
  KAKENHI-PROJECT-18K11219
[Presentation] テストセット最小化問題の両立集合被覆問題への定式化とその解法2018
- Author(s)
  松永　裕介
- Organizer
  情報処理学会DAシンポジウム
- Data Source
  KAKENHI-PROJECT-18K11219
[Presentation] 組合せ最適化問題としてのテストセット最小化問題2018
- Author(s)
  松永　裕介
- Organizer
  FTC研究会
- Data Source
  KAKENHI-PROJECT-18K11219
[Presentation] 論理暗号化に対するSAT攻撃の効率的なアルゴリズムについて2018
- Author(s)
  松永　裕介，　吉村　正義
- Organizer
  電子情報通信学会VLD研究会（デザインガイア）
- Data Source
  KAKENHI-PROJECT-18K11219
[Presentation] 高位合成における種々の最適化手法について2010
- Author(s)
  松永裕介
- Organizer
  第23回回路とシステム軽井沢ワークショップ
- Place of Presentation
  長野県,招待講演
- Year and Date
  2010-04-19
- Data Source
  KAKENHI-PROJECT-20300020
[Presentation] 高位合成における種々の最適化手法について2010
- Author(s)
  松永裕介
- Organizer
  第23回回路とシステム軽井沢ワークショップ
- Place of Presentation
  軽井沢プリンスホテル(長野県)
- Year and Date
  2010-04-19
- Data Source
  KAKENHI-PROJECT-20300020
[Presentation] TMR based Error Correction Method Considering Trade-offs between Soft Error Tolerance and Area2010
- Author(s)
  Shoji Harada, Masayoshi Yoshimura, Yusuke Matsunaga
- Organizer
  International Workshop on Logic and Synthesis
- Place of Presentation
  米国カリフォルニア州
- Year and Date
  2010-06-18
- Data Source
  KAKENHI-PROJECT-20300020
[Presentation] Multi-Operand Adder Synthesis on FPGAs using Generalized Parallel Counters2009
- Author(s)
  Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
- Organizer
  International Workshop on Logic and Synthesis
- Place of Presentation
  米国カリフォルニア州
- Year and Date
  2009-08-02
- Data Source
  KAKENHI-PROJECT-20300020
[Presentation] Multi-Operand Adder Synthesis on FPGAs using Generalized Parallel Counters2009
- Author(s)
  Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
- Organizer
  Proc.of International Workshop on Logic and Synthesis 2009,222-228
- Place of Presentation
  Berkeley, CA, USA
- Year and Date
  2009-08-01
- Data Source
  KAKENHI-PROJECT-20300020
[Presentation] A Power-aware Post-processing under depth constraint for LUT-based FPGA Technology Mapping2009
- Author(s)
  Taiga Takata, Yusuke Matsunaga
- Organizer
  Proc.of International Workshop on Logic and Synthesis 2009,332-339
- Place of Presentation
  Berkeley, CA, USA
- Year and Date
  2009-08-02
- Data Source
  KAKENHI-PROJECT-20300020
[Presentation] An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs2009
- Author(s)
  Taiga Takata, Yusuke Matsunaga
- Organizer
  ACM Great Lakes Symposium on VLSI,351-356
- Place of Presentation
  Boston, MA, USA
- Year and Date
  2009-05-11
- Data Source
  KAKENHI-PROJECT-20300020
[Presentation] ディペンダブルVLSI設計技術への挑戦2009
- Author(s)
  松永裕介, 他
- Organizer
  電子情報通信学会総合大会
- Place of Presentation
  愛媛大学
- Year and Date
  2009-03-18
- Data Source
  KAKENHI-PROJECT-19200004
[Presentation] ディペンダブルVLSI設計技術への挑戦2009
- Author(s)
  松永裕介, 安浦寛人, 馬場謙介, 吉村正義, 佐藤寿倫, 杉原真
- Organizer
  電子情報通信学会全国大会
- Place of Presentation
  愛媛大学(愛媛県松山市)
- Year and Date
  2009-03-18
- Data Source
  KAKENHI-PROJECT-19200004
[Presentation] A Power-aware Post-processing under depth constraint for LUT-based FPGA Technology Mapping2009
- Author(s)
  Taiga Takata, Yusuke Matsunaga
- Organizer
  International Workshop on Logic and Synthesis
- Place of Presentation
  米国カリフォルニア州
- Year and Date
  2009-08-01
- Data Source
  KAKENHI-PROJECT-20300020
[Presentation] Synthesis of parallel prefix adders considering switching activities2008
- Author(s)
  Taeko Matsunaga, Sin ji Kimura, Yusuke Matsunaga
- Organizer
  In proceedings of ICCD2008,404-409
- Place of Presentation
  Tahoe, CA, USA
- Year and Date
  2008-10-14
- Data Source
  KAKENHI-PROJECT-20300020
[Presentation] Synthesis of parallel prefix adders considering switching activities2008
- Author(s)
  Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
- Organizer
  ICCD2008
- Place of Presentation
  米国カリフォルニア州
- Year and Date
  2008-10-14
- Data Source
  KAKENHI-PROJECT-20300020

1. YASUURA Hiroto (80135540)

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2. MURAKAMI Kazuaki (10200263)

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3. INOUE Sozo (90346825)

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4. SAWADA Sunao (70235464)

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5. IWAIHARA Mizuho (40253538)

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6. YOSHIMURA Masayoshi (90452820)

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7. 伊達博

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8. SATO Toshinori (00322298)

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9. BABA Kensuke (70380681)

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10. Inoue Koji (80341410)

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11. TOMIYAMA Hiroyuki

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13. 富山宏之

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14. IKEDA Daisuke (00294992)

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15. ISHIDA Koji (90467879)

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18. YAMASHITA Masafumi (00135419)

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19. FUKUDA Akira (80165282)

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31. 廣瀬啓

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Matsunaga Yusuke 松永 裕介

松永 裕介 マツナガ ユウスケ

MATSUNAGA Yusuke 松永 裕介

MATSUNAGA Yuusuke 松永 裕介

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Developing robust algorithms for logic encryption protecting against piracy of logic IPPrincipal Investigator

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Model abstraction for accelerating TLM verification and test pattern generationPrincipal Investigator

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Development of a Technology Mapper for FPGA using Boolean Function Manipulation TechniquesPrincipal Investigator

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[Journal Article] Framework for Parallel Prefix Adder Synthesis Considering Switching Activities2009

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[Journal Article] Area Recovery under Depth Constraint for Technology Mapping for LUT-based FPGAs2009

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[Journal Article] Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAs2009

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[Journal Article] Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-based FPGAs2009

Matsunaga Yusuke 松永裕介

松永裕介マツナガユウスケ

MATSUNAGA Yusuke 松永裕介

MATSUNAGA Yuusuke 松永裕介