KIMURA Hiromitsu 木村啓明

Researcher Number	00361155
Affiliation (based on the past Project Information) *help	2003 – 2004: 東北大学, 大学院・情報科学研究科, 助手
Review Section/Research Field	Except Principal Investigator 計算機科学
Keywords	Except Principal Investigator data-transfer bottleneck / operation merging / storage / resistor-circuit network / device modeling / fully parallel processing / ferroelectric capacitor / TMR device / multiple-valued logic-in-memory / 多値基本演算子 … More / マイクロ順序動作 / ゲートレベルパイプライン処理 / パイプライン乗算器 / 多値集積回路 / フローティングゲートMOSトランジスタ / ゲートレベルパイプライン / FPGA / 不揮発性ロジック / 強誘電体CAM / 相補的動作 / 非破壊読出し / デバイスモデル / 全加算器 / 強誘電体デバイス / 非数値データ処理 / データ転送ボトルネックフリー / 記憶・演算一体化 / 抵抗回路網 / デバイスモデリング / 超並列演算 / 強誘電体キャパシタ / TMR素子 / 多値ロジックインメモリ Less

Implementation of a Transfer-Bottleneck-Free Multiple-Valued Logic-in-Memory VLSI and Its Application
- Principal Investigator
  
  HANYU Takahiro
- Project Period (FY)
  2001 – 2004
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  計算機科学
- Research Institution
  Tohoku University

All 2004 2003 2002

All Journal Article

[Journal Article] Complementary Ferroelectric-Capacitor Logic for Low-Power Logic-in-Memory VLSI2004
- Author(s)
  H.Kimura
- Journal Title
  
  IEEE Journal of Solid-State Circuits Vol.SC-39,No.6
  
  Pages: 919-926
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-13558026
[Journal Article] Complementary Ferroelectric-Capacitor Logic for Low-Power Logic-in-Memory VLSI2004
- Author(s)
  H.Kimura
- Journal Title
  
  IEEE Journal of Solid-State Circuits SC-39
  
  Pages: 919-926
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-13558026
[Journal Article] Complementary Ferroelectric-Capacitor Logic for Low-Power Logic-in-Memory VLSI2004
- Author(s)
  Hiromitsu Kimura
- Journal Title
  
  IEEE Journal of Solid-State Circuits SC-39・6
  
  Pages: 919-926
- Data Source
  KAKENHI-PROJECT-13558026
[Journal Article] A Study of Multiple-Valued Magnetoresistive RAM(MRAM) Using Binary MTJ2004
- Author(s)
  Hiromitsu Kimura
- Journal Title
  
  Proc.34th IEEE International Symposium on Multiple-Valued Logic 34
  
  Pages: 340-345
- Data Source
  KAKENHI-PROJECT-13558026
[Journal Article] TMR-Based Logic-in-Memory Circuit for Low-Power VLSI2004
- Author(s)
  H.Kimura
- Journal Title
  
  ITC-CSCC 2004
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-13558026
[Journal Article] TMR-Based Logic-in-Memory Circuit for Low-Power VLSI2004
- Author(s)
  Hiromitsu Kimura
- Journal Title
  
  Proc.ITC-CSCC 2004
- Data Source
  KAKENHI-PROJECT-13558026
[Journal Article] Multiple-Valued Logic-in-Memory VLSI Using MFSFETs and Its Application2003
- Author(s)
  H.Kimura
- Journal Title
  
  International Journal of Multiple-Valued Logic Vol.9, No.1
  
  Pages: 23-42
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-13558026
[Journal Article] Complementary Ferroelectric-Capacitor Logic and Its Application2003
- Author(s)
  H.Kimura
- Journal Title
  
  Digest of Technical Papers, IEEE International Solid-State Circuits Conference(ISSCC)
  
  Pages: 160-161
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-13558026
[Journal Article] 強誘電体デバイスを用いたロジックインメモリVLSIの構成2003
- Author(s)
  木村啓明
- Journal Title
  
  信学論 J86-C
  
  Pages: 886-893
- NAID
  110003202108
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-13558026
[Journal Article] Multiple-Valued Logic-in-Memory VLSI Using MFSFETs and Its Application2003
- Author(s)
  H.Kimura
- Journal Title
  
  International Journal of Multiple-Valued Logic 9
  
  Pages: 23-42
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-13558026
[Journal Article] 強誘電体デバイスを用いたロジックインメモリVLSIの構成2003
- Author(s)
  木村啓明
- Journal Title
  
  信学論 Vol.J86-C, No.8
  
  Pages: 886-893
- NAID
  110003202108
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-13558026
[Journal Article] Complementary Ferroelectric-Capacitor Logic and Its Application2003
- Author(s)
  H.Kimura
- Journal Title
  
  Digest of Technical Papers, IEEE International Solid-State Circuits Conference (ISSCC) 46
  
  Pages: 160-161
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-13558026
[Journal Article] Implementation of a DRAM-Cell-Based Multiple-Valued Logic-in-Memory Circuit2002
- Author(s)
  H.Kimura
- Journal Title
  
  IEICE Trans.on Electronics E85-C
  
  Pages: 1814-1823
- NAID
  110006351097
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-13558026
[Journal Article] Dynamic-Storage-Based Logic-in-Memory Circuit and Its Application to a Fine-Grain Pipelined System2002
- Author(s)
  H.Kimura
- Journal Title
  
  IEICE Trans.on Electronics E85-C
  
  Pages: 288-296
- NAID
  110003220853
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-13558026
[Journal Article] Dynamic-Storage-Based Logic-in-Memory Circuit and Its Application to a Fine-Grain Pipelined System2002
- Author(s)
  H.Kimura
- Journal Title
  
  IEICE Trans.on Electron. Vol.E85-C, No.2
  
  Pages: 288-296
- NAID
  110003220853
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-13558026
[Journal Article] Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition2002
- Author(s)
  H.Kimura
- Journal Title
  
  IEEE 32nd International Symposium on Multiple-Valued Logic
  
  Pages: 161-166
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-13558026
[Journal Article] Ferroelectric-Based Functional Pass-Gate for Low-Power VLSI2002
- Author(s)
  H.Kimura
- Journal Title
  
  2002 Symposium on VLSI Circuits
  
  Pages: 196-199
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-13558026
[Journal Article] Implementation of a DRAM-Cell-Based Multiple-Valued Logic-in-Memory Circuit2002
- Author(s)
  H.Kimura
- Journal Title
  
  IEICE Trans.on Electronics Vol.E85-C, No.10
  
  Pages: 1814-1823
- NAID
  110006351097
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-13558026
[Journal Article] Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition2002
- Author(s)
  H.Kimura
- Journal Title
  
  IEEE 32nd International Symposium on Multiple-Valued Logic 32
  
  Pages: 161-166
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-13558026

1. HANYU Takahiro (40192702)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
2. KAMEYAMA Michitaka (70124568)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
3. MOCHIZUKI Akira (40359542)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results

KIMURA Hiromitsu 木村 啓明

Research Projects

Research Products

Co-Researchers

Implementation of a Transfer-Bottleneck-Free Multiple-Valued Logic-in-Memory VLSI and Its Application

Principal Investigator

Project Period (FY)

Research Category

Research Field

Research Institution

[Journal Article] Complementary Ferroelectric-Capacitor Logic for Low-Power Logic-in-Memory VLSI2004

Author(s)

Journal Title

Description

Data Source

[Journal Article] Complementary Ferroelectric-Capacitor Logic for Low-Power Logic-in-Memory VLSI2004

Author(s)

Journal Title

Description

Data Source

[Journal Article] Complementary Ferroelectric-Capacitor Logic for Low-Power Logic-in-Memory VLSI2004

Author(s)

Journal Title

Data Source

[Journal Article] A Study of Multiple-Valued Magnetoresistive RAM(MRAM) Using Binary MTJ2004

Author(s)

Journal Title

Data Source

[Journal Article] TMR-Based Logic-in-Memory Circuit for Low-Power VLSI2004

Author(s)

Journal Title

Description

Data Source

[Journal Article] TMR-Based Logic-in-Memory Circuit for Low-Power VLSI2004

Author(s)

Journal Title

Data Source

[Journal Article] Multiple-Valued Logic-in-Memory VLSI Using MFSFETs and Its Application2003

Author(s)

Journal Title

Description

Data Source

[Journal Article] Complementary Ferroelectric-Capacitor Logic and Its Application2003

Author(s)

Journal Title

Description

Data Source

[Journal Article] 強誘電体デバイスを用いたロジックインメモリVLSIの構成2003

Author(s)

Journal Title

NAID

Description

Data Source

[Journal Article] Multiple-Valued Logic-in-Memory VLSI Using MFSFETs and Its Application2003

Author(s)

Journal Title

Description

Data Source

[Journal Article] 強誘電体デバイスを用いたロジックインメモリVLSIの構成2003

Author(s)

Journal Title

NAID

Description

Data Source

[Journal Article] Complementary Ferroelectric-Capacitor Logic and Its Application2003

Author(s)

Journal Title

Description

Data Source

[Journal Article] Implementation of a DRAM-Cell-Based Multiple-Valued Logic-in-Memory Circuit2002

Author(s)

Journal Title

NAID

Description

Data Source

[Journal Article] Dynamic-Storage-Based Logic-in-Memory Circuit and Its Application to a Fine-Grain Pipelined System2002

Author(s)

Journal Title

NAID

Description

KIMURA Hiromitsu 木村啓明