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HANYU Takahiro  羽生 貴弘

ORCIDConnect your ORCID iD *help
… Alternative Names

羽生 貴弘  ハニユウ タカヒロ

HANYU TAKAHIRO  羽生 貴弘

羽生 貴広  ハニュウ タカヒロ

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Researcher Number 40192702
Other IDs
External Links
Affiliation (Current) 2020: 東北大学, 電気通信研究所, 教授
Affiliation (based on the past Project Information) *help 2015 – 2020: 東北大学, 電気通信研究所, 教授
2010 – 2013: 東北大学, 電気通信研究所, 教授
2002 – 2008: Tohoku University, Research Institute of Electrical Communication, Professor, 電気通信研究所, 教授
1993 – 2001: 東北大学, 大学院・情報科学研究科, 助教授
1998: 東北大学, 大学院・情報科学研究所, 助教授 … More
1996 – 1997: Tohoku University, Graduate School of Information Sciences, Associate Professor, 大学院情報科学研究科, 助教授
1993: Tohoku University, Graduate school of Information Sciences, 情報科学研究科, 助教授
1992: TOHOKU UNIVERSITY FACULTY OF ENGINEERING ASSOCIATE PROFESSOR, 工学部, 助教授
1989 – 1991: 東北大学, 工学部, 助手 Less
Review Section/Research Field
Principal Investigator
計算機科学 / Computer system/Network / Computer system / 計測・制御工学 / Electron device/Electronic equipment
Except Principal Investigator
計算機科学 / 計測・制御工学 / 計測・制御工学 / Communication/Network engineering
Keywords
Principal Investigator
フローティングゲートMOSトランジスタ / 多値連想メモリ / 大小比較演算 / しきい演算 / 情報システム / 超並列処理 / 非数値データ処理 / 電流線形加算 / 差動対回路 / セルフチェッキング回路 … More / 記憶・演算一体化 / 不揮発性ロジック / 情報通信工学 / ロジックインメモリ構造 / 知的情報処理 / 非同期式回路 / 計算機システム / エッジ抽出 / 電流モード / 多値論理回路 / トップダウン / 特徴量 / モデルマッチング / ソース結合形 / ス-パパスゲート / 多値論理関数 / デバイスモデルベーストエレクトロニクス / 量子効果デバイス / 1トランジスタセル / 機能分離形CAM / 2線相補信号 / Signed-Digit数系 / 高速データ転送技術 / ニューパラダイムコンピユーティング / コミュニケーションVLSIプロセッサ / ISSCC / Rambus / マルチメディア応用 / 情報機器 / 高速伝送回路 / 誤り訂正符号 / 多値VLSI技術 / 非同期通信 / 2線符号 / LDPC符号 / 高速伝送技術 / 符号化 / 複号化 / 非同期式制御 / 高速プロトタイピング / 先端機能デバイス / 低電力化技術 / CAM / 不揮発性 / ロジック回路 / 回路設計技術 / 集積回路 / バラつき補正技術 / 新機能デバイス / 最適化技術 / Multiple-valued content-addressable memory (CAM) / Floating-gate-MOS pass-transistor network / Threshold operation / Logic-in-memory VLSI architecture / Non-numeric data processing / Fully parallel processing / Magnitude comparison / Intelligent information processing / フローティングゲートMOSトランスジスタ / Multiple-Valued CAM / Floating-Gate MOS Transistor / Threshold Operation / Logic-in-Memory Architecture / Non-numeric Data Processing / Highly-Parallel Operation / Magnitude Comparison / Intelligent Information Processing / 電流モード多値回路 / カレントミラーレス回路 / 電流比較回路 / 出力生成回路 / 電流電圧変換回路 / 2線式電流モード多値回路 / 多値2線式符号 / 多値算術演算回路 / ソース結合形回路 / ダイナミック回路 / カレントミラー / スレショルドディテクタ / 2線式符号 / スレッショルドディテクタ / 線形加算回路 / 2進SD数表現 / 算術演算回路 / Multiple-Valued Current-Mode Circuit / Differential-Pair Circuit / Current-Mirror-less Circuit / Current-Mode Comparator / Output Generator / Current-Mode Linear Sum / Current-to-Voltage Converter / Dual-Rail Current-Mode Circuit / 多値ロジックインメモリ / TMR素子 / 強誘電体キャパシタ / 超並列演算 / デバイスモデリング / 抵抗回路網 / データ転送ボトルネックフリー / 強誘電体デバイス / 全加算器 / デバイスモデル / 非破壊読出し / 相補的動作 / 強誘電体CAM / FPGA / ゲートレベルパイプライン / 多値集積回路 / パイプライン乗算器 / ゲートレベルパイプライン処理 / マイクロ順序動作 / 多値基本演算子 / multiple-valued logic-in-memory / TMR device / ferroelectric capacitor / fully parallel processing / device modeling / resistor-circuit network / storage / operation merging / data-transfer bottleneck / 電子デバイス・機器 / 半導体超微細化 / システムオンチップ / ネットワークオンチップ / チップ内高速データ転送技術 / 多値符号化 / ハンドシェイク通信 / クロック分配 / クロックスキュー / 2線符号化方式 / 非同期通信プロトコル / 双方向同時通信 / チップ内通信 / 2線式 / プロトコル / デュプレックス / information system / information communication engineering / electronic devices / equipments / semiconductor ultra-scaling / system-on-chip / network-on-chip / intra-chip high-speed signaling / multiple-valued encoding / 不揮発ロジック … More
Except Principal Investigator
高並列演算回路 / 知能集積システム / 多値集積回路 / 低消費電力多値集積回路 / Reed-Muller Expansion / 2線式電流モード多値集積回路 / ロジックインメモリVLSI / Dual-Rail Current-Mode Multiple-Valued Integrated Circuit / Logic-In-Memory VLSI / SD数系 / 対称R進数 / 多値ス-パ-チップ / 多値双方向電流モ-ド / 4進SD数全加算器 / ロボット制御用VLSI / ロボットビジョン用VLSI / 演算遅れ時間最小 / ス-パ-チップ / 知能ロボット用プロセッサ / 多値SD数演算回路 / 多値双方向電流モ-ド回路 / 多値モジュ-ルアレ- / 指定配線数 / 設計容易性 / セミカスタムVLSI / 知能ロボット / 高速算術演算用アレ- / 4進SD数加算器 / SD Number System / Multiple-Valued Bidirectional Current-Mode / SD Full-Adder / Modular Realization / SD Multiplier / Multiple-Valued Super Chip / 4値CMOS集積回路 / パターンマッチングセル / フローティングゲートMOS-FET / 推論チップ / 物体認識システム / グラフマッチング / クリーク抽出 / 3次元物体認識 / 知的情報処理 / VLSIアレー / 超高速推論ハ-ドウェアエンジン / パタ-ンマッチングセル / フロ-ティングゲ-トMOS-FET / 4-Valued CMOS Integrated Circuit / Pattern Matching Cell / Floating-Gate MOS-FET / Inference VLSI Chip / Object Recognition System / Graph Matching / Clique Finding / 3-D Object Recognition / 高並列多値演算回路 / 線形ディジタルシステム / 超微細集積回路 / 微小クリティカルパス遅延 / 微小配線遅延 / デバイスモデルベーストエレクトロニクス / 多値集積デバイス / 多値情報処理 / 専用VLSIプロセッサ / 空間的並列構造プロセッサ / Intelligent Integrated Systems / Highly Parallel Multiple-Valued Arithmetic and Logic Circuits / Linear Digital System / Ultra Fine Integrated Circuits / Small Critical-Delay Path / Small Interconnection Delay / Device-Model Based Electronics / Multiple-Valued Integrated Devices / 線形演算回路 / リ-ド・マラ-展開 / 多値冗長符号 / 多値電流モード集積回路 / クリティカルパス遅延最小化 / 超高並列演算システム / リ-ドマラ-展開 / Highly Parallel Arithmetic and Logic Circuit / Linear Digital Circuit / Critical-Path Minimization / Redundant Coding / Multiple-Valued Current-Mode Integrated Circuit / Low Power Multiple-Valued Integrated Circuit / 危険検出ルール / フローティングゲートMOSFET / 高安全自動車 / 多値CAM / 大小比較演算 / 多値しきい演算 / 多値記憶 / 1トランジスタセル / 多値連想メモリ / フローティングゲートMOSトランジスタ / 非数値データ処理 / Danger-Detection Rules / Floating-Gate MOS Transistor / Highly Safe Vehicle / Multiple-Valued CAM / Magnitude Comparison / Multiple-Valued Threshold Operation / Multiple-Valued Memory / One-Transistor CAM Cell / リアルワールド応用知能集積システム / ハイレベルシンセシス / スケジューリング / アロケーション / ロジックインメモリアーキテクチャ構造 / 空間並列構造 / 相互結合回路網 / ロジックインメモリアーキテクチャ / 並列構造VLSIプロセッサ / 演算遅れ時間最小化 / 並列データ供給 / 衝突チェックVLSIプロセッサ / ステレオビジョンVLSIプロセッサ / パイプライン並列構造 / 3次元計測VLSIプロセッサ / Intelligent Integrated Systems for Real-World Applications / High-Level Synthesis / Scheduling / Allocation / Logic-In-Memory Architecture / Spacially Parallel Structure / Interconnection Network / セルフチェッキング回路 / 算術演算回路 / 非同期式多値VLSI / Reed-Muller展開 / 分割理論 / 非同期式多値演算回路 / 電流モード多値集積回路 / 電流源制御 / 非同期多値演算回路 / 電力源制御 / Self Checking Circuit / Highly-Parallel Arithmetic and Logic Circuit / Asynchronous Multiple-Valued VLSI / Partition Theory / フルソースカップルドロジック / 細粒度パイプライン / 強誘電体デバイス / 不揮発ロジックインメモリ / 電圧・電流ハイブリッドモード多値集積回路 / ドミノ理論 / パストランジスタ理論 / ソース結合形理論 / 多値VLSIプロセッサ / パイプライン処理 / ステレオビジョンプロセッサ / Source-Coupled Logic / Fine-Grain Pipelinign / Ferro-Electric Device / Nonvolatile Logic-in-Mmemory / 高速シリアル通信 / 細粒度パワーゲーティング / 4値レベル信号 / PLL/DLLレス / 同期/非同期インタフェース / 同期/非同期インタフェース / 通信方式 / シリアル通信 / 低消費電力化 / クロック埋め込み Less
  • Research Projects

    (24 results)
  • Research Products

    (196 results)
  • Co-Researchers

    (29 People)
  •  脳型コンピューティング向けダーク・シリコンロジックLSIの基盤技術開発Principal Investigator

    • Principal Investigator
      羽生 貴弘
    • Project Period (FY)
      2016
    • Research Category
      Grant-in-Aid for Scientific Research (A)
    • Research Field
      Computer system
    • Research Institution
      Tohoku University
  •  脳型コンピューティング向けダーク・シリコンロジックLSIの基盤技術開発Principal InvestigatorOngoing

    • Principal Investigator
      羽生 貴弘
    • Project Period (FY)
      2016 – 2020
    • Research Category
      Grant-in-Aid for Scientific Research (S)
    • Research Field
      Computer system
    • Research Institution
      Tohoku University
  •  Study on Implementation for Greatly Reducing Power Dissipation of Serial Communication Mechanisms

    • Principal Investigator
      YONEDA Tomohiro
    • Project Period (FY)
      2015 – 2017
    • Research Category
      Grant-in-Aid for Scientific Research (A)
    • Research Field
      Communication/Network engineering
    • Research Institution
      National Institute of Informatics
  •  Nonvolatile-device-based PVT-variation-resilient VLSI systemPrincipal Investigator

    • Principal Investigator
      HANYU TAKAHIRO
    • Project Period (FY)
      2010 – 2013
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      Electron device/Electronic equipment
    • Research Institution
      Tohoku University
  •  Implementation of a High-Speed LDPC Decoder LSI Based on a Multiple-Valued Full-Duplex Data-Transfer TechniquePrincipal Investigator

    • Principal Investigator
      HANYU Takahiro
    • Project Period (FY)
      2006 – 2008
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      Computer system/Network
    • Research Institution
      Tohoku University
  •  不揮発性デバイスに基づくクイックオンVLSIシステムの構成Principal Investigator

    • Principal Investigator
      羽生 貴弘
    • Project Period (FY)
      2006 – 2007
    • Research Category
      Grant-in-Aid for Exploratory Research
    • Research Field
      Computer system/Network
    • Research Institution
      Tohoku University
  •  Implementation of a High-Speed Asynchronous Data Transfer VLSI Based on Bidirectional Current-Mode Multiple-Valued Circuit TechniquesPrincipal Investigator

    • Principal Investigator
      HANYU Takahiro
    • Project Period (FY)
      2003 – 2005
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Research Field
      Computer system/Network
    • Research Institution
      Tohoku University
  •  多値技術に基づく高速データ転送とそのマルチメディアVLSIプロセッサへの応用Principal Investigator

    • Principal Investigator
      羽生 貴弘
    • Project Period (FY)
      2002
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Research Field
      計算機科学
    • Research Institution
      Tohoku University
  •  Implementation of a Transfer-Bottleneck-Free Multiple-Valued Logic-in-Memory VLSI and Its ApplicationPrincipal Investigator

    • Principal Investigator
      HANYU Takahiro
    • Project Period (FY)
      2001 – 2004
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      計算機科学
    • Research Institution
      Tohoku University
  •  Interconnection-Bottleneck-Free VLSI System Based on Dual-Rail Multiple-Valued Digital Computing

    • Principal Investigator
      KAMEYAMA MICHITAKA
    • Project Period (FY)
      2000 – 2002
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      計算機科学
    • Research Institution
      Tohoku University
  •  Implementation of a High-Performance Multiple-Valued Current-Mode VLSI System with Low-Power and Highly Reliable CapabilitiesPrincipal Investigator

    • Principal Investigator
      HANYU Takahiro
    • Project Period (FY)
      2000 – 2002
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Research Field
      計算機科学
    • Research Institution
      Tohoku University
  •  高速・低電力電流モード多値算術演算VLSI回路の試作Principal Investigator

    • Principal Investigator
      羽生 貴弘
    • Project Period (FY)
      1998 – 1999
    • Research Category
      Grant-in-Aid for Encouragement of Young Scientists (A)
    • Research Field
      計算機科学
    • Research Institution
      Tohoku University
  •  MULTIPLE-VALUED PROCESSOR FOR INTELLIGENT INTEGRATED SYSTEMPrincipal Investigator

    • Principal Investigator
      HANYU Takahiro
    • Project Period (FY)
      1997 – 1998
    • Research Category
      Grant-in-Aid for international Scientific Research
    • Research Field
      計算機科学
    • Research Institution
      TOHOKU UNIVERSITY
  •  High-Level Synthesis of High-Performance VLSI Processors for Intelligent Integrated System

    • Principal Investigator
      KAMEYAMA Michitaka
    • Project Period (FY)
      1997 – 1999
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      計測・制御工学
    • Research Institution
      TOHOKU UNIVERSITY
  •  Development of a Chip Family for Ultra-Highly-Parallel Multiple-Valued Integrated Circuits and Its Applications

    • Principal Investigator
      KAMEYAMA Michitaka
    • Project Period (FY)
      1997 – 1999
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      計算機科学
    • Research Institution
      TOHOKU UNIVERSITY
  •  Implementation of a One-Transistor Multiple-Valued Content-Addressalbe Memory and Its ApplicationPrincipal Investigator

    • Principal Investigator
      HANYU Takahiro
    • Project Period (FY)
      1997 – 2000
    • Research Category
      Grant-in-Aid for Scientific Research (B).
    • Research Field
      計算機科学
    • Research Institution
      Tohoku Univesity
  •  超並列多値連想メモリに関する研究Principal Investigator

    • Principal Investigator
      羽生 貴弘
    • Project Period (FY)
      1996
    • Research Category
      Grant-in-Aid for Encouragement of Young Scientists (A)
    • Research Field
      計算機科学
    • Research Institution
      Tohoku University
  •  Study on Multiple-Valued VLSI Processors for a Highly Safe Intelligent Vehicle

    • Principal Investigator
      KAMEYAMA Michitaka
    • Project Period (FY)
      1995 – 1996
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      計算機科学
    • Research Institution
      Tohoku University
  •  次世代デバイスに基づく高性能多値VLSIシステムの構成に関する研究Principal Investigator

    • Principal Investigator
      羽生 貴弘
    • Project Period (FY)
      1994
    • Research Category
      Grant-in-Aid for Encouragement of Young Scientists (A)
    • Research Field
      計算機科学
    • Research Institution
      Tohoku University
  •  Ultra-Highly-Parallel Arithmetic and Logic Circuits and Their Multiple-Valued Integration

    • Principal Investigator
      KAMEYAMA Michitaka
    • Project Period (FY)
      1994 – 1996
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      計算機科学
    • Research Institution
      Tohoku University, Graduate School of Information Sciences
  •  ロボットビジョン用特徴抽出VLSIプロセッサシステムの構成に関する研究Principal Investigator

    • Principal Investigator
      羽生 貴弘
    • Project Period (FY)
      1993
    • Research Category
      Grant-in-Aid for Encouragement of Young Scientists (A)
    • Research Field
      計測・制御工学
    • Research Institution
      Tohoku University
  •  Study on Post-Binary ULSI Sstems

    • Principal Investigator
      KAMEYAMA Michitaka
    • Project Period (FY)
      1992 – 1993
    • Research Category
      Grant-in-Aid for international Scientific Research
    • Research Institution
      Tohoku University, Graduate School of Information Sciences
  •  IMPLEMENTATION OF ULTRA-HIGH-SPEED INFERENCE HARDWARE ENGINE BASED ON 4-VALUED CMOS INTEGRATED CIRCUITS AND ITS APPLICATION

    • Principal Investigator
      HIGUCHI Tatsuo
    • Project Period (FY)
      1991 – 1992
    • Research Category
      Grant-in-Aid for Developmental Scientific Research (B)
    • Research Field
      計測・制御工学
    • Research Institution
      TOHOKU UNIVERSITY
  •  BASIC STUDY ON HIGH-PERFORMANCE MULTIPLE-VALUED SUPER CHIP FOR INTELLIGENT ROBOTS

    • Principal Investigator
      HIGUCHI Tatsuo
    • Project Period (FY)
      1989 – 1991
    • Research Category
      Grant-in-Aid for General Scientific Research (B)
    • Research Field
      計測・制御工学
    • Research Institution
      TOHOKU UNIVERSITY

All 2020 2019 2018 2017 2016 2013 2012 2011 2010 2009 2008 2007 2006 2005 2003 2002 2001

All Journal Article Presentation Book

  • [Book] Beyond MRAM: Nonvolatile Logic-in-Memory VLSI, Chapter 7 in Book: Introduction to Magnetic Random-Access Memory2016

    • Author(s)
      Takahiro Hanyu, Tetsuo Endoh, Shoji Ikeda, Tadahiko Sugibayashi, Naoki Kasai, Daisuke Suzuki, Masanori Natsui, Hiroki Koike, and Hideo Ohno
    • Total Pages
      264
    • Publisher
      Wiley-IEEE Press
    • ISBN
      9781119009740
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Journal Article] Design of an MTJ-based Nonvolatile Multi-context Ternary Content-Addressable Memory2020

    • Author(s)
      N. Onizawa, R. Arakawa, and T. Hanyu
    • Journal Title

      Journal of Applied Logics

      Volume: 7 Pages: 89-105

    • Peer Reviewed / Open Access
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Journal Article] Networked Power-Gated MRAMs for Memory-Based Computing2018

    • Author(s)
      J.-P. Diguet, N. Onizawa, M. Rizk, M. J. Sepulveda, A. Baghdadi, and T. Hanyu
    • Journal Title

      IEEE Transactions on Very Large Scale Integration (VLSI) Systems

      Volume: 26 Pages: 2696-2708

    • DOI

      10.1109/tvlsi.2018.2856458

    • Peer Reviewed / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Journal Article] MTJ-Based Asynchronous Circuits for Re-Initialization Free Computing against Power Failures2018

    • Author(s)
      N. Onizawa, M. Imai, T. Yoneda, and T. Hanyu
    • Journal Title

      Microelectronics Journal

      Volume: 82 Pages: 46-61

    • DOI

      10.1016/j.mejo.2018.10.012

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Journal Article] Fabrication of an MTJ-Based Nonvolatile Logic-in-Memory LSI with Content-Aware Write Error Masking Scheme Achieving 92% Storage Capacity and 79% Power Reduction2017

    • Author(s)
      Masanori Natsui, Akira Tamakoshi, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: 56, 4S

    • Peer Reviewed / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Journal Article] Design of a Variation-Resilient Single-Ended Nonvolatile 6-Input Lookup Table Circuit with a Redundant-MTJ-Based Active Load for Smart IoT Applications2017

    • Author(s)
      D. Suzuki, M. Natsui, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu
    • Journal Title

      Institute of Engineering Technology (IET), Electronics Letters

      Volume: 53, 7 Pages: 456-458

    • Peer Reviewed / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Journal Article] Soft/Write-Error Resilient CMOS/MTJ Nonvolatile Flip-Flop Based on Majority-Decision Shared Writing2017

    • Author(s)
      Naoya Onizawa and Takahiro Hanyu
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: 56, 4S

    • Peer Reviewed / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Journal Article] Design of a Low-Power Nonvolatile Flip-Flop Using 3-Terminal Magnetic-Tunnel-Junction-Based Self-Terminated Mechanism2017

    • Author(s)
      Daisuke Suzuki and Takahiro Hanyu
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: 56, 4S

    • Peer Reviewed / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Journal Article] Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing2016

    • Author(s)
      T. Hanyu, T. Endoh, D. Suzuki, H. Koike, Y. Ma, N. Onizawa, M. Natsui, S. Ikeda, and H. Ohno
    • Journal Title

      Proc. IEEE

      Volume: 104 Pages: 1843-1863

    • DOI

      10.1109/jproc.2016.2574939

    • Peer Reviewed / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-26700003, KAKENHI-PROJECT-16K12494, KAKENHI-PROJECT-16H06300
  • [Journal Article] Analog-to-Stochastic Converter Using Magnetic Tunnel Junction Devices for Vision Chips2016

    • Author(s)
      N. Onizawa, D. Katagiri, W. J. Gross, and T. Hanyu
    • Journal Title

      IEEE Trans. on Nanotechnology

      Volume: 15 Pages: 705-714

    • DOI

      10.1109/tnano.2015.2511151

    • Peer Reviewed / Acknowledgement Compliant / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-26700003, KAKENHI-PROJECT-16K12494, KAKENHI-PROJECT-16H06300
  • [Journal Article] Design of Process-Variation-Resilient Analog Basic Components Using Magnetic-Tunnel-Junction Devices2013

    • Author(s)
      M. Natsui and T. Hanyu
    • Journal Title

      Journal of Multiple-Valued Logic and Soft Computing

      Volume: Vol.21, No.5-6 Pages: 597-608

    • URL

      http://www.oldcitypublishing.com/pdf/3498

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Journal Article] Design and Evaluation of a Differential Switching Gate for Low-Voltage Applications2013

    • Author(s)
      M. Natsui, K. Kashiuchi, and T. Hanyu
    • Journal Title

      43rd IEEE International Symposium on Multiple-Valued Logic (ISMVL2013)

      Pages: 147-151

    • DOI

      10.1109/ismvl.2013.23

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Journal Article] MTJ/MOS-Hybrid Logic-Circuit Design Flow for Nonvolatile Logic-in-Memory LSI2013

    • Author(s)
      M. Natsui, N. Sakimura, T. Sugibayashi, and T. Hanyu
    • Journal Title

      2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

      Pages: 105-108

    • DOI

      10.1109/iscas.2013.6571793

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Journal Article] Low-Energy Pipelined Multiple-Valued Current-Mode Circuit Based on Current-Level Control Technique2012

    • Author(s)
      M.Natsui, T.Arimitsu, T.Hanyu
    • Journal Title

      Journal of Multiple-Valued Logic and Soft Computing

      Volume: (未定)(掲載確定)

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Journal Article] Low-Energy Pipelined Multiple-Valued Current-Mode Circuit Based on Current-Level Control Technique2012

    • Author(s)
      M. Natsui, T. Arimitsu and T. Hanyu
    • Journal Title

      Journal of Multiple-Valued Logic and Soft Computing

      Volume: Vol.19, No.1-3 Pages: 219-231

    • URL

      http://www.oldcitypublishing.com/pdf/2910

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Journal Article] Process-Variation-Resilient OTA Using MTJ-Based Multi-Level Resistance Control2012

    • Author(s)
      M.Natsui, T.Nagashima, T.Hanyu
    • Journal Title

      Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic

      Volume: (掲載確定)

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Journal Article] Process-Variation-Resilient OTA Using MTJ-Based Multi-Level Resistance Control2012

    • Author(s)
      M. Natsui, T. Nagashima, and T. Hanyu
    • Journal Title

      42nd IEEE International Symposium on Multiple-Valued Logic (ISMVL2012)

      Pages: 214-219

    • DOI

      10.1109/ismvl.2012.52

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Journal Article] Variation-Resilient Current-Mode Logic Circuit Design Using MTJ Devices2012

    • Author(s)
      Y.Kim, M.Natsui, T.Hanyu
    • Journal Title

      Proceedings of 2012 IEEE International Symposium on Circuits & Systems

      Volume: (掲載確定)

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Journal Article] Scalable Serial-Configuration Scheme for MTJ/MOS-Hybrid Variation-Resilient VLSI System2012

    • Author(s)
      M. Natsui and T. Hanyu
    • Journal Title

      10th IEEE International NEWCAS Conference (NEWCAS2012)

      Pages: 97-100

    • DOI

      10.1109/newcas.2012.6328965

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Journal Article] Variation-Resilient Current-Mode Logic Circuit Design Using MTJ Devices2012

    • Author(s)
      Y. Kim, M. Natsui and T. Hanyu
    • Journal Title

      2012 IEEE International Symposium on Circuits & Systems (ISCAS2012)

      Pages: 2705-2708

    • DOI

      10.1109/iscas.2012.6271866

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Journal Article] MTJ-Based Optimal Vth-Tuning Technique for a Process-Variation-Aware VLSI processor2011

    • Author(s)
      M.Natsui, Y.Kim, T.Hanyu
    • Journal Title

      Proceedings of the 56th Magnetism and Magnetic Materials Conference

      Pages: 480-481

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Journal Article] MTJ-Based Optimal Vth-Tuning Technique for a Process-Variation-Aware VLSI processor2011

    • Author(s)
      M. Natsui, Y. Kim and T. Hanyu
    • Journal Title

      The 56th Magnetism and Magnetic Materials Conference (MMM2011)

      Pages: 480-481

    • URL

      http://www.magnetism.org/

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Journal Article] Design of High-Throughput Fully-Parallel LDPC Decoders Based on Wire Partitioning2009

    • Author(s)
      Naoya Onizawa, Takahiro Hanyu, and Vincent C. Gaudet
    • Journal Title

      IEEE Trans. on VLSI Systems (採録決定)

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving2009

    • Author(s)
      N. Onizawa, T. Hanyu and V. C. Gaudet
    • Journal Title

      IEICE Trans. Electron (掲載決定)

    • NAID

      10026822478

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] Design of High-Throughput Fully-Parallel LDPC Decoders Based on Wire Partitioning2009

    • Author(s)
      N. Onizawa, T. Hanyu and V.C. Gaudet
    • Journal Title

      IEEE Trans. on VLSI Systems (掲載決定)

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving Date of Evaluation2009

    • Author(s)
      Naoya Onizawa, Takahiro Hanyu, and Vincent C. Gaudet
    • Journal Title

      IEICE Trans. Electron (採録決定)

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] Highly Reliable Multiple-Valued Current-Mode Comparator Based on Active-Load Dual-Rail Operation2008

    • Author(s)
      M. Miura and T. Hanyu
    • Journal Title

      IEICE Trans. Electron Vol.E91-C, No.4

      Pages: 589-594

    • NAID

      10026817589

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] Power-Aware Asynchronous Peer-to-Peer Duplex Communication System Based on Multiple-Valued One-Phase Signaling2008

    • Author(s)
      K. Mizusawa, N. Onizawa and T. Hanyu
    • Journal Title

      IEICE Trans. Electron Vol.E91-C, No.4

      Pages: 581-588

    • NAID

      10026817575

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] 多値電流モード非同期データ転送方式に基づくLDPCデコーダLSIの実現2007

    • Author(s)
      鬼沢 直哉, 羽生 貴弘
    • Journal Title

      電子情報通信学会総合大会講演論文集

    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] Design of a Fluid Analysis Simulator Based on Lattice Gas Cellular Automaton2007

    • Author(s)
      D.Suzuki, T.Hanyu
    • Journal Title

      Proc. 4th International Symposium on System Construction of Global-Network-Oriented Information Electronics 4

      Pages: 330-331

    • Data Source
      KAKENHI-PROJECT-18650009
  • [Journal Article] 電流モード多値回路の信頼性評価2007

    • Author(s)
      高橋 知宏, 羽生 貴弘
    • Journal Title

      電子情報通信学会総合大会講演論文集

    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] トンネル磁気抵抗デバイスによる論理集積回路-不揮発性が拓く次世代ロジックLSIパラダイム-2007

    • Author(s)
      羽生貴弘
    • Journal Title

      応用物理 第76巻,第12号

      Pages: 1388-1393

    • NAID

      10020007373

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18650009
  • [Journal Article] 流体解析用格子ガスセルラアレーVLSIのFPGA実現2007

    • Author(s)
      鈴木 大輔, 羽生 貴弘
    • Journal Title

      電子情報通信学会総合大会講演論文集

    • Data Source
      KAKENHI-PROJECT-18650009
  • [Journal Article] Magnetic Tunnel Junctions for Spintronic Memories and Beyond2007

    • Author(s)
      Shoji Ikeda, Jun Hayakawa, Young Min Lee, Fumihiro Matsukura, Yuzo Ohno, Takahiro Hanyu, and Hideo Ohno
    • Journal Title

      IEEE Transactions on Electron Devices Vol.54, No.5

      Pages: 991-1002

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18650009
  • [Journal Article] TMRロジックに基づく低消費電力FPGAの構成と評価2007

    • Author(s)
      渡邊康広, 羽生貴弘
    • Journal Title

      電子情報通信学会「多値論理とその応用」第二種研究会技術報告 MVL-07・1

      Pages: 1-7

    • Data Source
      KAKENHI-PROJECT-18650009
  • [Journal Article] Implementation of a High-Throughput LDPC Decoder Chip Using an Asynchronous Interleaving Scheme2007

    • Author(s)
      N.Onizawa, T.Hanyu
    • Journal Title

      Proc. 4th International Symposium on System Construction of Global-Network-Oriented Information Electronics 4

      Pages: 398-399

    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] Design and Evaluation of a 54x54-bit Multiplier Based on Differential-Pair Circuitry2007

    • Author(s)
      Akira Mochizuki, Hirokatsu Shirahama and Takahiro Hanyu
    • Journal Title

      IEICE Trans. on Electronics E90-C・4

      Pages: 683-691

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] Novel Circuit Techniques for High-Speed Intra-Chip Communication2007

    • Author(s)
      T.Hanyu, T.Takahashi, S.Matsunaga
    • Journal Title

      Proc. 4th International Symposium on System Construction of Global-Network-Oriented Information Electronics 4

      Pages: 134-139

    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] Design and Evaluation of a 54x54-bit Multiplier Based on Differential-Pair Circuitry2007

    • Author(s)
      A. Mochizuki, H. Shirahama and T. Hanyu
    • Journal Title

      IEICE Trans. on Electronics Vol.E90-C, No.4

      Pages: 683-691

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] A Simplex/Duplex-Compatible System for Asynchronous Peer-to-Peer Communication Using One-phase Signaling2007

    • Author(s)
      T.Takahashi, T.Hanyu
    • Journal Title

      Proc. 4th International Symposium on System Construction of Global-Network-Oriented Information Electronics 4

      Pages: 338-339

    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] Nonvolatile Static Latch Based on Ferroelectric Defferential Logic2007

    • Author(s)
      S.Matsunaga, T.Hanyu
    • Journal Title

      Proc. 4th International Symposium on System Construction of Global-Network-Oriented Information Electronics 4

      Pages: 334-335

    • Data Source
      KAKENHI-PROJECT-18650009
  • [Journal Article] Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic2007

    • Author(s)
      S.Matsunaga, T.Hanyu, H.Kimura, T.Nakamura, H.Takasu
    • Journal Title

      Proc. Asia and South Pacific Design Automation Conf.

      Pages: 116-117

    • Data Source
      KAKENHI-PROJECT-18650009
  • [Journal Article] Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic2006

    • Author(s)
      N.Onizawa, T.Hanyu
    • Journal Title

      IEICE Trans. on Electronics E89-C? 11

      Pages: 1591-1597

    • NAID

      110007538694

    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] 差動ロジックに基づく高性能VLSIの展望2006

    • Author(s)
      望月明, 羽生貴弘
    • Journal Title

      多値論理研究ノート 29

    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] 多値2線符号化に基づく双方向非同期データ転送LSI の高性能化2006

    • Author(s)
      水澤一泰, 高橋知宏, 羽生貴弘
    • Journal Title

      平成18年度電気関係学会東北支部連合大会講演論文集

      Pages: 342-342

    • NAID

      130005444266

    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] TMRロジックとその応用2006

    • Author(s)
      羽生貴弘, 望月明, 渡邊康広
    • Journal Title

      応用電子物性分科会誌 12・4

      Pages: 154-159

    • NAID

      10024270241

    • Data Source
      KAKENHI-PROJECT-18650009
  • [Journal Article] Ferroelectric-Based Logic Circuit and Its Application to Content-Addressable Memory2006

    • Author(s)
      H.Kimura, Y.Fujimori, T.Nakamura, H.Takasu, T.Hanyu
    • Journal Title

      Proceeding of IEEE The 2006 International Meeting for Future Electron Devices

      Pages: 41-42

    • Data Source
      KAKENHI-PROJECT-18650009
  • [Journal Article] Implementation of a High-Speed Asynchronous Data-Transfer Chip Based on Multiple-Valued Current-Signal Multiplexing2006

    • Author(s)
      T.Takahashi, T.Hanyu
    • Journal Title

      IEICE Trans. on Electronics E89-C? 11

      Pages: 1598-1604

    • NAID

      110007538697

    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] TMR-Based Differential Logic for Vt-Variation Compansation2006

    • Author(s)
      A.Hirosaki, M.Miura, A.Mochizuki, T.Hanyu
    • Journal Title

      Proc. 3rd Workshop of Yeungnum Univ. and Tohoku Univ.

      Pages: 51-52

    • Data Source
      KAKENHI-PROJECT-18650009
  • [Journal Article] Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits2006

    • Author(s)
      A.Mochizuki, T.Kitamura, H.Shirahama, T.Hanyu
    • Journal Title

      Proc. 36th IEEE International Symposium on Multiple-Valued Logic 36(CD-ROM版のため頁番号なし)

    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] Automatic Place and Route Scheme in Multiple-Valued Current-Mode Circuit Design2006

    • Author(s)
      T.Nagai, T.Takahashi, N.Onizawa, T.Hanyu
    • Journal Title

      Proc. 3rd Workshop of Yeungnum Univ. and Tohoku Univ. 3

      Pages: 57-58

    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] 2線差動論理に基づくノイズフリー多値集積回路2006

    • Author(s)
      三浦 成友, 望月 明, 羽生 貴弘
    • Journal Title

      平成18年度電気関係学会東北支部連合大会講演論文集

      Pages: 341-341

    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic2006

    • Author(s)
      A. Mochizuki, H. Shirahama and T. Hanyu
    • Journal Title

      IEICE Trans. on Electronics Vol.E89-C, No.11

      Pages: 1575-1580

    • NAID

      110007538696

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] Highly reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic2006

    • Author(s)
      A.Mochizuki, T.Hanyu
    • Journal Title

      Proc. 36th IEEE International Symposium on Multiple-Valued Logic 36(CD-ROM版のため頁番号なし)

    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] Design of a Fluid Analysis Simulator Based on Lattice Gas Cellular Automaton2006

    • Author(s)
      D.Suzuki, T.Hanyu
    • Journal Title

      Proc. 3rd Workshop of Yeungnum Univ. and Tohoku Univ.

      Pages: 132-134

    • Data Source
      KAKENHI-PROJECT-18650009
  • [Journal Article] Implementation of a High-Speed Asynchronous Data-Transfer Chip Based on Multiple-Valued Current-Signal Multiplexing2006

    • Author(s)
      T. Takahashi, T. Hanyu
    • Journal Title

      IEICE Trans. on Electronics Vol. E89-C, No.11

      Pages: 1598-1604

    • NAID

      110007538697

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] TMRロジックに基づく低消費電力TCAMの構成2006

    • Author(s)
      木村圭, 渡邊康広, 羽生貴弘
    • Journal Title

      平成18年度電気関係学会東北支部連合大会講演論文集 1F7

      Pages: 206-206

    • NAID

      130005444064

    • Data Source
      KAKENHI-PROJECT-18650009
  • [Journal Article] Low-power Latch Based on Dynamic Differential Logic2006

    • Author(s)
      H.Shirahama, A.Mochizuki, T.Hanyu
    • Journal Title

      Proc. 3rd Workshop of Yeungnum Univ. and Tohoku Univ 3

      Pages: 138-140

    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic2006

    • Author(s)
      N. Onizawa and T. Hanyu
    • Journal Title

      IEICE Trans. on Electronics Vol.E89-C, No.11

      Pages: 1591-1597

    • NAID

      110007538694

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic2006

    • Author(s)
      A.Mochizuki, H.Shirahama, T.Hanyu
    • Journal Title

      IEICE Trans. on Electronics E89-C・11

      Pages: 1575-1580

    • NAID

      110007538696

    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] 多値2 線符号化に基づく高性能非同期データ転送VLSI2006

    • Author(s)
      高橋知宏, 水澤一泰, 羽生貴弘
    • Journal Title

      電子情報通信学会「集積回路研究会」技術報告 106・315

      Pages: 37-42

    • NAID

      10018637790

    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] 隣接データの類似性に着目した高速LDPC復号化とその評価2006

    • Author(s)
      池田智和, 鬼沢直哉, 羽生貴弘
    • Journal Title

      平成18年度電気関係学会東北支部連合大会講演論文集

      Pages: 70-70

    • NAID

      130005444329

    • Data Source
      KAKENHI-PROJECT-18300012
  • [Journal Article] Non-Volatile Logic-in-Memory Circuit and Its Application2005

    • Author(s)
      Takahiro Hanyu
    • Journal Title

      Proc.2nd International Symposium on System Construction of Global-Network-Oriented Information Electronics 2

      Pages: 99-102

    • Data Source
      KAKENHI-PROJECT-13558026
  • [Journal Article] Multiple-Valued Dynamic Source-Coupled Logic2003

    • Author(s)
      T.Hanyu
    • Journal Title

      IEEE International Symposium on Multiple-Valued Logic 33

      Pages: 207-212

    • NAID

      120001182151

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current-Mode Logic2003

    • Author(s)
      T.Hanyu
    • Journal Title

      IEEE Int.Symposium on Multiple-Valued Logic 33

      Pages: 99-104

    • NAID

      120001182150

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current-Mode Logic2003

    • Author(s)
      T.Hanyu
    • Journal Title

      IEEE International Symposium on Multiple-Valued Logic 33

      Pages: 99-104

    • NAID

      120001182150

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] Multiple-Valued Dynamic Source-Coupled Logic2003

    • Author(s)
      T.Hanyu
    • Journal Title

      IEEE Int.Symposium on Multiple-Valued Logic 33

      Pages: 207-212

    • NAID

      120001182151

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-15500029
  • [Journal Article] Ferroelectric-Based Functional Pass-Gate for Fine-Grain Pipelined VLSI Computation2002

    • Author(s)
      T.Hanyu
    • Journal Title

      Digest of Technical Papers, IEEE International Solid-State Circuits Conference(ISSCC)

      Pages: 208-209

    • NAID

      120002338721

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-13558026
  • [Journal Article] Ferroelectric-Based Functional Pass-Gate for Fine-Grain Pipelined VLSI Computation2002

    • Author(s)
      T.Hanyu
    • Journal Title

      Digest of Technical Papers, IEEE International Solid-State Circuits Conference (ISSCC) 45

      Pages: 208-209

    • NAID

      120002338721

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-13558026
  • [Journal Article] Challenge of a Multiple-Valued Technology in Recent Deep-Submicron VLSI2001

    • Author(s)
      T.Hanyu
    • Journal Title

      IEEE 31st International Symposium on Multiple-Valued Logic 31

      Pages: 241-244

    • NAID

      120002338720

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-13558026
  • [Journal Article] Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits2001

    • Author(s)
      T.Hanyu
    • Journal Title

      IEEE 31st International Symposium on Multiple-Valued Logic 31

      Pages: 167-172

    • NAID

      120002338719

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-13558026
  • [Journal Article] Challenge of a Multiple-Valued Technology in Recent Deep-Submicron VLSI2001

    • Author(s)
      T.Hanyu
    • Journal Title

      IEEE 31st International Symposium on Multiple-Valued Logic

      Pages: 241-244

    • NAID

      120002338720

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-13558026
  • [Journal Article] Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits2001

    • Author(s)
      T.Hanyu
    • Journal Title

      IEEE 31st International Symposium on Multiple-Valued Logic

      Pages: 167-172

    • NAID

      120002338719

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-13558026
  • [Presentation] Multi-Context TCAM Based Selective Computing Architecture for a Low-Paper NN2019

    • Author(s)
      Ren Arakawa, Naoya Onizawa, Jean-Philippe Diguet, and Takahiro Hanyu
    • Organizer
      26th IEEE International Conference on Electrocnis, Circuits & Systems (ICECS)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Presentation] Approximate Computing応用高性能マルチコンテキスト(MC-)TCAMの構成2019

    • Author(s)
      荒川怜、鬼沢直哉、羽生貴弘
    • Organizer
      2019年度 電気関係学会東北支部連合大会
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Presentation] ポストCMOS回路技術が拓く脳型LSIの挑戦2019

    • Author(s)
      羽生隆弘
    • Organizer
      日本磁気学会・第6回岩崎コンファランス
    • Invited
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Presentation] Stochastic computing for brainware LSI2019

    • Author(s)
      N. Onizawa, W. J. Gross, and T. Hanyu
    • Organizer
      IEEE ASYNC'19 Special Session
    • Invited / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Presentation] Prospects of Nonvolatile Logic LSI Using MTJ/MOS-Hybrid Circuitry and Its Application2018

    • Author(s)
      T. Hanyu
    • Organizer
      2018 International Conference on Solid State Devices and Materials (SSDM2018)
    • Invited / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Presentation] Minimum Power Supply Asynchronous Circuits for Re-initialization Free Computing2018

    • Author(s)
      M. Imai, N. Onizawa, T. Hanyu, and T. Yoneda
    • Organizer
      21st Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Presentation] Challenge of Spintronic-Device-Based Nonvolatile Logic-in-Memory Architecture for Internet-of-Things Applications2018

    • Author(s)
      T. Hanyu
    • Organizer
      世界トップレベル研究拠点(材料科学・スピントロニクス)合同キックオフシンポジウム
    • Invited
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Presentation] Challenge of Spintronics-Based Nonvolatile Logic LSI and Its Possibility2018

    • Author(s)
      T. Hanyu
    • Organizer
      Tohoku/SG-Spin workshop on Spintronics
    • Invited / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Presentation] ポストCMOS回路技術が拓くAIハードウェアの挑戦2018

    • Author(s)
      羽生貴弘
    • Organizer
      デザインガイア2018
    • Invited
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Presentation] Challenge of an MTJ-Based Non-Volatile Logic LSI for Internet-of-Things Application2018

    • Author(s)
      T. Hanyu
    • Organizer
      Workshop on Next Generation Computing System
    • Invited / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Presentation] Design of a Low-Power MTJ-Based True Random Number Generator Using a Multi Voltage/Current Convertor2018

    • Author(s)
      S. Mukaida, N. Onizawa, T. Hanyu
    • Organizer
      ISMVL2018
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Presentation] スピントロニクスが拓く新しいロジックLSIの展望2018

    • Author(s)
      羽生貴弘,鈴木大輔,鬼沢直哉,夏井雅典,遠藤哲郎,大野英男
    • Organizer
      CSRN年度末シンポジウム
    • Invited
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Presentation] Three-Terminal MTJ-Based Nonvolatile Logic Circuits with Self-Terminated Writing Mechanism for Ultra-Low-Power VLSI Processor2017

    • Author(s)
      T. Hanyu, D. Suzuki, N. Onizawa, and M. Natsui
    • Organizer
      Design, Automation & Test in Europe (DATE)
    • Invited / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Presentation] MTJ-Based Asynchronous Circuits for Re-initialization Free Computing against Power Failures2017

    • Author(s)
      N. Onizawa, M. Imai, T. Hanyu, and T. Yoneda
    • Organizer
      23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Presentation] Power-Gated Single-Track Asynchronous Circuits Using Three-Terminal MTJ-Based Nonvolatile Devices for Energy Harvesting Systems2016

    • Author(s)
      Tomohiro Yoneda, Naoya Onizawa, Masashi Imai, Takahiro Hanyu,
    • Organizer
      Async2016 Fresh ideas track
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Presentation] A Soft/Write-Error Resilient CMOS/MTJ Nonvolatile Flip-Flop Based on Majority-Decision Shared Writing2016

    • Author(s)
      Naoya Onizawa and Takahiro Hanyu
    • Organizer
      2016 International Conference on Solid State Devices and Materials (SSDM2016)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Presentation] A Self-Terminated Energy-Efficient Nonvolatile Flip-Flop Using 3-terminal Magnetic Tunnel Junction Device2016

    • Author(s)
      Daisuke Suzuki and Takahiro Hanyu
    • Organizer
      2016 International Conference on Solid State Devices and Materials (SSDM2016)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Presentation] Highly Reliable MTJ-Based Motion-Vector Prediction Unit with Dynamic Write Error Masking Scheme2016

    • Author(s)
      Masanori Natsui, Akira Tamakoshi, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu
    • Organizer
      2016 International Conference on Solid State Devices and Materials (SSDM2016)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H06300
  • [Presentation] Design and Evaluation of a Differential Switching Gate for Low-Voltage Applications2013

    • Author(s)
      M. Natsui, K. Kashiuchi, and T. Hanyu
    • Organizer
      43rd IEEE International Symposium on Multiple-Valued Logic (ISMVL2013)
    • Place of Presentation
      Toyama, Japan
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] MTJ 素子を用いた不揮発ロジックLSI の低電力化に関する一考察2013

    • Author(s)
      夏井雅典,荒木敦司,羽生貴弘
    • Organizer
      第36回多値論理フォーラム
    • Place of Presentation
      姫路
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] MTJ素子を用いた不揮発ロジックLSIの低電力化に関する一考察2013

    • Author(s)
      夏井雅典, 荒木敦司, 羽生貴弘
    • Organizer
      多値論理研究ノート
    • Place of Presentation
      兵庫
    • Year and Date
      2013-09-14
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] MTJ/MOS-Hybrid Logic-Circuit Design Flow for Nonvolatile Logic-in-Memory LSI2013

    • Author(s)
      M. Natsui, N. Sakimura, T. Sugibayashi, and T, Hanyu
    • Organizer
      2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)
    • Place of Presentation
      Beijing, China
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] Design of a Low-Voltage Logic Gate Based on Differential-Pair Circuitry2013

    • Author(s)
      K. Kashiuchi, M. Natsui, and T. Hanyu
    • Organizer
      2013 International Workshop on Emerging ICT
    • Place of Presentation
      Sendai, Japan
    • Year and Date
      2013-10-29
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] Vth補償機能を有するMOS/MTJハイブリッド電流モードロジックとその最適化2012

    • Author(s)
      キムヨンクン, 夏井雅典, 羽生貴弘
    • Organizer
      第25回多値論理とその応用研究会
    • Place of Presentation
      宮崎
    • Year and Date
      2012-01-08
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] Fundamental Technologies of High-Performance VLSI Processor for Multimedia Applications2012

    • Author(s)
      T.Hanyu, M.Natsui, A.Matsumoto
    • Organizer
      The 5th International Symposium and The 4th Student-Organizing International Mini-Conference on Information Electronics Systems
    • Place of Presentation
      仙台ウエスティンホテル
    • Year and Date
      2012-02-23
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] 低スイッチング電力基本論理ゲートの構成に関する一考察2012

    • Author(s)
      樫内清弘, 夏井雅典, 羽生貴弘
    • Organizer
      平成24年度電気関係学会東北支部連合大会
    • Place of Presentation
      秋田
    • Year and Date
      2012-08-30
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] Vth補償機能を有するMOS/MTJハイブリッド電流モードロジックとその最適化2012

    • Author(s)
      キム ヨンクン, 夏井雅典, 羽生貴弘
    • Organizer
      第25回多値論理とその応用研究会
    • Place of Presentation
      宮崎観光ホテル
    • Year and Date
      2012-01-08
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] 低電圧動作差動論理基本ゲートの構成に関する一考察2012

    • Author(s)
      樫内清弘, 夏井雅典, 羽生貴弘
    • Organizer
      多値論理研究ノート
    • Place of Presentation
      富山
    • Year and Date
      2012-09-15
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] Design of an MTJ-Based Variation-Resilient Basic Gate of Differential Logic2012

    • Author(s)
      Y. Kim, M. Natsui and T. Hanyu
    • Organizer
      平成24年度電気関係学会東北支部連合大会
    • Place of Presentation
      秋田
    • Year and Date
      2012-08-30
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] 不揮発性可変抵抗素子を用いたLSIパラメータばらつき最小化アルゴリズムの検討2011

    • Author(s)
      キムヨンクン, 夏井雅典, 羽生貴弘
    • Organizer
      平成23年度電気関係学会東北支部連合大会
    • Place of Presentation
      宮城
    • Year and Date
      2011-08-26
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] 不揮発性ロジックインメモリアーキテクチャが拓く新概念VLSI 設計パラダイム2011

    • Author(s)
      夏井雅典, 羽生貴弘
    • Organizer
      LSI とシステムのワークショップ2011
    • Place of Presentation
      福岡
    • Year and Date
      2011-05-16
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] 不揮発性ロジックインメモリアーキテクチャが拓く新概念VLSI設計パラダイム2011

    • Author(s)
      夏井雅典, 羽生貴弘
    • Organizer
      LSIとシステムのワークショップ2011
    • Place of Presentation
      北九州国際会議場
    • Year and Date
      2011-05-16
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] 不揮発性可変抵抗素子を用いたLSIパラメータばらつき最小化アルゴリズムの検討2011

    • Author(s)
      キム ヨンクン, 夏井雅典, 羽生貴弘
    • Organizer
      平成23年度電気関係学会東北支部連合大会
    • Place of Presentation
      東北学院大学
    • Year and Date
      2011-08-26
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] 不揮発性ロジックインメモリアーキテクチャが拓く新コンピューティングパラダイムの展望2011

    • Author(s)
      夏井雅典, 羽生貴弘
    • Organizer
      第58回応用物理学関係連合講演会
    • Place of Presentation
      神奈川工科大学
    • Year and Date
      2011-03-24
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] MTJ素子を用いた完全並列形不揮発TCAMワード回路の構成2011

    • Author(s)
      勝俣翠, 松永翔雲, 夏井雅典, 羽生貴弘
    • Organizer
      第24回多値論理とその応用研究会
    • Place of Presentation
      宮城
    • Year and Date
      2011-01-08
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] MTJ素子を用いた完全並列形不揮発TCAMワード回路の構成2011

    • Author(s)
      勝俣翠, 松永翔雲, 夏井雅典, 羽生貴弘
    • Organizer
      第24回多値論理とその応用研究会
    • Place of Presentation
      東北大学
    • Year and Date
      2011-01-08
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] 不揮発性ロジックインメモリアーキテクチャに基づく高信頼VLSI設計技術2011

    • Author(s)
      夏井雅典, 羽生貴弘
    • Organizer
      第73回ニューパラダイムコンピューティング研究会
    • Place of Presentation
      会津大学
    • Year and Date
      2011-07-30
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] Evaluation of Vth-Variation Effect on Multiple-Valued Current-Mode Circuits2011

    • Author(s)
      K.Kashiuchi, M.Natsui, T.Hanyu
    • Organizer
      2011 China-Korea-Japan Electronics and Communications Conference
    • Place of Presentation
      中国,成都
    • Year and Date
      2011-10-27
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] 可変抵抗素子を用いたポストプロセスばらつき補償機能付きOTAの検討2011

    • Author(s)
      長嶋孝晃, 夏井雅典, 桝井昇一, 羽生貴弘
    • Organizer
      平成23年度電気関係学会東北支部連合大会
    • Place of Presentation
      宮城
    • Year and Date
      2011-08-26
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] 可変抵抗素子を用いたポストプロセスばらつき補償機能付きOTAの検討2011

    • Author(s)
      長嶋孝晃, 夏井雅典, 桝井昇一, 羽生貴弘
    • Organizer
      平成23年度電気関係学会東北支部連合大会
    • Place of Presentation
      東北学院大学
    • Year and Date
      2011-08-26
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] Evaluation of Vth-Variation Effect on Multiple-Valued Current-Mode Circuits2011

    • Author(s)
      K. Kashiuchi, M. Natsui, and T. Hanyu
    • Organizer
      Proceedings of 2011 China-Korea-Japan Electronics and Communications Conference
    • Place of Presentation
      University of Electronic Science and Technology of China, China
    • Year and Date
      2011-10-27
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] 完全並列形不揮発TCAM向けワード回路の構成2010

    • Author(s)
      勝俣翠, 松永翔雲, 夏井雅典, 羽生貴弘
    • Organizer
      平成22年度電気関係学会東北支部連合大会
    • Place of Presentation
      青森
    • Year and Date
      2010-08-26
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] MTJ-Based Nonvolatile Reconfigurable LSI with Fine Grained Power Management2010

    • Author(s)
      L. Yuhui, D. Suzuki, M. Natsui and T. Hanyu
    • Organizer
      Japan-China-Korea Conference on Electronics & Communications 2010
    • Place of Presentation
      Tohoku University, Sendai, Japan
    • Year and Date
      2010-11-01
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] Design of a Dependable Logic Circuit Using Nonvolatile Programmable Devices2010

    • Author(s)
      Y.Kim, M.Natsui, T.Hanyu
    • Organizer
      Japan-China-Korea Conference on Electronics & Communications 2010
    • Place of Presentation
      東北大学
    • Year and Date
      2010-11-01
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] 完全並列形不揮発TCAM向けワード回路の構成2010

    • Author(s)
      勝俣翠, 松永翔雲, 夏井雅典, 羽生貴弘
    • Organizer
      平成22年度電気関係学会東北支部連合大会
    • Place of Presentation
      八戸工業大学
    • Year and Date
      2010-08-26
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] Design of a Dependable Logic Circuit Using Nonvolatile Programmable Devices2010

    • Author(s)
      Y. Kim, M. Natsui and T. Hanyu
    • Organizer
      Japan-China-Korea Conference on Electronics & Communications 2010
    • Place of Presentation
      Tohoku University, Sendai, Japan
    • Year and Date
      2010-11-01
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] MTJ-Based Nonvolatile Reconfigurable LSI with Fine Grained Power Management2010

    • Author(s)
      L.Yuhui, D.Suzuki, M.Natsui, T.Hanyu
    • Organizer
      Japan-China-Korea Conference on Electronics & Communications 2010
    • Place of Presentation
      東北大学
    • Year and Date
      2010-11-01
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] MTJ素子を用いた低消費電力不揮発性TCAMのパワーゲーティング手法2010

    • Author(s)
      松永翔雲, 夏井雅典, 羽生貴弘
    • Organizer
      多値論理研究ノート
    • Place of Presentation
      広島
    • Year and Date
      2010-09-11
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] MTJ素子を用いた低消費電力不揮発性TCAMのパワーケーディング手法2010

    • Author(s)
      松永翔雲, 夏井雅典, 羽生貴弘
    • Organizer
      第33回多値論理フォーラム
    • Place of Presentation
      広島市まちづくり市民交流プラザ
    • Year and Date
      2010-09-11
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] Fundamental Technologies towards New Paradigm VLSI Computing2010

    • Author(s)
      T.Hanyu, M.Natsui, A.Matsumoto, S.Matsunaga, N.Onizawa, D.Suzuki
    • Organizer
      The 4th International Symposium on Information Electronics Systems
    • Place of Presentation
      仙台エクセルホテル東急
    • Year and Date
      2010-07-08
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] Process-Variation-Aware VLSI Design Using an Emerging Functional Devices and Its Impact2010

    • Author(s)
      M. Natsui and T. Hanyu
    • Organizer
      Booklet of the 19th International Workshop on Post-Binary ULSI Systems
    • Place of Presentation
      Casa Convalescencia, Barcelona, Spain
    • Year and Date
      2010-05-28
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] Process-Variation-Aware VLSI Design Using an Emerging Functional Devices and Its Impact2010

    • Author(s)
      M.Natsui, T.Hanyu
    • Organizer
      19th International Workshop on Post-Binary ULSI Systems
    • Place of Presentation
      スペイン,バルセロナ
    • Year and Date
      2010-05-28
    • Data Source
      KAKENHI-PROJECT-22360137
  • [Presentation] Robust Multiple-Valued Current-Mode Circuit Components Based on Adaptive Reference-Voltage Control2009

    • Author(s)
      N. Onizawa and T. Hanyu
    • Organizer
      Naha
    • Place of Presentation
      Okinawa, Japan
    • Year and Date
      2009-05-21
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System2009

    • Author(s)
      T. Matsuura, H. Shirahama, M. Natsui and T. Hanyu
    • Organizer
      Naha
    • Place of Presentation
      Okinawa, Japan
    • Year and Date
      2009-05-21
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 高信頼電流モード多値集積回路技術とその応用2009

    • Author(s)
      白濱弘勝, 永井亮, 羽生青弓八
    • Organizer
      電子情報通信学会「多値論理とその応用」第二種研究会技術報告
    • Place of Presentation
      桐生
    • Year and Date
      2009-01-10
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 多値データ転送に基づく高性能NoCの構成2009

    • Author(s)
      松本敦, 羽生貴弘
    • Organizer
      電子情報通信学会「多値論理とその応用」第二種研究会技術報告
    • Place of Presentation
      桐生
    • Year and Date
      2009-01-10
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Systematic Design and Verification of Binary / Multiple-V alued Fused Logic Circuits2008

    • Author(s)
      Takashi Arimitsu, Tasuku Nagai, Masanori Natsui and Takahiro Hanyu
    • Organizer
      Proceedings of 2008 China-Korea-Japan Graduates Workshop on Electronic Information
    • Place of Presentation
      成都(中国)
    • Year and Date
      2008-10-30
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] TMRロジックとその応用2008

    • Author(s)
      羽生 貴弘
    • Organizer
      日本磁気学会第159回研究会
    • Place of Presentation
      東京
    • Year and Date
      2008-03-03
    • Data Source
      KAKENHI-PROJECT-18650009
  • [Presentation] High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit2008

    • Author(s)
      T. Nagai, N. Onizawa and T. Hanyu
    • Organizer
      Dallas, TX
    • Place of Presentation
      USA
    • Year and Date
      2008-05-22
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 電流モード多値回路および電圧モード多値回路の構成と評価2008

    • Author(s)
      白濱弘勝, 羽生貴弘
    • Place of Presentation
      兵庫
    • Year and Date
      2008-01-13
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Design of High-Performance Quaternary Adders Based on Output-Generator Sharing2008

    • Author(s)
      H. Shirahama and T. Hanyu
    • Organizer
      Proceedings 38th IEEE International Symposium on Multiple-Valued Logic
    • Place of Presentation
      ダラス(アメリカ)
    • Year and Date
      2008-05-21
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 多値符号化に基づく非同期式転送方式の検討2008

    • Author(s)
      松本敦, 羽生貴弘
    • Organizer
      電子情報通信学会「多値論理とその応用」第二種研究会
    • Place of Presentation
      神戸
    • Year and Date
      2008-01-13
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Asynchronous data-transfer interface for an interleaver in fully-parallel low-density parity-check decoders2008

    • Author(s)
      N. Onizawa and T. Hanyu
    • Place of Presentation
      Sendai, Japan
    • Year and Date
      2008-10-17
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 出力状態モニタリングに基づく電流モード多値順序回路の低消費電力化2008

    • Author(s)
      松浦貴史, 白濱弘勝, 夏井雅典, 羽生貴弘
    • Organizer
      平成20年度電気関係学会東北支部連合大会講演論文集
    • Place of Presentation
      郡山
    • Year and Date
      2008-08-22
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Systematic Design and Verification of Binary/Multiple-Valued Fused Logic Circuits2008

    • Author(s)
      T. Arimitsu, T. Nagai, M. Natsui and T. Hanyu
    • Place of Presentation
      Chengdu, China
    • Year and Date
      2008-10-30
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 適応的電流源制御に基づくパイプライン電流モード多値演算回路の低電力化2008

    • Author(s)
      松浦貴史, 白濱弘勝, 夏井雅典, 羽生貴弘
    • Place of Presentation
      沖縄
    • Year and Date
      2008-09-12
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 電流モードsingle-track方式に基づく非同期データ転送の高速化2008

    • Author(s)
      大竹遥, 鬼沢直哉, 松本敦, 羽生貴弘
    • Organizer
      平成20年度電気関係学会東北支部連合大会講演論文集
    • Place of Presentation
      郡山
    • Year and Date
      2008-08-22
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices2008

    • Author(s)
      A. Hirosaki, M. Miura, A. Matsumoto and T. Hanyu
    • Organizer
      Dallas, TX
    • Place of Presentation
      USA
    • Year and Date
      2008-05-22
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 多値符号化に基づく非同期式転送方式の検討2008

    • Author(s)
      松本敦, 羽生貴弘
    • Place of Presentation
      兵庫
    • Year and Date
      2008-01-13
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 出力状態モニタリングに基づく電流モード多値順序回路の低消費電力化2008

    • Author(s)
      松浦貴史, 白濱弘勝, 夏井雅典, 羽生貴弘
    • Place of Presentation
      福島
    • Year and Date
      2008-08-22
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Asynchronous Multiple-Valued Data Transfer and Its Application2008

    • Author(s)
      Tomoyoshi Funazaki, Naoya Onizawa, Atsushi Matsumoto and Takahiro Hanyu
    • Organizer
      Proceedings of 2008 China-Korea-Japan Graduates Workshop on Electronic Information
    • Place of Presentation
      成都(中国)
    • Year and Date
      2008-10-30
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 電流モ-ドsingle-track方式に基づく非同期データ転送の高速化2008

    • Author(s)
      大竹遥, 鬼沢直哉, 松本敦, 羽生貴弘
    • Place of Presentation
      福島
    • Year and Date
      2008-08-22
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Design of High-Performance Quaternary Adders Based on Output-Generator Sharing2008

    • Author(s)
      H. Shirahama and T. Hanyu
    • Organizer
      Dallas, TX
    • Place of Presentation
      USA
    • Year and Date
      2008-05-22
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Asynchronous Multiple-Valued Data Transfer and Its Application2008

    • Author(s)
      T. Funazaki, N. Onizawa, A. Matsumoto and T. Hanyu
    • Place of Presentation
      Chengdu, China
    • Year and Date
      2008-10-30
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] MRロジックとその可能性2008

    • Author(s)
      羽生貴弘, 松本敦, 松永翔雲
    • Organizer
      第55回応用物理関係学会講演会
    • Place of Presentation
      千葉
    • Year and Date
      2008-03-27
    • Data Source
      KAKENHI-PROJECT-18650009
  • [Presentation] 電流モード多値回路および電圧モード多値回路の構成と評価2008

    • Author(s)
      白濱弘勝, 羽生貴弘
    • Organizer
      電子情報通信学会「多値論理とその応用」第二種研究会
    • Place of Presentation
      神戸
    • Year and Date
      2008-01-13
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] High-level Synthesis of Asynchronous Circuits and Its Optimization2008

    • Author(s)
      A. Matsumoto, T. Yoneda and T. Hanyu
    • Organizer
      Optimization, Dallas, TX
    • Place of Presentation
      USA
    • Year and Date
      2008-05-24
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Asynchronous Data-Transfer Interface for an Interleaver in Fully-Parallel Low-Density Parity-Check Decoders2008

    • Author(s)
      Naoya Onizawa and Takahiro Hanyu
    • Organizer
      Proceedings of the 1st Student Organizing International Mini-Conference on Information Electronics Systems
    • Place of Presentation
      仙台
    • Year and Date
      2008-10-16
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 出力状態モニタリングに基づく電流モード多値順序回路の低消費電力化2008

    • Author(s)
      松浦貴史, 白濱弘勝, 夏井雅典, 羽生貴弘
    • Organizer
      第31回多値論理フォーラム
    • Place of Presentation
      沖縄
    • Year and Date
      2008-09-12
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 次世代VLSI向き多値回路の系統的設計2008

    • Author(s)
      夏井雅典, 羽生貴弘
    • Place of Presentation
      沖縄
    • Year and Date
      2008-09-12
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Design of a Processing Element Based on Multiple-Valued Current-Mode Logic for a Many-Core Processor2008

    • Author(s)
      H. Shirahama and T. Hanyu
    • Place of Presentation
      Sendai, Japan
    • Year and Date
      2008-10-17
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] TMR素子を用いたVthばらつき補正可能MOS基本回路とその応用2007

    • Author(s)
      廣崎旭宏, 三浦成友, 羽生貴弘
    • Organizer
      平成19年度電気関係学会東北支部連合大会
    • Place of Presentation
      弘前
    • Year and Date
      2007-08-24
    • Data Source
      KAKENHI-PROJECT-18650009
  • [Presentation] Novel Circuit Techniques for High-Speed Intra-Chip Communication2007

    • Author(s)
      T. Hanyu, T. Takahashi and S. Matsunaga
    • Place of Presentation
      Sendai, Japan
    • Year and Date
      2007-01-23
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] A Simplex/Duplex-Compatible System for Asynchronous Peer-to-Peer Communication Using One-phase Signaling2007

    • Author(s)
      T. Takahashi and T. Hanyu
    • Place of Presentation
      Sendai, Japan
    • Year and Date
      2007-01-25
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] High-speed Asynchronous Data Transfer Scheme Based on One-Phase Dual-Rail Coding2007

    • Author(s)
      Y. Otake, K. Mizusawa, N. Onizawa, and T. Hanyu
    • Organizer
      4th International Workshop of Tohoku Univ. and Yeungnum Univ.
    • Place of Presentation
      松島
    • Year and Date
      2007-11-12
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 電流モード多値回路の高速動作検証手法2007

    • Author(s)
      永井亮, 鬼沢直哉, 羽生貴弘
    • Place of Presentation
      青森
    • Year and Date
      2007-08-24
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor2007

    • Author(s)
      H. Shirahama, A. Mochizuki, T. Hanyu, M. Nakajima and K. Arimoto
    • Place of Presentation
      Oslo, Norway
    • Year and Date
      2007-05-15
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Quaternary Processing Element for a Multi-Core VLSI processor2007

    • Author(s)
      H. Shirahama, T. Hanyu, M. Nakajima, A. Mochizuki, and K. Arimoto
    • Organizer
      4th International Workshop of Tohoku Univ. and Yeungnum Univ.
    • Place of Presentation
      松島
    • Year and Date
      2007-11-12
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Active-Load Differential Comparator for Crosstalk-Noise Reduction2007

    • Author(s)
      A. Mochizuki, M. Miura and T. Hanyu
    • Place of Presentation
      Oslo, Norway
    • Year and Date
      2007-05-15
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Implementation of a High-Throughput LDPC Decoder Chip Using an Asynchronous Interleaving Scheme2007

    • Author(s)
      N. Onizawa and T. Hanyu
    • Place of Presentation
      Sendai, Japan
    • Year and Date
      2007-01-25
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 電流モード多値回路の高速動作検証手法2007

    • Author(s)
      永井亮, 鬼沢直哉, 羽生貴弘
    • Organizer
      平成19年度電気関係学会東北支部連合大会
    • Place of Presentation
      弘前
    • Year and Date
      2007-08-24
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Active-Load Differential Comparator for Crosstalk-Noise Reduction2007

    • Author(s)
      A. Mochizuki, M. Miura, and T. Hanyu
    • Organizer
      37th IEEE International Symposium on Multiple-Valued Logic
    • Place of Presentation
      オスロ(ノルウェー)
    • Year and Date
      2007-05-16
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Asynchronous Peer-to-Peer Simplex/Duplex-Compatible Communication System Using a One-Phase Signaling Scheme2007

    • Author(s)
      T. Takahashi, K. Mizusawa, and T. Hanyu
    • Organizer
      37th IEEE International Symposium on Multiple-Valued Logic
    • Place of Presentation
      オスロ(ノルウェー)
    • Year and Date
      2007-05-16
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 超並列プロセッサ内多値データ転送方式2007

    • Author(s)
      白濱弘勝, 羽生貴弘, 中島雅美, 望月明, 有本和民
    • Place of Presentation
      神奈川
    • Year and Date
      2007-08-21
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 3.2-Gb/s 1024-b Rate-1/2 LDPC Decoder Chip Using a Flooding-Type Update-Schedule Algorithm2007

    • Author(s)
      N. Onizawa, T. Ikeda, T. Hanyu and V. C. Gaudet
    • Place of Presentation
      Montreal, Canada
    • Year and Date
      2007-08-05
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 多値電流モード非同期データ転送方式に基づくLDPCデコーダLSIの実現2007

    • Author(s)
      鬼沢直哉, 羽生貴弘
    • Place of Presentation
      愛知
    • Year and Date
      2007-03-21
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 非同期式回路のFPGA実現とその評価2007

    • Author(s)
      松本敦, 米田友洋, 羽生貴弘
    • Place of Presentation
      北海道
    • Year and Date
      2007-08-02
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 多値非同期データ転送方式に基づく高性能LDPCデコーダLSIの実現2007

    • Author(s)
      鬼沢直哉, 羽生貴弘, Vincent Gaudet
    • Place of Presentation
      福岡
    • Year and Date
      2007-11-20
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor2007

    • Author(s)
      H. Shirahama, A. Mochizuki, T. Hanyu, M. Nakajima, K. Arimoto
    • Organizer
      37th IEEE International Symposium on Multiple-Valued Logic
    • Place of Presentation
      オスロ(ノルウェー)
    • Year and Date
      2007-05-16
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Asynchronous Peer-to-Peer Simplex/ Duplex-Compatible Communication System Using a One-Phase Signaling Scheme2007

    • Author(s)
      T. Takahashi, K. Mizusawa and T. Hanyu
    • Place of Presentation
      Oslo, Norway
    • Year and Date
      2007-05-15
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Design and Evaluation of a Multiple-Valued Full Adder2007

    • Author(s)
      T. Matsuura, H. Shirahama, T. Hanyu
    • Organizer
      4th International Workshop of Tohoku Univ. and Yeungnum Univ.
    • Place of Presentation
      松島
    • Year and Date
      2007-11-12
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 超並列プロセッサ内多値データ転送方式2007

    • Author(s)
      白濱弘勝, 羽生貴弘, 中島雅美, 望月明, 有本和民
    • Organizer
      多値論理研究会
    • Place of Presentation
      湘南
    • Year and Date
      2007-08-22
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 電流モード多値回路の信頼性評価2007

    • Author(s)
      高橋知宏, 羽生貴弘
    • Place of Presentation
      愛知
    • Year and Date
      2007-03-20
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Quaternary Processing Element for a Multi-Core VLSI processor2007

    • Author(s)
      H. Shirahama, T. Hanyu, M. Nakajima, A. Mochizuki and K. Arimoto
    • Place of Presentation
      Sendai, Japan
    • Year and Date
      2007-11-12
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 3.2-Gb/s 1024-b Rate-1/2 LDPC Decoder Chip Using a Flooding-Type Update-Schedule Algorithm2007

    • Author(s)
      N. Onizawa, T. Ikeda, T. Hanyu, and V. Gaudet
    • Organizer
      50th IEEE Midwest Symposium on Circuits and Systems
    • Place of Presentation
      モントリオール(カナダ)
    • Year and Date
      2007-08-06
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 多値非同期データ転送方式に基づく高性能LDPCデコーダLSIの実現2007

    • Author(s)
      鬼沢直哉, 羽生貴弘, V. Gaudet
    • Organizer
      第11回システムLSIワークショップ
    • Place of Presentation
      小倉
    • Year and Date
      2007-11-20
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 非同期式回路のFPGA実現とその評価2007

    • Author(s)
      松本敦, 米田友洋, 羽生貴弘
    • Organizer
      電子情報通信学会ディペンダブルコンピューティング研究会
    • Place of Presentation
      旭川
    • Year and Date
      2007-08-02
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] A Standby-Power-Free TCAM Based on TMR Logic2007

    • Author(s)
      Kei Kimura and Takahiro Hanyu
    • Organizer
      Proc. 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS)
    • Place of Presentation
      モントリオール(カナダ)
    • Year and Date
      2007-08-07
    • Data Source
      KAKENHI-PROJECT-18650009
  • [Presentation] Implementation of an Asynchronous LDPC Decoder Using Multiple-Valued Duplex Interleaving2007

    • Author(s)
      N. Onizawa, T. Hanyu, and V. Gaudet
    • Organizer
      The 2007 Analog Decoding Workshop
    • Place of Presentation
      モントリオール(カナダ)
    • Year and Date
      2007-05-24
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Design and Evaluation of a Multiple-Valued Full Adder2007

    • Author(s)
      T. Matsuura, H. Shirahama, T. Hanyu
    • Place of Presentation
      Sendai, Japan
    • Year and Date
      2007-11-12
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Standby-Power-Free Logic-in-Memory Circuit Based on Ferroelectric Logic2007

    • Author(s)
      S. Matsunaga, T. Hanyu, H. Kimura, Y. Fujimori, M. Moriwake, and H. Takasu
    • Organizer
      Proc. 4th International Workshop of Tohoku Univ. and Yeungnum Univ
    • Place of Presentation
      松島
    • Year and Date
      2007-11-12
    • Data Source
      KAKENHI-PROJECT-18650009
  • [Presentation] A TMR-Based Logic Circuit for a Power-Aware VLSI System2007

    • Author(s)
      K. Hiyama, S. Matsunaga, K. Kimura and T. Hanyu
    • Organizer
      Proc. 4th International Workshop of Tohoku Univ. and Yeungnum Univ
    • Place of Presentation
      松島
    • Year and Date
      2007-11-12
    • Data Source
      KAKENHI-PROJECT-18650009
  • [Presentation] High-speed Asynchronous Data Transfer Scheme Based on One-Phase Dual-Rail Coding2007

    • Author(s)
      Y. Otake, K. Mizusawa, N. Onizawa and T. Hanyu
    • Place of Presentation
      Sendai, Japan
    • Year and Date
      2007-11-12
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Implementation of an Asynchronous LDPC Decoder Using Multiple-Valued Duplex Interleaving2007

    • Author(s)
      N. Onizawa, T. Hanyu and V. Gaudet
    • Place of Presentation
      Montreal, Canada
    • Year and Date
      2007-05-24
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 多値2線符号化に基づく双方向非同期データ転送LSIの高性能化2006

    • Author(s)
      水澤一泰, 高橋知宏, 羽生貴弘
    • Place of Presentation
      秋田
    • Year and Date
      2006-09-01
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 多値2線符号化に基づく高性能非同期データ転送VLSI2006

    • Author(s)
      高橋知宏, 水澤一泰, 羽生貴弘
    • Place of Presentation
      宮城
    • Year and Date
      2006-10-27
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 差動ロジックに基づく高性能VLSIの展望2006

    • Author(s)
      望月明, 羽生貴弘
    • Place of Presentation
      宮城
    • Year and Date
      2006-08-23
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 2線差動論理に基づくノイズフリー多値集積回路2006

    • Author(s)
      三浦成友, 望月明, 羽生貴弘
    • Place of Presentation
      秋田
    • Year and Date
      2006-09-01
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Highly Reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic2006

    • Author(s)
      A. Mochizuki and T. Hanyu
    • Place of Presentation
      Singapore
    • Year and Date
      2006-05-18
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] 隣接データの類似性に着目した高速LDPC復号化とその評価2006

    • Author(s)
      池田智和, 鬼沢直哉, 羽生貴弘
    • Place of Presentation
      秋田
    • Year and Date
      2006-09-01
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Automatic Place and Route Scheme in Multiple-Valued Current-Mode Circuit Design2006

    • Author(s)
      T. Nagai, T. Takahashi, N. Onizawa and T. Hanyu
    • Place of Presentation
      Gyeongju, Korea
    • Year and Date
      2006-11-17
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Low-power Latch Based on Dynamic Differential Logic2006

    • Author(s)
      H. Shirahama, A. Mochizuki, T. Hanyu
    • Place of Presentation
      Gyeongju, Korea
    • Year and Date
      2006-11-17
    • Data Source
      KAKENHI-PROJECT-18300012
  • [Presentation] Design of a Microprocessor Data Path Using Four-Valued Differential-Pair Circuits2006

    • Author(s)
      A. Mochizuki, T. Kitamura, H. Shirahama and T. Hanyu
    • Place of Presentation
      Singapore
    • Year and Date
      2006-05-18
    • Data Source
      KAKENHI-PROJECT-18300012
  • 1.  KAMEYAMA Michitaka (70124568)
    # of Collaborated Projects: 12 results
    # of Collaborated Products: 0 results
  • 2.  YONEDA Tomohiro (30182851)
    # of Collaborated Projects: 4 results
    # of Collaborated Products: 4 results
  • 3.  MOCHIZUKI Akira (40359542)
    # of Collaborated Projects: 4 results
    # of Collaborated Products: 24 results
  • 4.  NATSUI Masanori (10402661)
    # of Collaborated Projects: 3 results
    # of Collaborated Products: 61 results
  • 5.  HIGUCHI Tatsuo (20005317)
    # of Collaborated Projects: 3 results
    # of Collaborated Products: 0 results
  • 6.  HARIYAMA Masanori (10292260)
    # of Collaborated Projects: 3 results
    # of Collaborated Products: 0 results
  • 7.  今井 雅 (70323665)
    # of Collaborated Projects: 3 results
    # of Collaborated Products: 4 results
  • 8.  MATSUMOTO Atsushi (40455853)
    # of Collaborated Projects: 2 results
    # of Collaborated Products: 12 results
  • 9.  鬼沢 直哉 (90551557)
    # of Collaborated Projects: 2 results
    # of Collaborated Products: 16 results
  • 10.  SMITH Kenneth C.
    # of Collaborated Projects: 2 results
    # of Collaborated Products: 0 results
  • 11.  SASAO Tsutomu (20112013)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 12.  XIAOWEI Deng (70261576)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 13.  KIMURA Hiromitsu (00361155)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 14.  川人 祥二 (40204763)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 15.  吉瀬 謙二 (50323887)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 16.  齋藤 寛 (50361671)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 17.  池田 正二 (90281865)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 3 results
  • 18.  村口 正和 (90386623)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 19.  BUTLER Jon T.
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 20.  LIN H.C.
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 21.  NG Wai-Tung
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 22.  GULAK Glenn
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 23.  SILIO Charle
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 24.  SILIO Carles B.
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 25.  CHARLES B Si
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 26.  JON T Butler
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 27.  KENNETH C Sm
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 28.  NG Wai Tung
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 29.  SMITH Rennet
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results

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