Hariyama Masanori 張山昌論

… Alternative Names

HARIYAMA Masanori 張山昌論

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Researcher Number	10292260
Other IDs
External Links
Affiliation (Current)	2025: 東北大学, 情報科学研究科, 教授
Affiliation (based on the past Project Information) *help	2016 – 2024: 東北大学, 情報科学研究科, 教授 2012 – 2015: 東北大学, 情報科学研究科, 准教授 2014: 東北大学, 大学院情報科学研究科, 准教授 2009 – 2012: Tohoku University, 大学院・情報科学研究科, 准教授 2007: Graduate School of Information Sciences, 大学院・情報科学研究科, Associate Professor … More 2006: 東北大学, 大学院情報科学研究科, 助教授 2004 – 2006: 東北大学, 大学院・情報科学研究科, 助教授 2002: Tohoku University, Graduate School of Information Sciences, Associate Professor, 大学院・情報科学研究科, 助教授 1997 – 2002: 東北大学, 大学院・情報科学研究科, 助手 1997: 東北大学, 大学院情報科学研究科, 助手 Less
Review Section/Research Field	Principal Investigator Computer system/Network / 計算機科学 / Sections That Are Subject to Joint Review: Basic Section60030:Statistical science-related , Basic Section61030:Intelligent informatics-related / Basic Section 60030:Statistical science-related / Basic Section 61030:Intelligent informatics-related / Basic Section 60100:Computational science-related / Computer system / Perception information processing/Intelligent robotics Except Principal Investigator Basic Section 90110:Biomedical engineering-related / 計算機科学 … More / Basic Section 09080:Science education-related / Medium-sized Section 9:Education and related fields / Life / Health / Medical informatics / Computer system/Network / Control engineering / 計測・制御工学 / Perception information processing/Intelligent robotics Less
Keywords	Principal Investigator FPGA / リコンフィギャラブルコンピューティング / GPU / 並列処理 / リコンフギャラブルコンピューティング / 高性能計算 / アクセラレータ / 画像処理 / 自然言語処理 / AI … More / 量子アリーリング / マテリアルインフォマティクス / 組合せ最適化問題 / 大規模固有値問題 / 大規模固有値計算 / 量子コンピューティング / 量子化学計算 / 量子コンピュータ / 量子アニーリング / 量子コンピュータシミュレーション / 量子化学 / ヘテロジニアスコンピューティング / 不揮発ロジック / リコンフィギャラブルプロセッサ / 高位合成 / リコンフィギャラブルシステム / 大規模計算 / ビッグデータ / OpenCL / ビッグデータ処理 / カスタムアクセラレータ / 強誘電体メモリ / ウェーブパイプライン / 非同期回路 / リーク電流 / フローティングゲートMOS / 強誘電体 / パワーゲーティング / 複数電源電圧 / 不揮発メモリ / 非同期式回路 / Adaptive window / SAD / 絶対値差分演算 / ロジックインメモリ / Adaptive Window / 絶対値差分 / ステレオビジョン / ハイレベルシンセシス / ASIC / 再構成可能アーキテクチャ / 再構成アーキテクチャ / 面積・時間積最小化 / 知能集積システム / 軌道計画 / 衝突警報システム … More Except Principal Investigator ハイレベルシンセシス / 脳血流測定 / Highly-Safe Intelligent Vehicle / 高安全知能自動車 / Logic-In-Memory Architecture / Allocation / Scheduling / High-Level Synthesis / Intelligent Integrated Systems for Real-World Applications / ロジックインメモリアーキテクチャ / アロケーション / スケジューリング / リアルワールド応用知能集積システム / 医療情報処理 / ECM / サイトカイン / 線維芽細胞 / 好中球 / エージェントシミュレーション / 脂肪組織由来間質細胞 / マルチエージェントシミュレーション / 複雑系 / 細胞外マトリクス / 炎症性サイトカイン / 生体シミュレーション / 細胞間コミュニケーション / 創傷治癒 / 心理師 / 医師 / 脳科学 / 科学教育 / 動的遺伝子検査 / 定量的指標 / 科学的指標 / 幼少期評価 / 運動 / 姿勢 / 学習効果 / 生物学的指標 / NIRS / エピゲノム / 養育環境 / 保育環境 / 幼児 / 早期介入 / 発達障害 / 3次元画像処理 / 超音波画像 / 超音波診断 / 医用画像処理 / ナビゲーション / ３D超音波画像 / ３D超音波装置 / ３D画像 / ３D超音波ナビゲーション / 肝切除術 / 超音波 / 3Dシミュレーション / 肝臓切除 / Human Extraction / Vehicle Extraction / Road Extraction / Motion Estimation / Reconfigurable VLSI / High-level Synthesis / System-on-Chip / サンプリング周期 / システムレベル統合設計 / VLSIアーキテクチャ / ベイジアンネットワーク / 非同期アーキテクチャ / メモリアロケーション / ステレオビジョン / 人物抽出 / 車両抽出 / 道路抽出 / 軌道予測 / リコンフィギャラブルVLSI / システムLSI / Low-Power VLSI Processor / ロジックインメモリーアーキテクチャ構造 / 低消費電力VLSI1プロセッサ / 低消費電力VLSIプロセッサ / Intelligent Information Processing / Magnitude Comparison / Highly-Parallel Operation / Non-numeric Data Processing / Logic-in-Memory Architecture / Threshold Operation / Floating-Gate MOS Transistor / Multiple-Valued CAM / フローティングゲートMOSトランジスタ / 知的情報処理 / 大小比較演算 / 超並列処理 / 非数値データ処理 / ロジックインメモリ構造 / しきい演算 / フローティングゲートMOSトランスジスタ / 多値連想メモリ / Partition Theory / Reed-Muller Expansion / Asynchronous Multiple-Valued VLSI / Highly-Parallel Arithmetic and Logic Circuit / Self Checking Circuit / Logic-In-Memory VLSI / Dual-Rail Current-Mode Multiple-Valued Integrated Circuit / 電力源制御 / 低消費電力多値集積回路 / 非同期多値演算回路 / 電流源制御 / 電流モード多値集積回路 / 非同期式多値演算回路 / 分割理論 / Reed-Muller展開 / 高並列演算回路 / 非同期式多値VLSI / 算術演算回路 / セルフチェッキング回路 / ロジックインメモリVLSI / 2線式電流モード多値集積回路 / Interconnection Network / Spacially Parallel Structure / 3次元計測VLSIプロセッサ / パイプライン並列構造 / ステレオビジョンVLSIプロセッサ / 衝突チェックVLSIプロセッサ / 並列データ供給 / 演算遅れ時間最小化 / 並列構造VLSIプロセッサ / 相互結合回路網 / 空間並列構造 / ロジックインメモリアーキテクチャ構造 / 肝切除ナビゲーション / 肝切除シミュレーション / 3次元立体画像 / ３Dシミュレーション / シミュレーション / 最適切除領域推定 / 術前計画 / 医療画像処理 / 肝臓外科手術支援 Less

High-efficiency Heterogeneous Custom Accelerator Foundation for TransformerPrincipal Investigator
- Principal Investigator
  
  張山昌論
- Project Period (FY)
  2024 – 2027
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Review Section
  
  Basic Section 61030:Intelligent informatics-related
  Basic Section 60030:Statistical science-related
  Sections That Are Subject to Joint Review: Basic Section60030:Statistical science-related , Basic Section61030:Intelligent informatics-related
- Research Institution
  Tohoku University
エージェントシミュレーションを活用した慢性炎症・臓器線維化のメカニズム追求
- Principal Investigator
  
  井上健一
- Project Period (FY)
  2024 – 2026
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 90110:Biomedical engineering-related
- Research Institution
  Dokkyo Medical University
Establishment of Effective Science Education during School Age utilizing Brain Science-based Methods by a Medical Doctor and a Psychologist
- Principal Investigator
  
  久保田健夫
- Project Period (FY)
  2021
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 09080:Science education-related
- Research Institution
  Seitoku University
細胞社会は互いのコミュニケーションをどのようにとっているか：複雑系の視点
- Principal Investigator
  
  岸本聡子
- Project Period (FY)
  2021 – 2024
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 90110:Biomedical engineering-related
- Research Institution
  Dokkyo Medical University
Custom Accelerators for Quantum-Annealing-Assisted Material InformaticsPrincipal Investigator
- Principal Investigator
  
  Masanori Hariyama
- Project Period (FY)
  2020 – 2023
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Review Section
  
  Basic Section 60100:Computational science-related
- Research Institution
  Tohoku University
Development of epigenomic markers that enable to perform early assessment and intervention for neurodevelopmental disorders
- Principal Investigator
  
  久保田健夫
- Project Period (FY)
  2018 – 2021
- Research Category
  
  Grant-in-Aid for Challenging Research (Exploratory)
- Review Section
  
  Medium-sized Section 9:Education and related fields
- Research Institution
  Seitoku University
Development of Highly-reliable and Low-power reconfigurable VLSI Based on Asynchronous architecture and Non-volatile memoryPrincipal Investigator
- Principal Investigator
  
  Masanori Hariyama
- Project Period (FY)
  2016 – 2017
- Research Category
  
  Grant-in-Aid for Challenging Exploratory Research
- Research Field
  
  Computer system
- Research Institution
  Tohoku University
Intraoperative planning and navigation based on three-dimensional image processing combining ultrasound and CT
- Principal Investigator
  
  Shimoda Mitsugi
- Project Period (FY)
  2016 – 2019
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Life / Health / Medical informatics
- Research Institution
  Tokyo Medical University
Development of Heterogeneous-Computing Platform with Custom Accelerators for Embedded HPC ApplicationsPrincipal Investigator
- Principal Investigator
  
  Hariyama Masanori
- Project Period (FY)
  2012 – 2015
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Tohoku University
Development of Surgery Navigation System Based on Real-time Intelligent Image Processing and Augmented Reality
- Principal Investigator
  
  SHIMODA Mitsugi
- Project Period (FY)
  2012 – 2014
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Perception information processing/Intelligent robotics
- Research Institution
  Dokkyo Medical University
Low-Power FPGA Based on Fine-grained Autonomous Supply-Voltage ControlPrincipal Investigator
- Principal Investigator
  
  HARIYAMA Masanori
- Project Period (FY)
  2009 – 2011
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Tohoku University
Optimal VLSI Design for a Highly-Safe Intelligent Vehicle Based on a System Integration Theory
- Principal Investigator
  
  KAMEYAMA Michitaka
- Project Period (FY)
  2005 – 2007
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system/Network
- Research Institution
  Tohoku University
リアルワールド知能システム用超高速ステレオビジョンVLSIプロセッサの開発Principal Investigator
- Principal Investigator
  
  張山昌論
- Project Period (FY)
  2004 – 2006
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  Perception information processing/Intelligent robotics
- Research Institution
  Tohoku University
リアルワールド応用低消費電力リコンフィギャラブルVLSIプロセッサの開発Principal Investigator
- Principal Investigator
  
  張山昌論
- Project Period (FY)
  2001 – 2002
- Research Category
  
  Grant-in-Aid for Young Scientists (B)
- Research Field
  
  計算機科学
- Research Institution
  Tohoku University
Development of VLSI Processor Chip Family for Highly-Safe Intelligent Vehicles Based on Optimal Design Mythologies
- Principal Investigator
  
  KAMEYAMA Michitaka
- Project Period (FY)
  2000 – 2002
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Control engineering
- Research Institution
  Tohoku University
面積・時間積最小化に基づく最高性能知能集積システム用VLSIプロセッサの開発Principal Investigator
- Principal Investigator
  
  張山昌論
- Project Period (FY)
  1998 – 1999
- Research Category
  
  Grant-in-Aid for Encouragement of Young Scientists (A)
- Research Field
  
  計算機科学
- Research Institution
  Tohoku University
High-Level Synthesis of High-Performance VLSI Processors for Intelligent Integrated System
- Principal Investigator
  
  KAMEYAMA Michitaka
- Project Period (FY)
  1997 – 1999
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  計測・制御工学
- Research Institution
  TOHOKU UNIVERSITY
Development of a Chip Family for Ultra-Highly-Parallel Multiple-Valued Integrated Circuits and Its Applications
- Principal Investigator
  
  KAMEYAMA Michitaka
- Project Period (FY)
  1997 – 1999
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  計算機科学
- Research Institution
  TOHOKU UNIVERSITY
Implementation of a One-Transistor Multiple-Valued Content-Addressalbe Memory and Its Application
- Principal Investigator
  
  HANYU Takahiro
- Project Period (FY)
  1997 – 2000
- Research Category
  
  Grant-in-Aid for Scientific Research (B).
- Research Field
  
  計算機科学
- Research Institution
  Tohoku Univesity

[Book] Automatic estimation of resected liver region using a tumor domination ratio.2015
- Author(s)
  Hariyama M, Shimoda M.
- Publisher
  Elsevier
- Data Source
  KAKENHI-PROJECT-24500242
[Journal Article] A Scalable Emulator for Quantum Fourier Transform Using Multiple-FPGAs With High-Bandwidth-Memory2022
- Author(s)
  Waidyasooriya Hasitha Muthumala、Oshiyama Hiroki、Kurebayashi Yuya、Hariyama Masanori、Ohzeki Masayuki
- Journal Title
  
  IEEE Access
  
  Volume: 10 Pages: 65103-65117
- DOI
  10.1109/access.2022.3183993
- Peer Reviewed / Open Access / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-20H04197, KAKENHI-PROJECT-19K11998
[Journal Article] Temporal and spatial parallel processing of simulated quantum annealing on a multicore CPU2022
- Author(s)
  Waidyasooriya Hasitha Muthumala、Hariyama Masanori
- Journal Title
  
  The Journal of Supercomputing
  
  Volume: 78 Issue: 6 Pages: 8733-8750
- DOI
  10.1007/s11227-021-04242-0
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-19K11998, KAKENHI-PROJECT-20H04197
[Journal Article] Design space exploration for an FPGA-based quantum annealing simulator with interaction-coefficient-generators2021
- Author(s)
  Liu Chia-Yin、Waidyasooriya Hasitha Muthumala、Hariyama Masanori
- Journal Title
  
  The Journal of Supercomputing
  
  Volume: 78 Issue: 1 Pages: 1-17
- DOI
  10.1007/s11227-021-03859-5
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-19K11998, KAKENHI-PROJECT-20H04197
[Journal Article] A GPU-Based Quantum Annealing Simulator for Fully-Connected Ising Models Utilizing Spatial and Temporal Parallelism2020
- Author(s)
  Waidyasooriya Hasitha Muthumala、Hariyama Masanori
- Journal Title
  
  IEEE Access
  
  Volume: 8 Pages: 67929-67939
- DOI
  10.1109/access.2020.2985699
- Peer Reviewed / Open Access / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-19K11998, KAKENHI-PROJECT-20H04197
[Journal Article] Development of new software enabling automatic identification of the optimal anatomical liver resectable region, incorporating preoperative liver function2019
- Author(s)
  MITSUGI SHIMODA1, MASANORI HARIYAMA1,2, YUKIO OSHIRO1 and SHUJI SUZUKI1
- Journal Title
  
  ONCOLOGY LETTERS
  
  Volume: 18 Pages: 6639-6647
- DOI
  10.3892/ol.2019.11006
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-16H02899
[Journal Article] An FPGA Accelerator for PatchMatch Multi-View Stereo Using OpenCL2018
- Author(s)
  Shunsuke Tatsumi, Masanori Hariyama, Koichi Ito, Takafumi Aoki
- Journal Title
  
  Journal of Real-Time Image Processing
  
  Volume: 1 Issue: 2 Pages: 1-13
- DOI
  10.1007/s11554-017-0745-9
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-16K12404
[Journal Article] Automatic Optimization of OpenCL-Based Stencil Codes for FPGAs and Its Evaluation2017
- Author(s)
  Tsukasa Endo, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Information Engineering Express
- Journal Title
  
  Information Engineering Express
  
  Volume: 3 Pages: 77-90
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-16K12404
[Journal Article] Hardware-Oriented Succinct-Data-Structure for Text Processing Based on Block-Size-Constrained Compression2016
- Author(s)
  Hasitha Muthumala Waidyasooriya, Daisuke Ono and Masanori Hariyama
- Journal Title
  
  International Journal of Computer Information Systems and Industrial Management Applications
  
  Volume: 8 Pages: 1-11
- Peer Reviewed / Acknowledgement Compliant / Open Access
- Data Source
  KAKENHI-PROJECT-24300013
[Journal Article] Evaluation of an OpenCL-Based FPGA Platform for Particle Filter2016
- Author(s)
  S. Tatsumi, M. Hariyama, and N. Ikoma
- Journal Title
  
  Journal of Advanced Computational Intelligence and Intelligent Informatics
  
  Volume: 20 Pages: 743-754
- NAID
  130007673350
- Peer Reviewed / Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-16K12404
[Journal Article] Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators2015
- Author(s)
  Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama and Michitaka Kameyama
- Journal Title
  
  IEICE Trans. Fundamentals
  
  Volume: E98.A Issue: 12 Pages: 2658-2669
- DOI
  10.1587/transfun.E98.A.2658
- NAID
  130005111969
- ISSN
  0916-8508, 1745-1337
- Language
  English
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-15J04973, KAKENHI-PROJECT-24300013, KAKENHI-PROJECT-25280011
[Journal Article] FDTD Acceleration for Cylindrical Resonator Design Based on the Hybrid of Single and Double Precision Floating-Point Computation2014
- Author(s)
  Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Yasuhiro Takei, and Michitaka Kameyama
- Journal Title
  
  Journal of Computational Engineering
  
  Volume: 2014 Pages: 1-8
- DOI
  10.1155/2014/634269
- Peer Reviewed / Acknowledgement Compliant / Open Access
- Data Source
  KAKENHI-PROJECT-24300013
[Journal Article] Evaluation of an FPGA-Based Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators2013
- Author(s)
  Yasuhiro Takei, Hasitha Muthumala WAIDYASOORIYA, Masanori Hariyama, Michitaka Kameyama
- Journal Title
  
  IEICE Transaction on Information and Systems
  
  Volume: E96-A,No.12 Pages: 2576-2586
- NAID
  130003385311
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-24300013
[Journal Article] rchitecture of an Asynchronous FPGA for Handshake-Component-Based Design2013
- Author(s)
  Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
- Journal Title
  
  IEICE Transaction on Information and Systems
  
  Volume: Vol.E96-D, No.8 Pages: 1632-1644
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-24300013
[Journal Article] 腫瘍領域情報に基づく肝臓切除容量最小化ための門脈切除点計算2013
- Author(s)
  岡田萌*, 張山昌論*, 亀山充隆*, 下田貢
- Journal Title
  
  計測自動制御学会東北支部　第279回研究集会
  
  Volume: 279 Pages: 279-3
- Data Source
  KAKENHI-PROJECT-24500242
[Journal Article] Platform and Mapping Methodology for Heterogeneous Multicore Processors2012
- Author(s)
  Masanori Hariyama, Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Michitaka Kameyama
- Journal Title
  
  IIS
  
  Volume: 18 Issue: 2 Pages: 175-184
- DOI
  10.4036/iis.2012.175
- NAID
  130002531678
- ISSN
  1340-9050, 1347-6157
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-11F01347, KAKENHI-PROJECT-24300013
[Journal Article] Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation2012
- Author(s)
  Yoshitaka Hiramatsu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Toru Nojiri, Kunio Uchiyaroa, Michitaka Kameyama
- Journal Title
  
  IEICE Trans. Electron.
  
  Volume: E95.C Issue: 12 Pages: 1872-1882
- DOI
  10.1587/transele.E95.C.1872
- NAID
  10031161435
- ISSN
  0916-8524, 1745-1353
- Language
  English
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-11F01347, KAKENHI-PROJECT-24300013
[Journal Article] Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture2011
- Author(s)
  Shota ISHIHARA, Ryoto TSUCHIYA Yoshiya KOMATSU, Masanori HARIYAMA , Michitaka KAMEYAMA
- Journal Title
  
  IEICE Trans. Elec
  
  Volume: Vol.E-94-C, No.10 Pages: 1669-1679
- NAID
  10030189959
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21700052
[Journal Article] A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating2011
- Author(s)
  Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
- Journal Title
  
  IEEE Trans. VLSI Systems
  
  Volume: Vol.19, No.8 Pages: 1394-1406
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21700052
[Journal Article] Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture2011
- Author(s)
  Shota ISHIHARA, Ryoto TSUCHIYA, Yoshiya KOMATSU, Masanori HARIYAMA, Michitaka KAMEYAMA
- Journal Title
  
  IEICE Transaction on Electron
  
  Volume: E-94-C Pages: 1669-1679
- NAID
  10030189959
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21700052
[Journal Article] A Switch Block for Multi-Context FPGAs Based on Floating-Gate-MOS Functional Pass-Gates Using Multiple/Binary Valued Hybrid Signals2011
- Author(s)
  Shota Ishihara, Noriaki Idobata, Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama
- Journal Title
  
  Journal of Multiple-Valued Logic and Soft Computing
  
  Volume: 17 Pages: 553-580
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21700052
[Journal Article] A Switch Block for Multi-Context FPGAs Based on Floating-Gate-MOS Functional Pass-Gates Using Multiple/Binary Valued Hybrid Signals2011
- Author(s)
  Shota Ishihara, Noriaki Idobata, Yoshihiro Nakatani, Masanori Hariyama and Michitaka Kameyama
- Journal Title
  
  Journal of Multiple-Valued Logic and Soft Computing
  
  Volume: Vol.17, No.5-7 Pages: 553-580
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21700052
[Journal Article] A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating2011
- Author(s)
  Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
- Journal Title
  
  IEEE Transactions on Very Large Scale Integration Systems
  
  Volume: 19 Pages: 1394-1406
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21700052
[Journal Article] A Switch Block Architecture for Multi-Context FPGAs Based on Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals2010
- Author(s)
  S.Ishihara, N.Idobata, M.Hariyama, M.Kameyama
- Journal Title
  
  IEICE Transaction on Information and Systems
  
  Volume: Vol.E93-D, No.8 Pages: 2134-2144
- NAID
  10027364639
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21700052
[Journal Article] Synchronising logic gates for wave-pipelining design2010
- Author(s)
  Z.Xia, S.Ishihara, M.Hariyama, M.Kameyama
- Journal Title
  
  Electronics Letters
  
  Volume: Vol.46,No.16 Pages: 1116-1117
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21700052
[Journal Article] Evaluation of a Self-Adaptive Voltage Control Scheme for Low-Power FPGAs2010
- Author(s)
  Shota Ishihara, Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama
- Journal Title
  
  Journal of Semiconductor Technology and Science
  
  Volume: Vol.10, No.3 Pages: 165-175
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21700052
[Journal Article] A Switch Block Architecture for Multi-Context FPGAs Based on Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals2010
- Author(s)
  Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama
- Journal Title
  
  EICE Transaction on Information and Systems
  
  Volume: Vol.E93-D, No.8 Pages: 2134-2144
- NAID
  10027364639
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21700052
[Journal Article] 自律適応電源電圧制御に基づく低消費電力FPGAの構成2010
- Author(s)
  石原翔太, 夏徴帆, 張山昌論, 亀山充隆
- Journal Title
  
  自律適応電源電圧制御に基づく低消費電力FPGAの構成 RECONF2009-69
  
  Pages: 95-99
- NAID
  110007999793
- Data Source
  KAKENHI-PROJECT-21700052
[Journal Article] An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture2010
- Author(s)
  Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
- Journal Title
  
  IEICE Trans. on Elec
  
  Volume: Vol.E93-C, No.8 Pages: 1338-1348
- NAID
  10027366062
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21700052
[Journal Article] An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture2010
- Author(s)
  S.Ishihara, Y.Komatsu, M.Hariyama, M.Kameyama
- Journal Title
  
  IEICE Transactions on Electronics
  
  Volume: Vol.E93-C,No.8 Pages: 1338-1348
- NAID
  10027366062
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21700052
[Journal Article] An Field-Programmable VLSI Based on Synchronous/Asynchronous Hybrid Architecture2010
- Author(s)
  M.Hariyama, R.Tsuchiya, S.Ishihara, M.Kameyama
- Journal Title
  
  Proc.International Conference on Engineering of Reconfigurable Systems and Algorithms
  
  Pages: 271-274
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21700052
[Journal Article] A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic2009
- Author(s)
  S.Ishihara, N.Idobata, M.Hariyama, M.Kameyama
- Journal Title
  
  Proc.International Conference on Engineering of Reconfigurable Systems and Algorithms
  
  Pages: 236-266
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21700052
[Journal Article] Architecture of a Low-Power FPGA Based on Self-Adaptive Voltage Control2009
- Author(s)
  石原翔太, 夏徴帆, 張山昌論, 亀山充隆
- Journal Title
  
  Proc.International SoC Design Conference
  
  Pages: 274-277
- NAID
  110007999793
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-21700052
[Journal Article] Design of a Multi-Context FPVLSI based on an AsynchronousBit-Serial Architecture2007
- Author(s)
  Waidyasooriya Hasitha Muthumala, Masanori Hariyama, and Michitaka Kameyama
- Journal Title
  
  Sixth IEEE Dallas Circuits and SystemsWorkshop
  
  Pages: 59-62
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 細粒度アーキテクチャに基づくフィールドプログラマブルVLSIの開発2007
- Author(s)
  張山昌論, 亀山充隆
- Journal Title
  
  電子情報通信学会エレクトロニクスソサイエティ大会 C-12-11
  
  Pages: 66-66
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 超高速ステレオビジョンVLSIプロセッサの設計2007
- Author(s)
  張山昌論, 横山直人, 吉田恒, 亀山充隆
- Journal Title
  
  第13回画像センシングシンポジウム予稿集
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] ウィンドウ演算のための最適スケジューリング・メモリアロケーション2007
- Author(s)
  小林康浩, 張山昌論, 亀山充隆
- Journal Title
  
  電子情報通信学会論文誌 Vo1. J90-D, No.5
  
  Pages: 1178-1193
- NAID
  110007380712
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 形状特徴を用いた人物抽出アルゴリズムとそのVLSIアーキテクチャ2007
- Author(s)
  橋本翔太, 佐々木明夫, 張山昌論, 亀山充隆
- Journal Title
  
  電子情報通信学会信学技報 Vol.107,No.382,ICD2007-13
  
  Pages: 77-82
- NAID
  110006546968
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] ウィンドウ演算のための最適スケジューリング・メモリアロケーション2007
- Author(s)
  小林康浩, 張山昌論, 亀山充隆
- Journal Title
  
  電子情報通信学会論文誌 Vol.J90-D,No.5
  
  Pages: 1178-1193
- NAID
  110007380712
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] A Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture2007
- Author(s)
  Masanori Hariyama, Shota Ishihara, Chang Chia Wei and Michitaka Kameyama
- Journal Title
  
  IEEE Asian Solid-State Circuits Conference
  
  Pages: 380-383
- NAID
  110006546969
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 相互結合網簡単化を考慮した遺伝的アルゴリズムに基づく電源・しきい値電圧割当2007
- Author(s)
  ウィシディスーリヤハシタムトゥマラ, 張山昌論, 亀山充隆
- Journal Title
  
  電子情報通信学会技術報告 ICD2007-31
  
  Pages: 85-90
- NAID
  110006291420
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Design of a Multi-Context FPVLSI based on an Asynchronous Bit-Serial Architecture2007
- Author(s)
  Waidyasooriya Hasitha Muthumala, Masanori Hariyama, and Michitaka Kameyama
- Journal Title
  
  Sixth IEEE Dallas Circuits and Systems Workshop
  
  Pages: 59-62
- NAID
  120001182116
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 非同期ビットシリアルアーキテクチャに基づくフィールドプログラマブルVLSIの構成2007
- Author(s)
  石原翔太, 張山昌論, 亀山充隆
- Journal Title
  
  電気関係学会東北支部連合大会 2E18
  
  Pages: 192-192
- NAID
  130005444444
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 相互結合網簡単化を考慮した遺伝的アルゴリズムに基づく電源・しきい値電圧割当2007
- Author(s)
  ウィシディスーリヤハシタムトゥマラ, 張山昌論, 亀山充隆
- Journal Title
  
  電子情報通信学会技術報告 ICD2007-31
  
  Pages: 85-90
- NAID
  110006291420
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] データ圧縮に基づく画像処理VLSIアーキテクチャとその応用2007
- Author(s)
  吉田恒, 小林康浩, 張山昌論, 亀山充隆
- Journal Title
  
  電子情報通信学会技術研究報告 ICD2007-100
  
  Pages: 11-14
- NAID
  110006453357
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 3次元情報を用いた車両検出アルゴリズムとそのVLSIアーキテクチャ2007
- Author(s)
  山下健策, 佐々木明夫, 張山昌論, 亀山充隆
- Journal Title
  
  電子情報通信学会技術研究報告 ICD2007-99
  
  Pages: 5-9
- NAID
  110006453356
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Design of a Multi-Context FPVLSI based on an AsynchronousBit-Serial Architecture2007
- Author(s)
  Waidyasooriya Hasitha Muthumala, Masanori Hariyama, and Michitaka Kameyama
- Journal Title
  
  Sixth IEEE Dallas Circuits and Systems Workshop
  
  Pages: 59-62
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 形状特徴を用いた人物抽出アルゴリズムとそのVLSIアーキテクチャ2007
- Author(s)
  橋本翔太, 佐々木明夫, 張山昌論, 亀山充隆
- Journal Title
  
  電子情報通信学会信学技報 Vol.107, No.38 2,ICD-2007-133
  
  Pages: 77-82
- NAID
  110006546968
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 高安全自動車道路抽出のための動的再構成アーキテクチャ2006
- Author(s)
  李承啓, 張山昌論, 亀山充隆
- Journal Title
  
  電子情報通信学会集積回路研究会(信学技報) ICD2006-51
  
  Pages: 63-67
- Data Source
  KAKENHI-PROJECT-16700160
[Journal Article] Optimal Periodical Memory Allocation for Logic-in-Memory Imag Processors2006
- Author(s)
  Masanori Hariyama, Michitaka Kameyama, and Yasuhiro Kobayashi
- Journal Title
  
  IEEE Computer Society Anual Symposium on VLSI
  
  Pages: 193-196
- NAID
  120001182132
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Processor Architecture for Road Extraction Based on Projective Transformation2006
- Author(s)
  Sunggae Lee, Masanori Hariyama, Michitaka Kameyama
- Journal Title
  
  SICE-ICCAS
  
  Pages: 1446-1450
- NAID
  110004748907
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Dynamically Reconfigurable Gata Array Based on Fine-Grained Switch Elements and Its CAD Environment2006
- Author(s)
  Masanori hariyama, Waidyasoority Hasitha muthumala, and Michitaka Kameyama
- Journal Title
  
  Proc. Asian Solid-State Circuits conference
  
  Pages: 155-158
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Optimal Periodical Memory Allocation for Logic-in-memory imag Processors2006
- Author(s)
  Masanori Hariyama, Michitaka kameyama, and yasuhiro Kobayashi
- Journal Title
  
  IEEE Computer Society Anual Symposium on VLSI
  
  Pages: 193-198
- NAID
  120001182132
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Processor Architecture for Road Extraction Based on Projective Transformation2006
- Author(s)
  Sunggae Lee, masanori Hariyama and Michitaka Kameyama
- Journal Title
  
  SICE-ICCAS
  
  Pages: 1446-1450
- NAID
  110004748907
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] ウィンドウ並列・ピクセル並列アーキテクチャに基づくステレオビジョンプロセッサ2006
- Author(s)
  横山直人, 張山昌諭, 小林康浩, 亀山充隆
- Journal Title
  
  電子情報通信学会集積回路研究会(信学技報) ICD2005-212
  
  Pages: 43-46
- NAID
  10017255609
- Data Source
  KAKENHI-PROJECT-16700160
[Journal Article] 1000frame/sec Stereo Matching VLSI Processor with Adaptive Window-Size Control2006
- Author(s)
  Masanori Hariyama, Naoto Yokoyama, Michitaka Kameyama
- Journal Title
  
  Proc. Asian Solid-State Circuits Conference
  
  Pages: 123-126
- NAID
  120001182113
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 高安全自動車道路抽出のための動的再構成可能アーキテクチャ2006
- Author(s)
  李承啓, 張山昌論, 亀山充隆
- Journal Title
  
  電子情報通信学会技術報告 ICD2006-51
  
  Pages: 63-67
- NAID
  110004748907
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 画像処理プロセッサのための最適メモリアロケーション2006
- Author(s)
  張山昌論, 小林康浩, 亀山充隆
- Journal Title
  
  電子情報通信学会技術報告 ICD2006-57
  
  Pages: 95-100
- NAID
  110004748913
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 1000 frame/sec Stereo Matching VLSI Processor with Adaptive Window-Size Control2006
- Author(s)
  M.Hariyama, N.Yokoyama, M.Kameyama
- Journal Title
  
  Proc. Asian Solid-State Circuits Conference
  
  Pages: 123-126
- NAID
  120001182113
- Data Source
  KAKENHI-PROJECT-16700160
[Journal Article] 最適スケジューリングに基づく3眼ステレオビジョンVLSIプロセッサの構成2006
- Author(s)
  横山直人, 張山昌論, 亀山充隆
- Journal Title
  
  電子情報通信学会集積回路研究会(信学技報) ICD2006-153
  
  Pages: 55-60
- NAID
  10018707021
- Data Source
  KAKENHI-PROJECT-16700160
[Journal Article] Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification2006
- Author(s)
  Masanori HARIYAMA, Shigeo YAMADERA, and Michitaka KAMEYAMA
- Journal Title
  
  IEICE Trans. Electron. Vol. E89-C, No. 11
  
  Pages: 1551-1558
- NAID
  110007538691
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 1000frame/sec Stereo Mateching VLSI Processor with Adaptive Window-Size Control2006
- Author(s)
  Masanori Hariyama, Nato Yokoyama and Michitaka Kameyama
- Journal Title
  
  Proc. Asian Solid-State Circuits Conference
  
  Pages: 123-126
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Processor Architecture for Road Extraction Based on Projective Transformation2006
- Author(s)
  S.Lee, M.Hariyama, M.Kameyama
- Journal Title
  
  Proc. SICE-ICCAS
  
  Pages: 1446-1450
- NAID
  110004748907
- Data Source
  KAKENHI-PROJECT-16700160
[Journal Article] 画像処理プロセッサのための最適メモリアロケーション2006
- Author(s)
  張山昌論, 小林康浩, 亀山充隆
- Journal Title
  
  電子情報通信学会集積回路研究会(信学技報) ICD2006-57
  
  Pages: 95-100
- NAID
  110004748913
- Data Source
  KAKENHI-PROJECT-16700160
[Journal Article] GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design2006
- Author(s)
  Waidyasooriya Hasitha Muthumala, Masanori Hariyama, and Michitaka, Kameyama
- Journal Title
  
  IEEE Asia Pacific Conference on Circuits and Systems
  
  Pages: 1266-1269
- NAID
  110006291420
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design2006
- Author(s)
  Waidyasooriya Hasitha Muthumala, Masanori Hariyama, andMichitaka, Kameyama
- Journal Title
  
  IEEE Asia Pacific Conference on Circuits and Systems
  
  Pages: 1266-1269
- NAID
  110006291420
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Dynamically Reconfigurable Gate Array Based on Fine-Grained Switch Elements and Its CAD Environment2006
- Author(s)
  Masanori Hariyama, Waidyasooriya Hasitha Muthumala, and Michitaka Kameyama
- Journal Title
  
  Proc. Asian Solid-State Circuits Conference
  
  Pages: 155-158
- NAID
  120001182114
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Dynamically Reconfigurable Gate Array Based on Fine-Grained Switch Elements and Its CAD Environment2006
- Author(s)
  Masanori Hariyama, Waidyasooriya Hasitha Muthumala, Michitaka Kameyama
- Journal Title
  
  Proc. Asian Solid-State Circuits Conference
  
  Pages: 155-158
- NAID
  120001182114
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 多値・二値ハイブリッドコンテクストスイッチング信号を用いたマルチコンテクストFPGAのアーキテクチャ2006
- Author(s)
  中谷好博, 張山昌論, 亀山充隆
- Journal Title
  
  電子情報通信学会技術報告 ICD2005-211
  
  Pages: 37-42
- NAID
  10017255603
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 1000frame/sec Stereo Matching VLSI Processor with Adaptive Window-Size Control2006
- Author(s)
  Masanori Hariyama, Naoto Yokoyama and Michitaka Kameyama
- Journal Title
  
  Proc. Asian Solid-State Circuits Conference
  
  Pages: 123-126
- NAID
  120001182113
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 最適スケジューリングに基づく3眼ステレオビジョンVLSIプロセッサの構成2006
- Author(s)
  横山直人, 張山昌論, 亀山充隆
- Journal Title
  
  電子情報通信学会技術報告 ICD-2006-153
  
  Pages: 55-60
- NAID
  10018707021
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Processor Architecture for Road Extraction Based on Projective Transformation2006
- Author(s)
  Sunggae Lee, Masanori Hariyama and Michitaka Kameyama
- Journal Title
  
  SICE-ICCAS
  
  Pages: 1446-1450
- NAID
  110004748907
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors2006
- Author(s)
  MasanoriHariyama, Michitaka Kameyama, Yasuhiro Kobayashi
- Journal Title
  
  IEEE Computer Society Anual Symposium on VLSI
  
  Pages: 193-198
- NAID
  120001182132
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification2006
- Author(s)
  Masanori HARIYAMA, Shigeo YAMADERA, and Michitaka KAMEYAMA
- Journal Title
  
  IEICE Trans. Electron Vol. E89-C, No. 11
  
  Pages: 1551-1558
- NAID
  110007538691
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] ウィンドウ並列・ピクセル並列アーキテクチャに基づくステレオビジョンプロセッサ2006
- Author(s)
  横山直人, 張山昌論, 小林康浩, 亀山充隆
- Journal Title
  
  電子情報通信学会技術報告 ICD2005-212
  
  Pages: 43-46
- NAID
  10017255609
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification2006
- Author(s)
  MasanoriHARIYAMA, Shigeo YAMADERA, Michitaka KAMEYAMA
- Journal Title
  
  IEICE Trans. Electron. Vol.E89-C, No.11
  
  Pages: 1551-1558
- NAID
  110007538691
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design2006
- Author(s)
  Waidyasooriya Hasitha Muthumala, Masanori Hariyama, Michitaka, Kameyama
- Journal Title
  
  IEEE Asia Pacific Conference on Circuits and Systems
  
  Pages: 1266-1269
- NAID
  110006291420
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Minimizing Energy Consumption of VLSI Processors Based on Dual-Supply-Voltage Assignment and Interconnection Simpoification2005
- Author(s)
  Masanori Hariyama, Shigeo Yamadera and Michitaka Kameyama
- Journal Title
  
  Proc. 48th IEEE International Midwest Symposium on Circuits and Systems
  
  Pages: 1867-1870
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] FPGAImplementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture2005
- Author(s)
  Masanori Hariyama, Yasuhiro Kobayashi, Haruka Sasaki, and Michitaka Kameyama
- Journal Title
  
  IEICE Trans. Fundamentals Vol.E88-A,No.12
  
  Pages: 3516-3522
- NAID
  110004019457
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] ウィンドウ並列・ピクセル並列スケジューリングに基づく高信頼ステレオマッチングVLSIのアーキテクチャ2005
- Author(s)
  横山直人, 張山昌論, 亀山充隆
- Journal Title
  
  電気関係学会東北支部連合大会 2I8
  
  Pages: 328-328
- NAID
  130005443855
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 対応点探索と差分画像処理に基づく道路抽出アルゴリズム2005
- Author(s)
  李承啓, 張山昌論, 亀山充隆
- Journal Title
  
  電気関係学会東北支部連合大会 2G14
  
  Pages: 260-260
- NAID
  130005443759
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Novel Switch Block Architecture Using Non-Volatile Functional Pass-gate for Multi-Context FPGAs2005
- Author(s)
  Masanori Hariyama, Weisheng Chong, Sho Ogata, Michitaka Kameyama
- Journal Title
  
  Proc. IEEE Computer Society Annual Conference on vlsi
  
  Pages: 46-50
- NAID
  120001182131
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture2005
- Author(s)
  M.Hariyama, Y.Kobayashi, H.Sasaki, M.Kameyama
- Journal Title
  
  IEICE Trans.Fundamentals Vol.E88-A, No.12
  
  Pages: 3516-3522
- NAID
  110004019457
- Data Source
  KAKENHI-PROJECT-16700160
[Journal Article] Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages2005
- Author(s)
  Masanori Hariyama, Tetsuya Aoyama, and Michitaka Kameyama
- Journal Title
  
  IEEE Transaction on Computers Vol.54,No.6
  
  Pages: 642-650
- NAID
  120001182139
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Design of Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate2005
- Author(s)
  Masanori Hariyama, Sho Ogata, Michitaka Kameyama, Yasutoshi Morita
- Journal Title
  
  IEEE Asian Solid-State Circuits Conference(A-SSCC)
  
  Pages: 421-424
- NAID
  120001182112
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Low-Power Field-Programmalble VLSI Using Multiple Supply Voltages2005
- Author(s)
  Weisheng Chong, Masanori Hariyama, Michitaka Kameyama
- Journal Title
  
  IEICE Trans. Fundamentals Vol. E88-A No. 12
  
  Pages: 3298-3305
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Low-Power Field-Programmalble VLSI Using Multiple Supply Voltages2005
- Author(s)
  Weisheng Chong, Masanori Hariyama, Michitaka Kameyama
- Journal Title
  
  IEICE Trans. Fundamentals Vol.E88-A No.12,
  
  Pages: 3298-3305
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] DSP-Specific Field-Programmable VLSI and Its CAD Environment2005
- Author(s)
  Masanori Hariyama, Sho Ogata, and Michitaka Kameyama
- Journal Title
  
  Proc. 48th IEEE International Midwest Symposium on Circuits and Systems
  
  Pages: 651-654
- NAID
  120001182135
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architectgure2005
- Author(s)
  Masanori Hariyama, Yasuhiro Kobayashi, naoto Yokoyama, and Michitaka Kameyama
- Journal Title
  
  Proc. 48th IEEE International Midwest Symposium on Circuits and Systems
  
  Pages: 1219-1222
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory2005
- Author(s)
  Weisheng Chong, Sho Ogata, Masanori Hariyama and Michitaka Kameyama
- Journal Title
  
  Proc. International Parallel and Distributed Processing Symposium CD-ROM
- NAID
  110003318215
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] 機能パスゲートを用いたマルチコンテクストFPGA2005
- Author(s)
  中谷好博, 張山昌論, 亀山充隆
- Journal Title
  
  電気関係学会東北支部連合大会 2I9
  
  Pages: 329-329
- NAID
  130005443858
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel and Pixel-Parallel Architecture2005
- Author(s)
  M.Hariyama, N.Yokoyama, M.Kameyama, Y.Kobayashi
- Journal Title
  
  IEEE International Midwest Symposium on Circuits and Systems (CD-ROM)
- NAID
  110004019457
- Data Source
  KAKENHI-PROJECT-16700160
[Journal Article] Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access2005
- Author(s)
  Masanori Hariyama, Haruka Sasaki, and Michitaka Kameyama
- Journal Title
  
  IEICE Trans. Inf. & Syst. Vol.E88-D,No.7
  
  Pages: 1486-1491
- NAID
  110003214339
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages2005
- Author(s)
  Masanori Hariyama, Tetsuya Aoyama, Michitaka Kameyama
- Journal Title
  
  IEEE Transaction on Computers Vol.54, No.6
  
  Pages: 642-650
- NAID
  120001182139
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Minimizing Energy Consumption of VLSI Processors Based on Dual-Supply-Voltage Assignment and Interconnection Simpoification2005
- Author(s)
  Masanori Hariyama, Shigeo Yamadera, Michitaka Kameyama
- Journal Title
  
  Proc.48th IEEE International Midwest Symposium on Circuits and Systems
  
  Pages: 3201-3201
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Low-Power Field-Programmalble VLSI Using Multiple Supply Voltages2005
- Author(s)
  Weisheng Chong, Masanori Hariyama, Michitaka Kameyama
- Journal Title
  
  IEICE Trans.Fundamentals Vol.E88-A, No.12
  
  Pages: 3298-3305
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture2005
- Author(s)
  Masanori Hariyama, Yasuhiro Kobayashi, Haruka Sasaki, Michitaka Kameyama
- Journal Title
  
  IEICE Trans.Fundamentals Vol.E88-A, No.12
  
  Pages: 3516-3522
- NAID
  110004019457
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture2005
- Author(s)
  Masanori Hariyama, Yasuhiro Kobayashi, Naoto Yokoyama, Michitaka Kameyama
- Journal Title
  
  Proc.48th IEEE International Midwest Symposium on Circuits and Systems
  
  Pages: 3194-3194
- NAID
  110004019457
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access2005
- Author(s)
  Masanori Hariyama, Haruka Sasaki, Michitaka Kameyama
- Journal Title
  
  IEICE Trans.Inf.& Syst. Vol.E88-D, No.7
  
  Pages: 1486-1491
- NAID
  110003214339
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Design of Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate2005
- Author(s)
  Masanori Hariyama, Sho Ogata, and Michitaka Kameyama, yasutoshi Morita
- Journal Title
  
  IEEE Asian Solid-State Circuits Conference(A-SSCC)
  
  Pages: 421-424
- NAID
  120001182112
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Novel Switch Block Architecture Using Non-Volatile Functional Pass-gate for Multi-Context FPGAs2005
- Author(s)
  Masanori Hariyama, Weisheng Chong, Sho Ogata, Michitaka Kameyama
- Journal Title
  
  Proc. IEEE Computer Society Annual Conference on VLSI
  
  Pages: 46-50
- NAID
  120001182131
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Genetic Approach to Minimizing Energy Consumption of VLSI Processors using Multiple Supply voltages2005
- Author(s)
  Masanori Hariyama, Tetsuya Aoyama, and Michitaka Kameyama
- Journal Title
  
  IEEE Transaction on Computers Vol. 54, No. 6
  
  Pages: 642-650
- NAID
  120001182139
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] DSP-Specific Field-Programmable VLSI and Its CAD Environment2005
- Author(s)
  Masanori Hariyama, Sho Ogata, Michitaka Kameyama
- Journal Title
  
  Proc.48th IEEE International Midwest Symposium on Circuits and Systems
  
  Pages: 3199-3199
- NAID
  120001182135
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access2005
- Author(s)
  Masanori Hariyama, Haruka Sasaki, and Michitaka Kameyama
- Journal Title
  
  ELCE Trans. Inf. & Syst Vol. E88-D, No. 7
  
  Pages: 1486-1491
- NAID
  110003214339
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architectgure2005
- Author(s)
  Masanori Hariyama, Yasuhiro Kobayashi, Naoto Yokoyama, and Michitaka Kameyama
- Journal Title
  
  Proc. 48th IEEE International Midwest Symposlum on Circuits and Systems
  
  Pages: 1219-1222
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Novel Switch Block Architecture Using Non-Volatile Functional Pass-gate for Multi-Context FPGAs2005
- Author(s)
  Masanori Hariyama, Weisheng Chong, Sho Ogata, Michitaka Kameyama
- Journal Title
  
  Proc.IEEE Computer Society Annual Conference on VLSI
  
  Pages: 46-50
- NAID
  120001182131
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory2005
- Author(s)
  Weisheng Chong, Sho Ogata, Masanori Haariyama, Michitaka Kameyama
- Journal Title
  
  Proc.International Parallel and Distributed Processing Symposium
- NAID
  110003318215
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] ウィンドウ並列・ピクセル並列スケジューリングに基づく高信頼ステレオマッチングVLSIのアーキテクチャ2005
- Author(s)
  横山直人, 張山昌論, 亀山充隆
- Journal Title
  
  電気関係学会東北支部連合大会 2I8
  
  Pages: 328-328
- NAID
  130005443855
- Data Source
  KAKENHI-PROJECT-16700160
[Journal Article] Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory2005
- Author(s)
  Weisheng Chong, Sho Ogata, masanori hariyama and Michitaka Kameyama
- Journal Title
  
  Proc. International Parallel and Distributed Processing Symposium, CD-ROM (CD-ROM)
- NAID
  110003318215
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] FPGAImplementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture2005
- Author(s)
  Masanori Hariyama, yasuhiroKobayashi, Haruka Sasaki, and Michitaka Kameyama
- Journal Title
  
  IEICE Trans. Fundamentals Vol. E88-A, No. 12
  
  Pages: 3516-3522
- NAID
  110004019457
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access2005
- Author(s)
  M.Hariyama, H.Sasaki, M.Kameyama
- Journal Title
  
  IEICE Trans.Inf.& Syst. Vol.E88-D, No.7
  
  Pages: 1486-1491
- NAID
  110003214339
- Data Source
  KAKENHI-PROJECT-16700160
[Journal Article] Design of Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate2005
- Author(s)
  Masanori Hariyama, Sho Ogata, and Michitaka Kameyama, Yasutoshi Morita
- Journal Title
  
  IEEE Asian Solid-State Circuits Conference (A-SSCC)
  
  Pages: 421-424
- NAID
  120001182112
- Description
  「研究成果報告書概要(和文)」より
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-17300009
[Journal Article] アクティブステレオビジョンを用いた捕球ロボットシステムの構成2004
- Author(s)
  佐々木明夫, 張山昌論, 亀山充隆
- Journal Title
  
  電気関係学会東北支部連合大会予稿集
  
  Pages: 311-311
- NAID
  130005443519
- Data Source
  KAKENHI-PROJECT-16700160
[Journal Article] Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access2004
- Author(s)
  Masanori Hariyama, Haruka Sasaki, Michitaka Kameyama
- Journal Title
  
  Proc.International Midwest Symposium on Circuits and Systems
  
  Pages: 245-247
- NAID
  110003214339
- Data Source
  KAKENHI-PROJECT-16700160
[Journal Article] 高速軌道予測に基づく捕球ロボットシステム2004
- Author(s)
  佐々木明夫, 張山昌論, 亀山充隆
- Journal Title
  
  計測自動制御学会東北支部40周年記念学術講演会予稿集
  
  Pages: 53-56
- Data Source
  KAKENHI-PROJECT-16700160
[Journal Article] 最適スケジューリングに基づくステレオビジョンVLSIプロセッサ2004
- Author(s)
  張山昌論, 亀山充隆
- Journal Title
  
  電子情報通信学会技術研究報告 ICD2004-99
  
  Pages: 11-15
- NAID
  10014032564
- Data Source
  KAKENHI-PROJECT-16700160
[Journal Article] VLSI Processor for Reliable Stereo Matching Based on Window-Parallel Logic-in-Memory Architecture2004
- Author(s)
  Masanori Hariyama, Michitaka Kameyama
- Journal Title
  
  Digest of Technical Paper 2004 Symposium on VLSI Circuits VLSI Symposium
  
  Pages: 166-169
- Data Source
  KAKENHI-PROJECT-16700160
[Presentation] 大規模問題に対応可能なFPGAベース量子アニーリングシミュレータ2021
- Author(s)
  張山昌論
- Organizer
  ウェイビナー「実世界を最適化するための量子コンピューティングおよび量子に着想を得た計算手法」
- Invited
- Data Source
  KAKENHI-PROJECT-20H04197
[Presentation] Intelligent Computing Technologies Related to Materials Informatics2021
- Author(s)
  Masanori Hariyama
- Organizer
  Webinar on Materials and Systems Under Extreme Conditions
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-20H04197
[Presentation] 大規模問題に対応可能なFPGAベース量子アニーリングシミュレータの展望2021
- Author(s)
  張山昌論
- Organizer
  量子コンピューティングEXPO
- Invited
- Data Source
  KAKENHI-PROJECT-20H04197
[Presentation] 創発性・協働性を促す外遊びの中の発話の園児間構造分析が示唆する発達2019
- Author(s)
  金澤亮、Kevin Jay Singh、鈴木峻介、花朱迪、陶テイ、横田澄絵、久保田健夫、仙田満、谷口新、大豆生田啓友、小柴満美子、渡辺英則、張山昌論
- Organizer
  こども環境学会2019年大会
- Data Source
  KAKENHI-PROJECT-18K18663
[Presentation] ３D-CTシミュレーションから超音波３D画像を用いたナビゲーションシステムの構築.2019
- Author(s)
  下田貢, 張山昌論, 大城幸雄, 鈴木修司
- Organizer
  第44回日本外科系連合学会学術集会
- Data Source
  KAKENHI-PROJECT-16H02899
[Presentation] Construction of ３D navigation system using ultrasound.2019
- Author(s)
  下田貢, 張山昌論, 大城幸雄, 鈴木修司
- Organizer
  第31回日本肝胆膵外科学会学術集会
- Data Source
  KAKENHI-PROJECT-16H02899
[Presentation] あそび学ぶ状態推移計測：音声・環境音解析2018
- Author(s)
  陶テイ、伊藤幸子、嶋崎さなえ、渡辺英則、谷口新、仙田満、大豆生田啓友、久保田健夫、張山昌論、小柴満美子.
- Organizer
  こども環境学会2018年大会
- Data Source
  KAKENHI-PROJECT-18K18663
[Presentation] 術前肝機能を考慮した最適肝切除領域自動抽出ソフトウエアの開発(会議録)2018
- Author(s)
  下田貢、張山昌論, 鈴木修司
- Organizer
  第１１８回日本外科学会定期学術集会
- Data Source
  KAKENHI-PROJECT-16H02899
[Presentation] 離散最適化問題のためのFPGAベースk-out-of-n生成器の構成2017
- Author(s)
  平舘侑樹，Waidyasooriya Hasitha Muthumala，張山昌論
- Organizer
  第32回信号処理シポジウム
- Data Source
  KAKENHI-PROJECT-16K12404
[Presentation] LDAベース推論のためのFPGAアクセラレータ設計2017
- Author(s)
  小野泰輔，Waidyasooriya Hasitha Muthumala，張山昌論，石垣司
- Organizer
  第32回信号処理シポジウム
- Data Source
  KAKENHI-PROJECT-16K12404
[Presentation] OpenCLを用いたステンシル計算用FPGAアクセラレータの最適設計2017
- Author(s)
  遠藤司，Waidyasooriya Hasitha Muthumala，張山昌論
- Organizer
  第32回信号処理シポジウム
- Data Source
  KAKENHI-PROJECT-16K12404
[Presentation] OpenCLを用いた位相限定相関法のためのFPGAアクセラレータの評価2016
- Author(s)
  張山昌論
- Organizer
  電子情報通信学会技術報告(信学技報)，リコンフィギャラブルシステム研究会
- Place of Presentation
  富士通研究所（神奈川県・川崎市）
- Year and Date
  2016-05-20
- Data Source
  KAKENHI-PROJECT-16K12404
[Presentation] FPGA Architecture for 3-D FDTD Acceleration Using OpenCL2016
- Author(s)
  Hasitha Muthumala Waidyasooriya, Masanori Hariyama and Yasuo Ohtera
- Organizer
  Progress in Electromagnetics Research Symposium (PIERS)
- Place of Presentation
  Shanghai, CHINA
- Year and Date
  2016-08-08
- Data Source
  KAKENHI-PROJECT-24300013
[Presentation] OpenCL-based Design of an FPGA Accelerator for Phase-Based Correspondence Matching2015
- Author(s)
  Shunsuke Tatsumi, Masanori Hariyama, Mamoru Miura, Koichi Ito, Takafumi Aoki
- Organizer
  International Conference on Parallel and Distributed Processing Techniques and Applications(PDPTA)
- Place of Presentation
  Las Vegas, USA
- Year and Date
  2015-07-28
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-24300013
[Presentation] An FPGA Architecture for Text Search Using a Wavelet-Tree-Based Succinct-Data-Structure2015
- Author(s)
  Hasitha Muthumala Waidyasooriya, Daisuke Ono, Masanori Hariyama, Michitaka Kameyama
- Organizer
  International Conference on Parallel and Distributed Processing Techniques and Applications(PDPTA)
- Place of Presentation
  Las Vegas, USA
- Year and Date
  2015-07-28
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-24300013
[Presentation] Evaluation of an FPGA-Based Shortest-Path-Search Accelerator2015
- Author(s)
  Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama
- Organizer
  International Conference on Parallel and Distributed Processing Techniques and Applications(PDPTA)
- Place of Presentation
  Las Vegas, USA
- Year and Date
  2015-07-29
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-24300013
[Presentation] Hardware-Oriented Succinct-Data-Structure based on the Block-Size-Constrained Compression2015
- Author(s)
  Hasitha Waidyasooriya, Daisuke Ono and Masanori Hariyama
- Organizer
  Soft computing and Pattern Recognition(SoCPaR)
- Place of Presentation
  Fukuoka, Japan
- Year and Date
  2015-11-15
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-24300013
[Presentation] FPGA-Oriented Design of an FDTD Accelerator Based on Overlapped Tiling2015
- Author(s)
  Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
- Organizer
  International Conference on Parallel and Distributed Processing Techniques and Applications(PDPTA)
- Place of Presentation
  Las Vegas, USA
- Year and Date
  2015-07-29
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-24300013
[Presentation] FPGA-Accelerator for DNA Sequence Alignment Based on an Efficient Data-Dependent Memory Access Scheme2014
- Author(s)
  Hasitha Waidyasooriya, Masanori Hariyama and Michitaka Kameyama
- Organizer
  International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies(HEART)
- Place of Presentation
  Sendai, Japan
- Year and Date
  2014-06-10
- Data Source
  KAKENHI-PROJECT-24300013
[Presentation] 腫瘍視点から同定する門脈支配率を用いた肝臓切除領域の推定.2014
- Author(s)
  下田貢, 白木孝之, 張山昌論, 窪田敬一.
- Organizer
  第9回肝癌治療シミュレーション研究会
- Place of Presentation
  大阪
- Year and Date
  2014-09-27
- Data Source
  KAKENHI-PROJECT-24500242
[Presentation] 大規模計算応用のためのカスタムアクセラレータの展望　～応用・アーキテクチャ・回路～2014
- Author(s)
  張山昌論
- Organizer
  電子情報通信学会技術報告(信学技報)
- Place of Presentation
  仙台
- Year and Date
  2014-06-11
- Invited
- Data Source
  KAKENHI-PROJECT-24300013
[Presentation] 肝臓構造モデルに基づく高精度な肝臓領域自動抽出ソフトウェアの開発2014
- Author(s)
  482.張山昌論，白木孝之，前田圭佑，下田貢，窪田敬一
- Organizer
  第9回肝癌治療シミュレーション研究会
- Place of Presentation
  大阪
- Year and Date
  2014-09-27
- Data Source
  KAKENHI-PROJECT-24500242
[Presentation] 人間中心のリアル・ワールド知能システムのための計算技術2012
- Author(s)
  張山昌論
- Organizer
  電子情報通信学会技術報告(信学技報)
- Place of Presentation
  ホテルルイズ,岩手県盛岡市
- Year and Date
  2012-10-18
- Data Source
  KAKENHI-PROJECT-24300013
[Presentation] FPGA/GPUアクセラレータを有する高性能計算向けヘテロジニアスプラットフォームと2-DFDTDへの応用2012
- Author(s)
  張山昌論
- Organizer
  電子情報通信学会技術報告(信学技報)
- Place of Presentation
  立命館大学,滋賀県草津市
- Year and Date
  2012-09-19
- Data Source
  KAKENHI-PROJECT-24300013
[Presentation] An FPGA Based on Synchronous/Asynchroous Hybrid Architecture with Area-Efficient FIFO Interfaces2011
- Author(s)
  Masanori Hariyama, Yoshiya Komatsu, Shota Ishihara, Ryoto Tsuchiya, and Michitaka Kameyama
- Organizer
  Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms(ERSA)
- Place of Presentation
  Las Vegas(USA)
- Year and Date
  2011-07-19
- Data Source
  KAKENHI-PROJECT-21700052
[Presentation] An Implementation of an Asynchronous FPGA Based on LEDR/Four-Phase-Dual-Rail Hybrid Architecture2011
- Author(s)
  Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
- Organizer
  The Asia and South Pacific Design Automation Conference(ASP-DAC)
- Place of Presentation
  横浜
- Year and Date
  2011-01-26
- Data Source
  KAKENHI-PROJECT-21700052
[Presentation] An Field-Programmable VLSI Based on Synchronous/Asynchronous Hybrid Architecture2010
- Author(s)
  Masanori Hariyama, Ryoto Tsuchiya, Shota Ishihara, and Michitaka Kameyama
- Organizer
  Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms(ERSA)
- Place of Presentation
  Las Vegas(USA)
- Year and Date
  2010-07-13
- Data Source
  KAKENHI-PROJECT-21700052
[Presentation] A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic2009
- Author(s)
  Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama
- Organizer
  International Conference on Engineering of Reconfigurable Systems and Algorithms(ERSA)
- Place of Presentation
  Las Vegas(USA)
- Year and Date
  2009-07-14
- Data Source
  KAKENHI-PROJECT-21700052
[Presentation] An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters2009
- Author(s)
  Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
- Organizer
  Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms(ERSA)
- Place of Presentation
  Las Vegas(USA)
- Year and Date
  2009-07-14
- Data Source
  KAKENHI-PROJECT-21700052
[Presentation] Architecture of a Low-Power FPGA Based on Self-Adaptive Voltage Control2009
- Author(s)
  Shota Ishihara, Zhengfan Xia, Masanori Hariyama, and Michitaka Kameyama
- Organizer
  Proc. International SoC Design Conference(ISOCC)
- Place of Presentation
  Busan(Korea)
- Year and Date
  2009-11-22
- Data Source
  KAKENHI-PROJECT-21700052
[Presentation] 肝細胞癌手術にオンコロジカルな視点を考慮した自動肝切除領域抽出ソフトの使用経験
- Author(s)
  下田貢, 清水崇行, 白木孝之, 張山昌論†, 窪田敬一
- Organizer
  第26回日本肝胆膵外科学会
- Place of Presentation
  和歌山
- Year and Date
  2014-06-11 – 2014-06-13
- Data Source
  KAKENHI-PROJECT-24500242
[Presentation] educing Floating-Point Error Based on Residue-Preservation and Its Evaluation on an FPGA
- Author(s)
  Hasitha Muthumala Waidyasooriya, Hirokazu Takahashi, Yasuhiro Takei, Masanori Hariyama and Michitaka Kameyama
- Organizer
  Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)
- Place of Presentation
  Las Vegas, Nevada, USA
- Data Source
  KAKENHI-PROJECT-24300013
[Presentation] OpenCLを用いたFPGAベースFDTDアクセラレータの設計
- Author(s)
  武井康浩，ハシタムトゥマラウィシディスーリヤ，張山昌論，亀山充隆
- Organizer
  電子情報通信学会技術報告(信学技報) EST
- Place of Presentation
  東北大学，仙台，日本
- Data Source
  KAKENHI-PROJECT-24300013
[Presentation] 外科手術支援システム操作のための3次元ユーザーインタフェース(エアマウス)の開発
- Author(s)
  張山昌論
- Organizer
  第8回肝癌シミュレーション研究会
- Place of Presentation
  東京
- Data Source
  KAKENHI-PROJECT-24500242
[Presentation] Heterogeneous Multicore Platform with Accelerator Templates and Its Implementation on an FPGA with Hard-core CPUs
- Author(s)
  Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama and Michitaka Kameyama
- Organizer
  Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)
- Place of Presentation
  Las Vegas, Nevada, USA
- Data Source
  KAKENHI-PROJECT-24300013
[Presentation] 人にやさしい応用を拓く「計算」技術
- Author(s)
  張山昌論
- Organizer
  IEEE CASS Kansai Chapter 技術講演会
- Place of Presentation
  神戸大学，神戸，日本
- Invited
- Data Source
  KAKENHI-PROJECT-24300013
[Presentation] 腫瘍領域情報に基づく肝臓切除容量最小化ための門脈切除点計算"
- Author(s)
  岡田萌, 張山昌論,亀山充隆,下田貢
- Organizer
  計測自動制御学会東北支部
- Place of Presentation
  岩手
- Data Source
  KAKENHI-PROJECT-24500242
[Presentation] Liver Extraction from CT Images Based on Liver Structure Models. Int'l Conf. IP, Comp. Vision, and Pattern Recognition, 2014; 170-3.
- Author(s)
  Hariyama M, Tanizawa R, Shimoda M, Kubota K, Kobayashi Y
- Organizer
  IPCV'14
- Place of Presentation
  Las Vegas
- Year and Date
  2014-07-21 – 2014-07-24
- Data Source
  KAKENHI-PROJECT-24500242
[Presentation] Estimation of Resected Liver Regions Using a Tumor Domination Ratio.
- Author(s)
  2.Hariyama M, Okada M, Shimoda M, Kubota K:
- Organizer
  IPCV'14
- Place of Presentation
  Las Vegas
- Year and Date
  2014-07-21 – 2014-07-24
- Data Source
  KAKENHI-PROJECT-24500242
[Presentation] Implementation of a Custom Hardware-Accelerator for Short-read Mapping Using Burrows-Wheeler Alignment
- Author(s)
  Hasitha Muthumala Waidyasooriya, Masanori Hariyama and Michitaka Kameyama
- Organizer
  Proc. 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBS)
- Place of Presentation
  Osaka, Japan
- Data Source
  KAKENHI-PROJECT-24300013
[Presentation] 血管グラフ構造解析を用いた門脈自動追跡ソフトの開発とAiRScouter WD-を用いた術中ナビゲーションシステムの構築
- Author(s)
  下田貢、清水崇行、張山昌論、窪田敬一
- Organizer
  日本外科学会
- Place of Presentation
  福岡
- Data Source
  KAKENHI-PROJECT-24500242
[Presentation] An Area-Efficient Asynchronous FPGA Architecture for Handshake-Component-Based Design
- Author(s)
  Yoshiya KOMATSU, Masanori HARIYAMA and Michitaka KAMEYAMA
- Organizer
  Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)
- Place of Presentation
  Las Vegas, Nevada, USA
- Data Source
  KAKENHI-PROJECT-24300013

1. KAMEYAMA Michitaka (70124568)

# of Collaborated Projects: 5 results

# of Collaborated Products: 69 results
2. Waidyasooriya Hasitha Muthumala (60723533)

# of Collaborated Projects: 3 results

# of Collaborated Products: 16 results
3. HANYU Takahiro (40192702)

# of Collaborated Projects: 3 results

# of Collaborated Products: 0 results
4. SHIMODA Mitsugi (90332999)

# of Collaborated Projects: 2 results

# of Collaborated Products: 13 results
5. 久保田健夫 (70293511)

# of Collaborated Projects: 2 results

# of Collaborated Products: 2 results
6. 岸本聡子 (10511488)

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
7. 井上健一 (90587974)

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
8. 山口豊一 (10348154)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
9. 腰川一惠 (70406742)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
10. 望月和樹 (80423838)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
11. 鈴木由美 (30331383)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results

Hariyama Masanori 張山 昌論

HARIYAMA Masanori 張山 昌論

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High-efficiency Heterogeneous Custom Accelerator Foundation for TransformerPrincipal Investigator

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Custom Accelerators for Quantum-Annealing-Assisted Material InformaticsPrincipal Investigator

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Development of Highly-reliable and Low-power reconfigurable VLSI Based on Asynchronous architecture and Non-volatile memoryPrincipal Investigator

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Development of Heterogeneous-Computing Platform with Custom Accelerators for Embedded HPC ApplicationsPrincipal Investigator

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Low-Power FPGA Based on Fine-grained Autonomous Supply-Voltage ControlPrincipal Investigator

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リアルワールド知能システム用超高速ステレオビジョンVLSIプロセッサの開発Principal Investigator

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リアルワールド応用低消費電力リコンフィギャラブルVLSIプロセッサの開発Principal Investigator

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Hariyama Masanori 張山昌論

HARIYAMA Masanori 張山昌論