USAMI KIMIYOSHI 宇佐美公良

… Alternative Names

宇佐美公良ウサミキミヨシ

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Researcher Number	20365547
Other IDs
External Links
Affiliation (based on the past Project Information) *help	2022 – 2023: 芝浦工業大学, 工学部, 教授 2013 – 2020: 芝浦工業大学, 工学部, 教授 2004 – 2008: 芝浦工業大学, 工学部, 教授
Review Section/Research Field	Principal Investigator Basic Section 60040:Computer system-related / Computer system/Network Except Principal Investigator Computer system / Basic Section 60040:Computer system-related / Computer system/Network
Keywords	Principal Investigator FPGA / ハードウェア・セキュリティ / 製造ばらつき / ハードウェアセキュリティ / 低消費エネルギー / 超低電圧 / リーク電流 / PUF / Leakage power / Architecture … More / Low power / リーク電力 / アーキテクチャ / 低消費電力 … More Except Principal Investigator 計算機システム / コンピュータアーキテクチャ / System In Package技術 / ワイヤレスチップ間通信 / チップ積層 / チップ間ワイヤレス通信 / 三次元積層技術 / 不揮発メモリ / 低電力アーキテクチャ / ヘテロジーニアスマルチコアプロセッサ / チップ間誘導結合 / 計算機アーキテクチャ / 情報工学 / 性能、電力自動調整 / System In Package / 熱解析 / 電力制御 / チップ間ネットワーク / チップ間接続技術 / 命令時効制御 / 命令実行制御 / パワースイッチ / 動的リーク電力 / 低消費電力 Less

Realization of chip authentication circuit using a leak monitor and elucidation of resistance mechanism against machine learning attacksPrincipal Investigator
- Principal Investigator
  
  宇佐美公良
- Project Period (FY)
  2022 – 2024
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Shibaura Institute of Technology
Stacking methods with chip bridges for a building block computing system
- Principal Investigator
  
  AMANO HIDEHARU
- Project Period (FY)
  2018 – 2020
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Keio University
Non-Volatile Memory Computing
- Principal Investigator
  
  Nakamura Hiroshi
- Project Period (FY)
  2017 – 2019
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  Computer system
- Research Institution
  The University of Tokyo
A Study on Building-Block Computing Systems using Inductive Coupling Interconnect
- Principal Investigator
  
  Hideharu Amano
- Project Period (FY)
  2013 – 2017
- Research Category
  
  Grant-in-Aid for Scientific Research (S)
- Research Field
  
  Computer system
- Research Institution
  Keio University
Architecture and Circuit-Level Co-Design for Low-Power High-Performance Microprocessor
- Principal Investigator
  
  NAKAMURA Hiroshi
- Project Period (FY)
  2006 – 2008
- Research Category
  
  Grant-in-Aid for Scientific Research (A)
- Research Field
  
  Computer system/Network
- Research Institution
  The University of Tokyo
Research on Low Power Optimization for Computer ArchitecturePrincipal Investigator
- Principal Investigator
  
  USAMI Kimiyoshi
- Project Period (FY)
  2004 – 2006
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system/Network
- Research Institution
  Shibaura Institute of Technology

All 2023 2020 2019 2017 2016 2014 2013 2009 2008 2007 2006 2004

All Journal Article Presentation Book

[Book] Leakage in Nanometer CMOS Technologies2006
- Author(s)
  S.Narendra, A.Chandrakasan 編著 (K.Usami が 4章を執筆)
- Total Pages
  307
- Publisher
  Springer Science+Business Media, Inc.
- Data Source
  KAKENHI-PROJECT-16500041
[Journal Article] An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications2017
- Author(s)
  A.Koshiba, M.Sato, K.Usami, H.Amano, R.Sakamoto, M.Kondo, H.Nakamura, M.Namiki
- Journal Title
  
  IEICE Trans. on Electronics
  
  Volume: E99-C, No.8 Pages: 926-935
- NAID
  130005253989
- Peer Reviewed / Acknowledgement Compliant / Open Access
- Data Source
  KAKENHI-PROJECT-25220002
[Journal Article] Power Optimization Methodology for Ultra Low Power Microcontrolller with Silicon on Thin BOX MOSFET2017
- Author(s)
  H.Okuhara, Y.Fujita, K.Usami, H.Amano
- Journal Title
  
  IEEE Transaction on VLSI systems
  
  Volume: Vol.25, No.4 Issue: 4 Pages: 1578-1582
- DOI
  10.1109/tvlsi.2016.2635675
- Peer Reviewed / Acknowledgement Compliant
- Data Source
  KAKENHI-PROJECT-25220002
[Journal Article] Novel Chips Stacking Methods to Extend Both Horizontally and Vertically for Many-Core Architectures with ThrouChip Interface2016
- Author(s)
  H.Nakahara, T.Ozaki, H.Matsutani, K.Usami, H.Amano
- Journal Title
  
  IEICE Trans. on Information and Systems
  
  Volume: E99-D, No.12 Pages: 2871-2880
- NAID
  130005170939
- Peer Reviewed / Acknowledgement Compliant / Open Access
- Data Source
  KAKENHI-PROJECT-25220002
[Journal Article] 細粒度パワーゲーティングにおけるリークモニタの直接駆動によるスリープ制御2016
- Author(s)
  工藤優, 宇佐美公良
- Journal Title
  
  電子情報通信学会論文誌
  
  Volume: Vol.J99-A, No.8 Pages: 309-320
- Peer Reviewed / Acknowledgement Compliant / Open Access
- Data Source
  KAKENHI-PROJECT-25220002
[Journal Article] Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-Power Network-on-Chips Sytems2016
- Author(s)
  A.B.Armed, H.Matsutani, M.Koibichi, K.Usami, H.Amano
- Journal Title
  
  IEICE Trans. on Electronics
  
  Volume: E99-C, No.8 Pages: 909-917
- Peer Reviewed / Acknowledgement Compliant / Open Access
- Data Source
  KAKENHI-PROJECT-25220002
[Journal Article] A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface 3D NoC2013
- Author(s)
  N.Miura, Y.Koizumi, Y.Take, H.Matsutani, T.Kuroda, H.Amano, R.Sakamoto, M.Namiki, K.Usami, M.Kondo, H.Nakamura
- Journal Title
  
  IEEE Micro
  
  Volume: Vol.33, Issue 6 Issue: 1 Pages: 6-15
- DOI
  10.1109/mm.2013.12
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-25220002
[Journal Article] ランタイムパワーゲーティングをテ寄与した乗算器を用いた消費電力に影響する要因の解析2007
- Author(s)
  武田清大, 香嶋俊裕, 白井利明, 大久保直昭, 宇佐美公良
- Journal Title
  
  電子情報通信学会VLD/ICD研究会 VLD2006-154
  
  Pages: 81-85
- Data Source
  KAKENHI-PROJECT-18200002
[Journal Article] 細粒度動的スリープ制御による動作時リーク電力低減手法2006
- Author(s)
  大久保直昭, 宇佐美公良
- Journal Title
  
  情報処理学会DAシンポジウム2006論文集,IPSJ Symposium Series Vol.2006,No.7
  
  Pages: 199-204
- Data Source
  KAKENHI-PROJECT-18200002
[Journal Article] Delay Modeling and Critical-path Delay Calculation for MTCMOS Circuits, IEICE Transactions on Fundamentals of Electronics2006
- Author(s)
  N. Ohkubo and K. Usami
- Journal Title
  
  Communications and Computer Sciences Vol.E89-A, NO.12
  
  Pages: 3482-3490
- Data Source
  KAKENHI-PROJECT-18200002
[Journal Article] 走行時パワーゲーティングを適用した低消費電力乗算器の物理設計と試作2006
- Author(s)
  武田清大, 香嶋俊裕, 大久保直昭, 白井利明, 宇佐美公良
- Journal Title
  
  電子情報通信学会研究会デザインガイア VLD2006-74
  
  Pages: 13-18
- NAID
  110005717364
- Data Source
  KAKENHI-PROJECT-18200002
[Journal Article] 走行時パワーゲーティングを適用した低消費電力乗算器のアーキテクチャ設計2006
- Author(s)
  香嶋俊裕, 武田清大, 大久保直昭, 白井利明, 宇佐美公良
- Journal Title
  
  電子情報通信学会研究会デザインガイア VLD2006-73
  
  Pages: 7-12
- NAID
  110005717363
- Data Source
  KAKENHI-PROJECT-18200002
[Journal Article] Delay Modeling and Critical-path Delay Calculation for MTCMOS Circuits2006
- Author(s)
  N.Ohkubo, K.Usami
- Journal Title
  
  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A・12
  
  Pages: 3482-3490
- NAID
  110007537851
- Data Source
  KAKENHI-PROJECT-16500041
[Journal Article] Dynamic Sleep Control for Finite-State-Machines to Reduce Active Leakage Power2004
- Author(s)
  K.Usami, H.Yoshioka
- Journal Title
  
  IEICE Transaction of Fundamentals Vol.E87-A, No.12
  
  Pages: 3116-3123
- NAID
  110003212848
- Description
  「研究成果報告書概要(欧文)」より
- Data Source
  KAKENHI-PROJECT-16500041
[Journal Article] Dynamic Sleep Control for Finite-State-Machines to Reduce Active Leakage Power2004
- Author(s)
  K.Usami, H.Yoshioka
- Journal Title
  
  IEICE Transactions on Fundamentals Vol.E87-A, No.12
  
  Pages: 3116-3123
- NAID
  110003212848
- Data Source
  KAKENHI-PROJECT-16500041
[Journal Article] Dynamic Sleep Control for Finite-State-Machines to Reduce Active Leakage Power2004
- Author(s)
  K.Usami, H.Yoshioka
- Journal Title
  
  IEICE Transaction of Fundamentals Vol. E87-A, No. 12
  
  Pages: 3116-3123
- NAID
  110003212848
- Description
  「研究成果報告書概要(和文)」より
- Data Source
  KAKENHI-PROJECT-16500041
[Presentation] Design Optimization of Leakage Based PUF Circuit targeting at Ultra-Low Voltage Operation2023
- Author(s)
  Shunkichi Hata, Kimiyoshi Usami
- Organizer
  2023 International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC)
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-22K11959
[Presentation] リーク電流の製造ばらつきを利用したLRPUFの超低電圧に向けた回路の最適化とシミュレーション評価2023
- Author(s)
  畑俊吉, 宇佐美公良
- Organizer
  電子情報通信学会VLD研究会
- Data Source
  KAKENHI-PROJECT-22K11959
[Presentation] 3次元積層チップの発熱時における熱過渡解析と温度制御回路の設計2020
- Author(s)
  笈川智秋, 宇佐美公良
- Organizer
  電子情報通信学会VLD研究会, VLD2020-9, 2020.6.18.
- Data Source
  KAKENHI-PROJECT-18H03215
[Presentation] 3次元積層LSIの実チップ発熱・放熱時における温度の過渡解析と評価2019
- Author(s)
  堀米亮汰, 宇佐美公良
- Organizer
  電子情報通信学会VLSI設計技術研究会(VLD2018-107)
- Data Source
  KAKENHI-PROJECT-17H01708
[Presentation] 2電源を用いた不揮発性フリップフロップの提案と評価2019
- Author(s)
  秋葉爽輔、宇佐美公良
- Organizer
  電子情報通信学会VLD研究会
- Data Source
  KAKENHI-PROJECT-17H01708
[Presentation] Building Block multi-chip systems using inductive coupling through chip interface2017
- Author(s)
  H.Amano, T.Kuroda, H.Nakamura, K.Usami, M.Kondo, H.Matsutani, M.Namiki
- Organizer
  International SoC Design Conference
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25220002
[Presentation] Digital Embedded Memory Scheme using Voltage Scaling and Body Bias Separation for Low-Power System2017
- Author(s)
  Y.Yoshida, K.Usami, H.Amano
- Organizer
  International SoC Design Conference
- Invited / Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25220002
[Presentation] Level Shifter Free Approach for Multi-VDD SOTB employing Adaptive Vt Modulation for pMOSFET2017
- Author(s)
  K.Usami, K.Kogure, Y.Yoshida, R.Magasaki, H.Amano
- Organizer
  IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25220002
[Presentation] Unbalanced Buffer Tree Synthesis to Suppress Ground Bounce for Fine-Grain Power Gating2014
- Author(s)
  K.Usami
- Organizer
  International Symposium on System-on-Chip(SOC2014)
- Place of Presentation
  Tampere Finland
- Year and Date
  2014-10-28
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25220002
[Presentation] Design and Control Methodology for Fine Grain Power Gating based on Energy Characterization and Code Profiling of Microprocessors2014
- Author(s)
  Kimiyoshi Usami
- Organizer
  ASP-DAC 2014
- Place of Presentation
  Singapore
- Data Source
  KAKENHI-PROJECT-25220002
[Presentation] Design and Implementation of Fine-grain Power Gating with Ground Bounce Suppression2009
- Author(s)
  K.Usami, T.Shirai, T.Hashida, H.Masuda, S.Takeda, M.Nakata, N.Seki, H.Amano, M.Namiki, M.Imai, M.Kondo, and H.Nakamura
- Organizer
  22nd International Conference on VLSI Design (VLSI Conference'09)
- Place of Presentation
  (381-386)
- Data Source
  KAKENHI-PROJECT-18200002
[Presentation] 命令レベル並列アーキテクチャを有するCPUにおけるパワーゲーティングの有効性に関する研究2009
- Author(s)
  武藤徹也, 白井利明, 宇佐美公良
- Organizer
  電子情報通信学会2009 総合大会, D-6-4
- Data Source
  KAKENHI-PROJECT-18200002
[Presentation] スタティックタイミング解析を可能にするパワースイッチの時間的共有化手法2009
- Author(s)
  山本辰也, 抱山冴子, 白井利明, 宇佐美公良
- Organizer
  電子情報通信学会2009 総合大会, A-3-3
- Data Source
  KAKENHI-PROJECT-18200002
[Presentation] 低電圧パワーゲーティング回路の遅延ばらつき解析2009
- Author(s)
  白井利明, 宇佐美公良
- Organizer
  電子情報通信学会2009 総合大会, A-3-2
- Data Source
  KAKENHI-PROJECT-18200002
[Presentation] オンチップ・リークモニタの65nmプロセスでの実装設計と評価2009
- Author(s)
  小山慧, 宇佐美公良
- Organizer
  電子情報通信学会技術研究報告
- Place of Presentation
  (vol.108, no.478, VLD2008-163)(219-224)
- Data Source
  KAKENHI-PROJECT-18200002
[Presentation] 太L-パワースイッチが消費電力と遅延に及ぼす影響2009
- Author(s)
  増田大樹, 白井利明, 宇佐美公良
- Organizer
  電子情報通信学会2009 総合大会, A-3-1
- Data Source
  KAKENHI-PROJECT-18200002
[Presentation] ランタイムパワーゲーティングを適用した低電力乗算器の設計試作及び実測による性能評価2009
- Author(s)
  中田光貴, 白井利明, 武田清大, 宇佐美公良
- Organizer
  電子情報通信学会技術研究報告
- Place of Presentation
  (vol.108, no.478, VLD2008-162)(213-218)
- Data Source
  KAKENHI-PROJECT-18200002
[Presentation] ランタイムパワーゲーティングを適用したMIPS R3000 プロセッサの実装設計と評価2008
- Author(s)
  白井利明, 香嶋俊裕, 武田清大, 中田光貴, 宇佐美公良, 長谷川揚平, 関直臣, 天野英晴
- Organizer
  信学技報
- Place of Presentation
  (vol.107, no.414, VLD2007-112)(43-48)
- Data Source
  KAKENHI-PROJECT-18200002
[Presentation] パワーゲーティング手法によるCPUのレジスタファイルの消費電力低減化技術2008
- Author(s)
  大木亮, 高木一光, 宇佐美公良
- Organizer
  電子情報通信学会2008総合大会, A-3-11
- Data Source
  KAKENHI-PROJECT-18200002
[Presentation] Power-Switch Clustering Method for Static Timing Analysis2008
- Author(s)
  T.Hashida, K.Usami
- Organizer
  23rd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'08)
- Place of Presentation
  (217-220)
- Data Source
  KAKENHI-PROJECT-18200002
[Presentation] Hybrid Design of Dual Vth and Power Gating to Reduce Leakage Power under Vth Variations2008
- Author(s)
  T.Shirai and K.Usami
- Organizer
  International SoC Design Conference 2008(ISOCC'08)
- Place of Presentation
  (310-313)
- Data Source
  KAKENHI-PROJECT-18200002
[Presentation] スタティックタイミング解析を可能にするパワースイッチ共有化手法2008
- Author(s)
  橋田達徳, 宇佐美公良
- Organizer
  電子情報通信学会2008総合大会, A-3-10
- Data Source
  KAKENHI-PROJECT-18200002
[Presentation] MTCMOS回路を利用したオンチップ・リークモニタの設計と評価2008
- Author(s)
  小山慧, 武田清大, 宇佐美公良
- Organizer
  信学技報
- Place of Presentation
  (vol.107, no.507, VLD2007-146)(13-18)
- Data Source
  KAKENHI-PROJECT-18200002
[Presentation] 2電源電圧手法による動的リコンフィギャラブル・プロセッサの低消費電力化2008
- Author(s)
  馬橋雄祐, 神林侑希, 宇佐美公良, 加東勝, 長谷川揚平, 天野英晴
- Organizer
  電子情報通信学会2008総合大会, D-18-4
- Data Source
  KAKENHI-PROJECT-18200002
[Presentation] ランタイムパワーゲーティングを適用した回路での検証環境と電力見積もり手法の構築2008
- Author(s)
  中田光貴, 白井利明, 香嶋俊裕, 武田清大, 宇佐美公良, 関直臣, 長谷川揚平, 天野英晴
- Organizer
  信学技報
- Place of Presentation
  (vol.107, no.414, VLD2007-111)(37-42)
- Data Source
  KAKENHI-PROJECT-18200002
[Presentation] Design and Analysis of On-chip Leakage Monitor using an MTCMOS circuit2008
- Author(s)
  S.Koyama, S.Takeda, and K.Usami
- Organizer
  23rd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'08)
- Place of Presentation
  (205-208)
- Data Source
  KAKENHI-PROJECT-18200002
[Presentation] パワースイッチの実現方式が速度と消費電力に及ぼす影響の研究2008
- Author(s)
  会田真弘, 宇佐美公良
- Organizer
  電子情報通信学会2008総合大会, A-3-9
- Data Source
  KAKENHI-PROJECT-18200002
[Presentation] Power Reduction Technique for Dynamic Reconfigurable Processors with Dynamic Assignment of Dual Supply Voltages2008
- Author(s)
  Y.Umahashi, Y.Kambayashi, M.Kato, Y.Hasegawa, H.Amano, and K.Usami
- Organizer
  23rd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'08)
- Place of Presentation
  (213-216)
- Data Source
  KAKENHI-PROJECT-18200002
[Presentation] 走行時パワーゲーティングを適用した低消費電力乗算器の試作による電力評価2007
- Author(s)
  香嶋俊裕, 武田清大, 白井利明, 大久保直昭, 宇佐美公良
- Organizer
  信学技報
- Place of Presentation
  (vol.107, no.195, ICD2007-80)(63-68)
- Data Source
  KAKENHI-PROJECT-18200002
[Presentation] LSIの動的スリープ制御における高速復帰技術2007
- Author(s)
  白井利明, 宇佐美公良
- Organizer
  電子情報通信学会講演論文集
- Place of Presentation
  (Vol.2007年基礎・境界(20070307))(103)
- Data Source
  KAKENHI-PROJECT-18200002
[Presentation] パワースイッチを共有したMTCMOS回路の遅延時間解析手法2007
- Author(s)
  伊藤総一, 宇佐美公良
- Organizer
  電子情報通信学会講演論文集
- Place of Presentation
  (Vol.2007年基礎・境界(20070307))(98)
- Data Source
  KAKENHI-PROJECT-18200002
[Presentation] FPGAを利用した動的スリープ制御信号の動作解析2007
- Author(s)
  桐原啓介, 宇佐美公良
- Organizer
  電子情報通信学会講演論文集
- Place of Presentation
  (Vol.2007年基礎・境界(20070307))(104)
- Data Source
  KAKENHI-PROJECT-18200002
[Presentation] 2電源を用いたFPGAにおける消費電力低減化技術2007
- Author(s)
  秋元裕美, 野島俊孝, 宇佐美公良
- Organizer
  電子情報通信学会講演論文集
- Place of Presentation
  (Vol.2007年基礎・境界(20070307))(105)
- Data Source
  KAKENHI-PROJECT-18200002
[Presentation] ランタイムパワーゲーティングを適用した乗算器を用いた消費電力に影響する要因の解析2007
- Author(s)
  武田清大, 香嶋俊裕, 白井利明, 大久保直昭, 宇佐美公良
- Organizer
  電子情報通信学会VLD/ICD研究会
- Place of Presentation
  (VLD2006-154)(81-85)
- Data Source
  KAKENHI-PROJECT-18200002
[Presentation] Overview on Low Power SoC Design Technology2007
- Author(s)
  K.Usami
- Organizer
  IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC'07)
- Place of Presentation
  (invited paper)(634-636)
- Data Source
  KAKENHI-PROJECT-18200002
[Presentation] 細粒度動的スリープ制御による動作時リーク電力低減手法2006
- Author(s)
  大久保直昭, 宇佐美公良
- Organizer
  情報処理学会DAシンポジウム2006論文集, IPSJ Symposium Series
- Place of Presentation
  (Vol.2006, No.7)(199-204)
- Data Source
  KAKENHI-PROJECT-18200002
[Presentation] 走行時パワーゲーティングを適用した低消費電力乗算器のアーキテクチャ設計2006
- Author(s)
  香嶋俊裕, 武田清大, 大久保直昭, 白井利明, 宇佐美公良
- Organizer
  電子情報通信学会研究会デザインガイア
- Place of Presentation
  (VLD2006-73)(7-12)
- Data Source
  KAKENHI-PROJECT-18200002
[Presentation] A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals2006
- Author(s)
  K.Usami and N.Ohkubo
- Organizer
  IEEE International Conference on Computer Design (ICCD'06)
- Place of Presentation
  (155-161)
- Data Source
  KAKENHI-PROJECT-18200002
[Presentation] 走行時パワーゲーティングを適用した低消費電力乗算器の物理設計と試作2006
- Author(s)
  武田清大, 香嶋俊裕, 大久保直昭, 白井利明, 宇佐美公良
- Organizer
  電子情報通信学会研究会デザインガイア
- Place of Presentation
  (VLD2006-74)(13-18)
- Data Source
  KAKENHI-PROJECT-18200002

1. NAKAMURA Hiroshi (20212102)

# of Collaborated Projects: 5 results

# of Collaborated Products: 4 results
2. KONDO MASAAKI (30376660)

# of Collaborated Projects: 3 results

# of Collaborated Products: 4 results
3. 並木美太郎 (10208077)

# of Collaborated Projects: 3 results

# of Collaborated Products: 3 results
4. Hideharu Amano (60175932)

# of Collaborated Projects: 2 results

# of Collaborated Products: 8 results
5. 黒田忠広 (50327681)

# of Collaborated Projects: 2 results

# of Collaborated Products: 2 results
6. IMAI MASASHI (70323665)

# of Collaborated Projects: 1 results

# of Collaborated Products: 1 results
7. MATSUTANI Hiroki (70611135)

# of Collaborated Projects: 1 results

# of Collaborated Products: 4 results
8. 鯉渕道紘 (40413926)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results

USAMI KIMIYOSHI 宇佐美 公良

宇佐美 公良 ウサミ キミヨシ

Research Projects

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Co-Researchers

Realization of chip authentication circuit using a leak monitor and elucidation of resistance mechanism against machine learning attacksPrincipal Investigator

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Stacking methods with chip bridges for a building block computing system

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Non-Volatile Memory Computing

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A Study on Building-Block Computing Systems using Inductive Coupling Interconnect

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Architecture and Circuit-Level Co-Design for Low-Power High-Performance Microprocessor

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Research on Low Power Optimization for Computer ArchitecturePrincipal Investigator

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[Book] Leakage in Nanometer CMOS Technologies2006

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[Journal Article] An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications2017

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NAID

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[Journal Article] Power Optimization Methodology for Ultra Low Power Microcontrolller with Silicon on Thin BOX MOSFET2017

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[Journal Article] Novel Chips Stacking Methods to Extend Both Horizontally and Vertically for Many-Core Architectures with ThrouChip Interface2016

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NAID

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[Journal Article] 細粒度パワーゲーティングにおける リークモニタの直接駆動によるスリープ制御2016

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[Journal Article] Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-Power Network-on-Chips Sytems2016

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[Journal Article] A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface 3D NoC2013

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[Journal Article] ランタイムパワーゲーティングをテ寄与した乗算器を用いた消費電力に影響する要因の解析2007

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Journal Title

Data Source

[Journal Article] 細粒度動的スリープ制御による動作時リーク電力低減手法2006

Author(s)

USAMI KIMIYOSHI 宇佐美公良

宇佐美公良ウサミキミヨシ

[Journal Article] 細粒度パワーゲーティングにおけるリークモニタの直接駆動によるスリープ制御2016

[Presentation] 3次元積層チップの発熱時における熱過渡解析と温度制御回路の設計2020