メニュー
Search
Search Research Projects
Search Researchers
How to Use
Japanese
English
Back to previous page
Hiraishi Hiromi
平石 裕実
Connect your ORCID iD
*help
…
Alternative Names
HIRAISHI Hiromi 平石 裕実
平石 裕美 ヒライシ ヒロミ
Less
Researcher Number
40093299
Other IDs
External Links
Affiliation (Current)
2019: 京都産業大学, 情報理工学部, 教授
Affiliation (based on the past Project Information)
*help
2008: Kyoto Sangyo University, コンピュータ理工学部, 教授
2006 – 2007: 京都産業大学, 工学部, 教授
2001 – 2002: 京都産業大学, 先端科学技術研究所, 教授
2000: 京都産業大学, 工学部, 教授
1991 – 1998: 京都産業大学, 工学部, 教授
…
More
1989 – 1991: Faculty of Engineering, Kyoto Univ., Assoc. Professor, 工学部, 助教授
1989: 京都大学, 工学部, 助手
1989: 京都大学, 工学部・, 助教授
1987: Associate Professor, Faculty of Engineering, Kyoto Unversity, 工学部, 助教授
1986: Faculty of Engineering,Kyoto University, 工学部, 講師
Less
Review Section/Research Field
Principal Investigator
計算機科学
/
計算機工学
/
情報工学
/
Computer system/Network
Except Principal Investigator
計算機工学
/
情報工学
/
計算機科学
/
Informatics
Keywords
Principal Investigator
形式的検証 / 設計検証 / 時相論理 / 論理設計 / Temporal Logic / Formal Verification / 記号モデル検査 / Logic Design / 論理設計検証 / 並列アルゴリズム
…
More
/ BDD / Symbolic Model Checking / 共有二分決定グラフ / 順序機械 / 分散アルゴリズム / モデル検査 / Logic Design Verification / Distributed Algorithm / Parallel Processing / Design \verification / 有限状態システム / モジュール分割 / Distributed Processing / Model Checking / 計算機援用設計 / クラスタシステム / 耐故障設計 / 分散処理 / 二分決定グラフ / Formal Design Verification / セルフチェック / Cluster System / Finite State Systems / 記号シミュレ-ション / Design Verification / Computer Aided Design / 抽象化 / ベクトル計算機 / 並列処理 / セルフテスト / 様相論理 / Binary Decision Diagram / 形式的設計検証 / 正則集合 / 遷移関係 / 計算機援設計 / 仕様記述
…
More
Except Principal Investigator
論理設計検証 / 時相論理 / 二分決定グラフ / 論理関数処理 / Logic Simulation / Logic Design Verification / Hardware Algorithm / 論理シミュレ-ション / 論理シミュレーション / ハードウェアアルゴリズム / Temporal Logic / モデルチェッキング / 論理設計 / Symbolic Simulation / Logic Design / Binary Decision Diagram / 仕様記述 / 算術演算回路 / temporal logic / Timing Verification / 記号シミュレ-ション / タイミング検証 / 順序回路 / デ-タベ-ス / 論理関数簡単化 / 剰余数表示法 / 大容量主記憶 / 並行処理 / バックアップ / ハードウェア / 論理開数処理 / 算術演算回路検証 / ホットスポットデ-タ / Arithmetic Circuits / logic function manipulation / 論理シミュレータ / Formal Verification / Formal Specification / Function level design / 並列トランザクション / Computational complexity / binary decision diagram / Asynchronous Sequential Circuit / 計算機援用設計 / グラフィックス / ハ-ドウェアアルゴリズム / On-Line Error Detection / First-order Predicate logic / 第一階述語論理 / ハ-ドウェアバックアップ機構 / 非同期式順序回路 / データベース / 調理関数処理 / ハザ-ド / parallel transaction / Specification Desctiption / computer-aided logic design / concurrency / 二分モーメントグラフ / model checking / Arithmetic Operation / 論立設計検証 / 利用者インタフェース / Computational Geometry / 耐故障設計 / main memory database / ハ-ドウェアログ / マイクロプロセッサ / Boolean Function / 論理設計支援 / ハ-ドウェア並行処理制御 / 2ポ-トメモリ / Workstation / Logic Function Manipulation / マルチメディア / オブジェクト指向 / Test Generation / マルチスクリーン / 形式的検証 / 地理情報処理 / 意味モデル / 冗長符号化 / 並行処理制御 / Formal design verification / 故障シミュレ-ション / 視覚的言語 / ベクトルプロセッサ / backup / Vector Processof / 超LSI / プロトタイピング / Model Checking / 論理合成 / 高水準ハードウェア記述 / log / 計算幾何学 / sequential circuits / Hazard / Unification / ログ / 冗長表現 / 形式的論理設計検証 / state assignment / シミュレーション / Database / Semantic Model / logic design verification / 計算複雑さ / 機能レベル設計 / 形式的設計検証 / オンライン誤り検出 / Fault Simulation / Fault-Tolerant Design / computer Aided Design / logic function optimization / 回復処理 / Boolean Function Manipulation / 三分決定グラフ / Residue Number Representation / トランザクションマシン / テスト生成 / シミュレ-ション / 質問処理 / Multi-media / 正則時相論理 / 機能レベル検証 / recovery / 単一化操作 / hotspot / 代数的仕様記述 / ワークステーション / ホットスポット / Graphics / 故障シミュレーション / Query Processing / VLSI; Redundant Binary Representation / ハードウェア設計言語 / ハ-ドウェア / 状態割当て / Visual Language / database / 主記憶デ-タベ-ス / 冗長2進表現 / logic synthesis / Object-Oriented / Redundant Coding / 論理関数 / Redundant Representation
Less
Research Projects
(
18
results)
Research Products
(
4
results)
Co-Researchers
(
20
People)
Project Start Year (Newest)
Project Start Year (Oldest)
Parallel Logic Design Verification Based on Module Dependence
Principal Investigator
Principal Investigator
HIRAISHI Hiromi
Project Period (FY)
2006 – 2008
Research Category
Grant-in-Aid for Scientific Research (C)
Research Field
Computer system/Network
Research Institution
Kyoto Sangyo University
Parallel and Distributed Formal Logic Design Verification for Workstation Cluster System
Principal Investigator
Principal Investigator
HIRAISHI Hiromi
Project Period (FY)
2000 – 2002
Research Category
Grant-in-Aid for Scientific Research (C)
Research Field
計算機科学
Research Institution
Kyoto Sangyo University
Studies on Formal Logic Design Verification
Principal Investigator
Principal Investigator
HIRAISHI Hiromi
Project Period (FY)
1997 – 1998
Research Category
Grant-in-Aid for Scientific Research (C)
Research Field
計算機科学
Research Institution
Kyoto Sangyo University
大規模論理設計の形式的検証に関する研究
Principal Investigator
Principal Investigator
平石 裕実
Project Period (FY)
1996
Research Category
Grant-in-Aid for Scientific Research (C)
Research Field
計算機科学
Research Institution
Kyoto Sangyo University
時相理論を用いた形式的論理設計検証に関する研究
Principal Investigator
Principal Investigator
平石 裕実
Project Period (FY)
1995
Research Category
Grant-in-Aid for General Scientific Research (C)
Research Field
計算機科学
Research Institution
Kyoto Sangyo University
Research on Development of Formal Logic Design Verifier for Microprocessors
Principal Investigator
YAJIMA Shuzo
Project Period (FY)
1995 – 1996
Research Category
Grant-in-Aid for Scientific Research (A)
Research Field
計算機科学
Research Institution
KYOTO UNIVERSITY
Research on Formal Verifier of Logic Design Based on Temporal Logic
Principal Investigator
YAJIMA Shuzo
Project Period (FY)
1993 – 1994
Research Category
Grant-in-Aid for Developmental Scientific Research (B)
Research Field
計算機科学
Research Institution
KYOTO UNIVERSITY
Research on Formal Verification of Finite State Systems
Principal Investigator
Principal Investigator
HIRAISHI Hiromi
Project Period (FY)
1993 – 1994
Research Category
Grant-in-Aid for General Scientific Research (C)
Research Field
計算機科学
Research Institution
Kyoto Sangyo University
Research on Development of Logic Synthesizer and Design Verifier for Sequential Circuits Based on Boolean Function Manipulation
Principal Investigator
YAJIMA Shuzo
Project Period (FY)
1991 – 1992
Research Category
Grant-in-Aid for Developmental Scientific Research (B)
Research Field
情報工学
Research Institution
KYOTO UNIVERSITY
Research on Computer Aided Formal Verification Based on Temporal Logics
Principal Investigator
Principal Investigator
HIRAISHI Hiromi
Project Period (FY)
1991 – 1992
Research Category
Grant-in-Aid for General Scientific Research (C)
Research Field
情報工学
Research Institution
Kyoto Sangyo University
Research on Efficient Manipulation of Boolean Functions Using Shared Binary Decision Diagrams and Its Application to Computer Aided Logic Design
Principal Investigator
YAJIMA Shuzo
Project Period (FY)
1990 – 1991
Research Category
Grant-in-Aid for General Scientific Research (B)
Research Field
情報工学
Research Institution
Kyoto University
Researches on Formal Logic Design Verification Based on Regular Temporal Logic
Principal Investigator
Principal Investigator
HIRAISHI Hiromi
Project Period (FY)
1989 – 1990
Research Category
Grant-in-Aid for General Scientific Research (C)
Research Field
計算機工学
Research Institution
Kyoto University
Research on Development of a Logic Design Verification System Based on Time-Symbolic Simulation
Principal Investigator
YAJIMA Shuzo
Project Period (FY)
1989 – 1990
Research Category
Grant-in-Aid for Developmental Scientific Research (B).
Research Field
計算機工学
Research Institution
Kyoto University
Researches on the Design of Highly Reliable High-Speed Arithmetic Circuits with Redundant Coding
Principal Investigator
YAJIMA Shuzo
Project Period (FY)
1988 – 1989
Research Category
Grant-in-Aid for General Scientific Research (B)
Research Field
計算機工学
Research Institution
KYOTO UNIVERSITY
Studies on Development of Advanced Multi-Media Databases Based on Semantic Structures
Principal Investigator
KAMBAYASHI Yahiko
Project Period (FY)
1988 – 1990
Research Category
Grant-in-Aid for General Scientific Research (B)
Research Field
Informatics
Research Institution
Kyoto University
Kyushu University
Studies on High-Speed Transaction Machines Utilizing Hardware Concurrency Control Mechanisms
Principal Investigator
KAMBAYASHI Yahiko
Project Period (FY)
1988 – 1990
Research Category
Grant-in-Aid for Developmental Scientific Research (B).
Research Field
計算機工学
Research Institution
Kyoto University
Kyushu University
Research on Development of High-Speed Logic Simulators Using a Vector Processor and Logic Design Verification Systems
Principal Investigator
YAJIMA Shuzo
Project Period (FY)
1986 – 1987
Research Category
Grant-in-Aid for Developmental Scientific Research
Research Field
計算機工学
Research Institution
Kyoto University
Research on Design of VLSI Oriented Hardware Algorithms Using Redundant Representation
Principal Investigator
YAJIMA Shuzo
Project Period (FY)
1985 – 1986
Research Category
Grant-in-Aid for General Scientific Research (B)
Research Field
計算機工学
Research Institution
Kyoto University
All
2009
2008
2007
All
Presentation
[Presentation] 記号モデル検査器SMVにおけるBDDの変数順について
2009
Author(s)
平石 裕実
Organizer
DTC研究会
Place of Presentation
箱根千代田荘
Year and Date
2009-03-29
Data Source
KAKENHI-PROJECT-18500043
[Presentation] 記号モデル検査器SMVにおけるBDDの変数順について
2009
Author(s)
平石裕実
Organizer
DTC研究会
Place of Presentation
箱根千代田壮
Year and Date
2009-03-29
Data Source
KAKENHI-PROJECT-18500043
[Presentation] SATアルゴリズムを利用した記号モデル検査について
2008
Author(s)
平石裕実
Organizer
DTC研究会
Place of Presentation
京都ガーデンパレス
Year and Date
2008-03-02
Data Source
KAKENHI-PROJECT-18500043
[Presentation] 記号モデル検査のスケールアップについて
2007
Author(s)
平石裕実
Organizer
DTC研究会
Place of Presentation
別府豊泉荘
Year and Date
2007-03-03
Data Source
KAKENHI-PROJECT-18500043
# of Projects (Dsc)
# of Projects (Asc)
1.
OGINO Hiroyuki
(40144323)
# of Collaborated Projects:
9 results
# of Collaborated Products:
0 results
2.
TAKAGI Naofumi
(10171422)
# of Collaborated Projects:
8 results
# of Collaborated Products:
0 results
3.
YAJIMA Shuzo
(20025901)
# of Collaborated Projects:
8 results
# of Collaborated Products:
0 results
4.
ISHIURA Nagisa
(60193265)
# of Collaborated Projects:
6 results
# of Collaborated Products:
0 results
5.
TAKENAGA Yasuhiko
(20236491)
# of Collaborated Projects:
4 results
# of Collaborated Products:
0 results
6.
IWAMA Kazuo
(50131272)
# of Collaborated Projects:
3 results
# of Collaborated Products:
0 results
7.
HAMAGUCHI Kiyoharu
(80238055)
# of Collaborated Projects:
3 results
# of Collaborated Products:
0 results
8.
KAWAKUBO Kazuo
(10186067)
# of Collaborated Projects:
2 results
# of Collaborated Products:
0 results
9.
YASUURA Hiroto
(80135540)
# of Collaborated Projects:
2 results
# of Collaborated Products:
0 results
10.
KAMBAYASHI Yahiko
(00026311)
# of Collaborated Projects:
2 results
# of Collaborated Products:
0 results
11.
ARIKAWA Masatoshi
(30202758)
# of Collaborated Projects:
2 results
# of Collaborated Products:
0 results
12.
WATANABE Masako
(70127158)
# of Collaborated Projects:
2 results
# of Collaborated Products:
0 results
13.
MINO Michihiko
(70166099)
# of Collaborated Projects:
2 results
# of Collaborated Products:
0 results
14.
SAISHO Keizo
(50170486)
# of Collaborated Projects:
2 results
# of Collaborated Products:
0 results
15.
古川 哲也
(00209165)
# of Collaborated Projects:
2 results
# of Collaborated Products:
0 results
16.
今井 浩
(80183010)
# of Collaborated Projects:
2 results
# of Collaborated Products:
0 results
17.
掛下 哲郎
(10214272)
# of Collaborated Projects:
1 results
# of Collaborated Products:
0 results
18.
吉川 正俊
(30182736)
# of Collaborated Projects:
1 results
# of Collaborated Products:
0 results
19.
中村 千秋
(00217861)
# of Collaborated Projects:
1 results
# of Collaborated Products:
0 results
20.
田中 克己
(00127375)
# of Collaborated Projects:
1 results
# of Collaborated Products:
0 results
×
Are you sure that you want to connect your ORCID iD to this researcher?
×
