ISHIURA Nagisa 石浦菜岐佐

… Alternative Names

Researcher Number	60193265
External Links
Affiliation (Current)	2021: 関西学院大学, 工学部, 教授
Affiliation (based on the past Project Information) *help	2013 – 2020: 関西学院大学, 理工学部, 教授 2008 – 2010: Kwansei Gakuin University, 理工学部, 教授 2002 – 2004: Kwansei Gakuin University School of Science and Technology, 理工学部, 教授 1998 – 2001: Osaka University, Department of Information Systems Engineering Associate Professor, 大学院・工学研究科, 助教授 1994 – 1997: 大阪大学, 工学部, 助教授 1991 – 1992: Osaka University, Faculty of Engineering, Lecturer, 工学部, 講師 1987 – 1990: Research Associate, Faculty of Engineering, Kyoto University, 工学部, 助手
Review Section/Research Field	Principal Investigator 計算機科学 / Computer system/Network / Computer system / Basic Section 60040:Computer system-related Except Principal Investigator 計算機工学 / 情報工学 / 情報通信工学 / System engineering
Keywords	Principal Investigator DSP / 高位合成 / 二分決定グラフ / 論理関数 / 組み込みシステム / リターゲッタブルコンパイラ / 組込みプロセッサ / マルチコア / 組込みシステム / ディジタル信号処理 … More Except Principal Investigator VLSI / 論理設計検証 / Logic Design Verification / 時相論理 / 記号シミュレ-ション / Temporal Logic / 論理シミュレ-ション / Logic Simulation / VLSI implementation / MPEG-4 / 形式的検証 / 論理設計 / 仕様記述 / Formal Verification / Logic Design / タイミング検証 / Timing Verification / Symbolic Simulation / 二分決定グラフ / 計算機援用設計 / Binary Decision Diagram / CAD / 故障シミュレ-ション / MPEG2 / MPEG / 低消費電力 / low power / retargetable compiler / 論理シミュレーション / モデル検査 / 設計検証 / 正則集合 / 順序機械 / 共有二分決定グラフ / Model Checking / 非同期式順序回路 / ハザ-ド / 論立設計検証 / Asynchronous Sequential Circuit / Hazard / 論理関数 / 論理関数処理 / 計算複雑さ / Boolean Function / Boolean Function Manipulation / computer Aided Design / Computational complexity / 並列処理 / 回路シミュレ-ション / 自動配線 / VLSI自動配線 / Computer-Aided Design / Parallel Processing / Circuit Simulation / Logic simulation / Fault / Simulation / Routing / 計算機援設計 / ベクトル計算機 / Computer Aided Design / 高位合成 / 多重スレッド / プロセッサ / 画像生成 / 高速合成 / マルチスレッド / ASIC / high-level synthesis / multithreaded architecture / processor / ディジタル信号処理 / VLSI化設計 / FIRフィルタ / ディジタル記号処理 / digital signal processing / FIR filter / リターゲッタブル・コンパイラ / DSP / リターゲッタブルコンパイラ / MPEG4 / コンパイラ / 離散ウェーブレット変換 / 4相NMOS / ウエーブレット変換 / 画像圧縮 / JPEG2000 / discrete wavelet transform / ベクトルプロセッサ / ワークステーション / マルチスクリーン / 論理シミュレータ / 高水準ハードウェア記述 / 正則時相論理 / 代数的仕様記述 / Vector Processof / Specification Desctiption / Workstation / 算術演算回路 / ハ-ドウェアアルゴリズム / 耐故障設計 / オンライン誤り検出 / テスト生成 / 冗長符号化 / ハードウェアアルゴリズム / 故障シミュレーション / Arithmetic Circuits / Hardware Algorithm / Fault-Tolerant Design / On-Line Error Detection / Fault Simulation / Test Generation / Redundant Coding Less

Synthesis of Full Hardware Implementation of RTOS-Based SystemsPrincipal InvestigatorOngoing
- Principal Investigator
  
  石浦菜岐佐
- Project Period (FY)
  2019 – 2021
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Review Section
  
  Basic Section 60040:Computer system-related
- Research Institution
  Kwansei Gakuin University
Interrupt handling and dynamic scheduling for binary synthesisPrincipal Investigator
- Principal Investigator
  
  Ishiura Nagisa
- Project Period (FY)
  2016 – 2018
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system
- Research Institution
  Kwansei Gakuin University
Random testing of compilers based on precise computation of expected values and symbolic execution of generated codesPrincipal Investigator
- Principal Investigator
  
  Nagisa ISHIURA
- Project Period (FY)
  2013 – 2016
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system
- Research Institution
  Kwansei Gakuin University
High-Level Synthesis System Autogenerating Software Compatible HardwarePrincipal Investigator
- Principal Investigator
  
  ISHIURA Nagisa
- Project Period (FY)
  2008 – 2010
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system/Network
- Research Institution
  Kwansei Gakuin University
Research on retargetable code generation for custom VLIW DSPsPrincipal Investigator
- Principal Investigator
  
  ISHIURA Nagisa
- Project Period (FY)
  2003 – 2004
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  Computer system/Network
- Research Institution
  Kwansei Gakuin University
Codesign Methodology of Application Specific DSPs Based on a Retargetable CompilerPrincipal Investigator
- Principal Investigator
  
  ISHIURA Nagisa
- Project Period (FY)
  2001 – 2002
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  計算機科学
- Research Institution
  Kwansei Gakuin University
  Osaka University
VLSI Architecture for Video Codec Based on Discrete Wavelet Transform
- Principal Investigator
  
  SHIRAKAWA Isao
- Project Period (FY)
  2000 – 2001
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  情報通信工学
- Research Institution
  Osaka University
Research on Code Generation Algorithms for Retargetable Compilers for DSPsPrincipal Investigator
- Principal Investigator
  
  ISHIURA Nagisa
- Project Period (FY)
  1999 – 2000
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  計算機科学
- Research Institution
  Osaka University
VLSI architecture for MPEG-4 Audio Visual Codec
- Principal Investigator
  
  SHIRAKAWA Isao
- Project Period (FY)
  1998 – 1999
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  情報通信工学
- Research Institution
  Osaka University
Research on Control Dominant High-Level SynthesisPrincipal Investigator
- Principal Investigator
  
  ISHIURA Nagisa
- Project Period (FY)
  1997 – 1998
- Research Category
  
  Grant-in-Aid for Scientific Research (C)
- Research Field
  
  計算機科学
- Research Institution
  Osaka University
条件分岐と繰り返し構造を含む動作記述からの高位合成手法に関する研究Principal Investigator
- Principal Investigator
  
  石浦菜岐佐
- Project Period (FY)
  1996
- Research Category
  
  Grant-in-Aid for Encouragement of Young Scientists (A)
- Research Field
  
  計算機科学
- Research Institution
  Osaka University
VLSI Implementation for Digital Video Transmission and Compression
- Principal Investigator
  
  SHIRAKAWA Isao
- Project Period (FY)
  1996 – 1997
- Research Category
  
  Grant-in-Aid for Scientific Research (B)
- Research Field
  
  情報通信工学
- Research Institution
  Osaka University
論理関数処理による記号シミュレーションと無解釈評価に基づくプロセッサの形式的検証Principal Investigator
- Principal Investigator
  
  石浦菜岐佐
- Project Period (FY)
  1995
- Research Category
  
  Grant-in-Aid for Encouragement of Young Scientists (A)
- Research Field
  
  計算機科学
- Research Institution
  Osaka University
二分決定グラフに基づく組合せ論理回路の合成法に関する研究Principal Investigator
- Principal Investigator
  
  石浦菜岐佐
- Project Period (FY)
  1994
- Research Category
  
  Grant-in-Aid for Encouragement of Young Scientists (A)
- Research Field
  
  計算機科学
- Research Institution
  Osaka University
VLSI Implementation of New Architectures Using High-Level Synthesis System-Design of Multithreaded Processor
- Principal Investigator
  
  SHIRAKAWA Isao
- Project Period (FY)
  1994 – 1995
- Research Category
  
  Grant-in-Aid for General Scientific Research (B)
- Research Field
  
  System engineering
- Research Institution
  Osaka University
Research on Computer Aided Formal Verification Based on Temporal Logics
- Principal Investigator
  
  HIRAISHI Hiromi
- Project Period (FY)
  1991 – 1992
- Research Category
  
  Grant-in-Aid for General Scientific Research (C)
- Research Field
  
  情報工学
- Research Institution
  Kyoto Sangyo University
Research on Efficient Manipulation of Boolean Functions Using Shared Binary Decision Diagrams and Its Application to Computer Aided Logic Design
- Principal Investigator
  
  YAJIMA Shuzo
- Project Period (FY)
  1990 – 1991
- Research Category
  
  Grant-in-Aid for General Scientific Research (B)
- Research Field
  
  情報工学
- Research Institution
  Kyoto University
Research on Parallel Processing Techniques for Computer-Aided Design of VLSIs
- Principal Investigator
  
  SHIAKAWA Isao
- Project Period (FY)
  1990 – 1991
- Research Category
  
  Grant-in-Aid for Developmental Scientific Research (B)
- Research Field
  
  情報工学
- Research Institution
  Osaka University
Researches on Formal Logic Design Verification Based on Regular Temporal Logic
- Principal Investigator
  
  HIRAISHI Hiromi
- Project Period (FY)
  1989 – 1990
- Research Category
  
  Grant-in-Aid for General Scientific Research (C)
- Research Field
  
  計算機工学
- Research Institution
  Kyoto University
Research on Development of a Logic Design Verification System Based on Time-Symbolic Simulation
- Principal Investigator
  
  YAJIMA Shuzo
- Project Period (FY)
  1989 – 1990
- Research Category
  
  Grant-in-Aid for Developmental Scientific Research (B).
- Research Field
  
  計算機工学
- Research Institution
  Kyoto University
Researches on the Design of Highly Reliable High-Speed Arithmetic Circuits with Redundant Coding
- Principal Investigator
  
  YAJIMA Shuzo
- Project Period (FY)
  1988 – 1989
- Research Category
  
  Grant-in-Aid for General Scientific Research (B)
- Research Field
  
  計算機工学
- Research Institution
  KYOTO UNIVERSITY
Research on Development of High-Speed Logic Simulators Using a Vector Processor and Logic Design Verification Systems
- Principal Investigator
  
  YAJIMA Shuzo
- Project Period (FY)
  1986 – 1987
- Research Category
  
  Grant-in-Aid for Developmental Scientific Research
- Research Field
  
  計算機工学
- Research Institution
  Kyoto University

All 2019 2018 2017 2016 2015 2014 2011 2010 2009 2008 Other

All Journal Article Presentation Patent

[Journal Article] Synthesis of Full Hardware Implementation of RTOS-Based Systems2018
- Author(s)
  Y. Oosako, N. Ishiura, H. Tomiyama, and H. Kanbara
- Journal Title
  
  Proc. International Symposium on Rapid System Prototyping (RSP 2018)
  
  Volume: - Pages: 1-7
- DOI
  10.1109/rsp.2018.8631993
- NAID
  40021841150
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-16K00088
[Journal Article] Extended Distributed Control for Dynamic Scheduling across Dataflow Graphs2018
- Author(s)
  W. Nakano and N. Ishiura
- Journal Title
  
  Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies 2018
  
  Volume: 1 Pages: 35-36
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-16K00088
[Journal Article] High-Level Synthesis of Side Channel Attack Resistant RSA Decryption Circuit2018
- Author(s)
  N. Osako, S. OTA, S. Yura, and N. Ishiura
- Journal Title
  
  Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies 2018
  
  Volume: 1 Pages: 159-160
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-16K00088
[Journal Article] CF3: Test Suite for Arithmetic Optimization of C Compilers (letter)2017
- Author(s)
  Y. Hibino, H. Ikeo, and N. Ishiura
- Journal Title
  
  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (July, 2017, to appear)
  
  Volume: E100-A
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-25330073
[Journal Article] Speculative Execution in Distributed Controllers for High-Level Synthesis2017
- Author(s)
  M. Shimizu, N. Ishiura, S. Ota, and W. Nakano
- Journal Title
  
  Proc. International Symposium on Rapid System Prototyping 2017
  
  Volume: 1 Pages: 99-105
- DOI
  10.1145/3130265.3130319
- NAID
  170000173423
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-16K00088
[Journal Article] Distributed Memory Architecture for High-Level Synthesis of Embedded Controllers from Erlang2017
- Author(s)
  K. Azuma, N. Ishiura, N. Yoshida, and H. Kanbara
- Journal Title
  
  Proc. ACM SIGPLAN International Workshop on Erlang 2017
  
  Volume: 1 Pages: 13-19
- DOI
  10.1145/3123569.3123574
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-16K00088
[Journal Article] Binary Synthesis Implementing External Interrupt Handler as Independent Module2017
- Author(s)
  N. Ito, Y. Oosako, N. Ishiura, H. Tomiyama, and H. Kanbara
- Journal Title
  
  Proc. International Symposium on Rapid System Prototyping 2017
  
  Volume: 1 Pages: 92-98
- DOI
  10.1145/3130265.3130317
- NAID
  40020736742
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-16K00088
[Journal Article] Detecting Arithmetic Optimization Opportunities for C Compilers by Randomly Generated Equivalent Programs2016
- Author(s)
  A. Hashimoto and N. Ishiura
- Journal Title
  
  IPSJ Transactions on System LSI Design Methodology
  
  Volume: 7 Issue: 0 Pages: 21-29
- DOI
  10.2197/ipsjtsldm.9.21
- NAID
  130005126056
- ISSN
  1882-6687
- Language
  English
- Peer Reviewed / Acknowledgement Compliant / Open Access
- Data Source
  KAKENHI-PROJECT-25330073
[Journal Article] Reinforcing Random Testing of Arithmetic Optimization of C Compilers by Scaling up Size and Number of Expressions2014
- Author(s)
  E. Nagai, A. Hashimoto, and N. Ishiura
- Journal Title
  
  IPSJ Transactions on System LSI Design Methodology
  
  Volume: 7 Issue: 0 Pages: 91-100
- DOI
  10.2197/ipsjtsldm.7.91
- NAID
  130004679062
- ISSN
  1882-6687
- Language
  English
- Peer Reviewed / Open Access
- Data Source
  KAKENHI-PROJECT-25330073
[Journal Article] Stat ic Scheduling of Dynamic Execution for High-Level Synthesis2009
- Author(s)
  Y.Toda, N.Ishiura, K.Sone
- Journal Title
  
  Proc.the Workshop on Synthesis and System Integration of Mixed Inf ormation Technologies 2
  
  Pages: 107-11
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20500058
[Journal Article] High-Level Synthesis of Software Function Calls2008
- Author(s)
  M.Nishimura, N.Ishiura, Y.Ishimori, H.Kanbara, H.Tomiyama
- Journal Title
  
  IEICE Trans.Fundamentals No.E91-A
  
  Pages: 3556-3558
- NAID
  10026853994
- Peer Reviewed
- Data Source
  KAKENHI-PROJECT-20500058
[Patent] リアルタイム処理装置及びその作製方法2018
- Inventor(s)
  石浦菜岐佐, 大迫裕樹
- Industrial Property Rights Holder
  学校法人関西学院
- Industrial Property Rights Type
  特許
- Industrial Property Number
  2018-029244
- Filing Date
  2018
- Data Source
  KAKENHI-PROJECT-16K00088
[Presentation] RTOS を用いたシステムのフルハードウェア実装とその自動化2019
- Author(s)
  大迫裕樹, 石浦菜岐佐, 冨山宏之, 神原弘之
- Organizer
  電子情報通信学会VLSI設計技術研究会
- Data Source
  KAKENHI-PROJECT-16K00088
[Presentation] 複数データフローグラフにまたがる動的スケジューリングを実現する分散制御回路の自動合成2019
- Author(s)
  太田小百合, 石浦菜岐佐
- Organizer
  電子情報通信学会VLSI設計技術研究会
- Data Source
  KAKENHI-PROJECT-16K00088
[Presentation] Erlangからの高位合成のためのメモリ分散アーキテクチャ2018
- Author(s)
  東香実, 浜名将輝, 若林秀和, 石浦菜岐佐, 吉田信明, 神原弘之
- Organizer
  電子情報通信学会VLSI設計技術研究会
- Data Source
  KAKENHI-PROJECT-16K00088
[Presentation] 分散制御による動的スケジューリングの適用範囲の拡大2017
- Author(s)
  中野和香子, 石浦菜岐佐
- Organizer
  電子情報通信学会ソサイエティ大会
- Data Source
  KAKENHI-PROJECT-16K00088
[Presentation] モンゴメリ法及び並列化を適用した耐サイドチャネル攻撃RSA復号回路の高位合成2017
- Author(s)
  大窄直樹, 石浦菜岐佐
- Organizer
  電子情報通信学会ソサイエティ大会
- Data Source
  KAKENHI-PROJECT-16K00088
[Presentation] Erlang からの高位合成のための関数レベル並列化2017
- Author(s)
  若林秀和, 石浦菜岐佐, 吉田信明, 神原弘之
- Organizer
  電子情報通信学会ソサイエティ大会
- Data Source
  KAKENHI-PROJECT-16K00088
[Presentation] Erlang からの高位合成のためのライブラリモジュールの回路規模削減2017
- Author(s)
  浜名将輝, 石浦菜岐佐, 吉田信明, 神原弘之
- Organizer
  電子情報通信学会ソサイエティ大会
- Data Source
  KAKENHI-PROJECT-16K00088
[Presentation] RTOS を用いたシステムの高位合成によるフルハードウェア化2017
- Author(s)
  大迫裕樹, 石浦菜岐佐, 神原弘之, 冨山宏之
- Organizer
  組込みシステム技術に関するサマーワークショップ (SWEST)
- Data Source
  KAKENHI-PROJECT-16K00088
[Presentation] 割り込み駆動のモータ制御プログラムからの高位合成2016
- Author(s)
  大迫裕樹, 神原弘之, 石浦菜岐佐
- Organizer
  情報処理学会関西支部大会
- Place of Presentation
  大阪大学中之島センター (大阪府大阪市)
- Year and Date
  2016-09-26
- Data Source
  KAKENHI-PROJECT-16K00088
[Presentation] Introducing Real Constraints in Partitioned ILP-Based Biding in High-Level Synthesis (short paper)2016
- Author(s)
  N. Ishiura and Y. Oosako
- Organizer
  Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2016)
- Place of Presentation
  京都リサーチパーク (京都府京都市)
- Year and Date
  2016-10-25
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16K00088
[Presentation] 等価変換に基づくCコンパイラのランダムテストにおける変数の複数回参照の導入2016
- Author(s)
  高倉正悟, 石浦菜岐佐
- Organizer
  電子情報通信学会ソサイエティ大会
- Place of Presentation
  北海道大学 (北海道札幌市)
- Year and Date
  2016-09-21
- Data Source
  KAKENHI-PROJECT-25330073
[Presentation] Random Testing of C Compilers Based on Test Program Generation by Equivalence Transformation2016
- Author(s)
  K. Nakamura and N. Ishiura
- Organizer
  Asia and Pacific Conference on Circuits and Systems (APCCAS 2016)
- Place of Presentation
  Ramada Plaza Hotel (大韓民国済州市)
- Year and Date
  2016-10-27
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25330073
[Presentation] 不定サイクル演算に対応した分散制御における投機的実行2016
- Author(s)
  清水美帆, 石浦菜岐佐
- Organizer
  情報処理学会 DAシンポジウム 2016
- Place of Presentation
  ゆのくに天祥 (石川県加賀市)
- Year and Date
  2016-09-14
- Data Source
  KAKENHI-PROJECT-16K00088
[Presentation] コンパイラのランダムテストシステムOrange3の拡張によるJava処理系のテスト2016
- Author(s)
  清水遼太朗, 池尾弘史, 石浦菜岐佐
- Organizer
  電子情報通信学会ソサイエティ大会
- Place of Presentation
  北海道大学 (北海道札幌市)
- Year and Date
  2016-09-21
- Data Source
  KAKENHI-PROJECT-25330073
[Presentation] Erlang による組込みシステムの制御記述とその高位合成2016
- Author(s)
  東香実, 石浦菜岐佐, 竹林陽, 吉田信明, 神原弘之
- Organizer
  組込みシステム技術に関するサマーワークショップ (SWEST)
- Place of Presentation
  水明館 (岐阜県下呂市)
- Year and Date
  2016-08-25
- Data Source
  KAKENHI-PROJECT-16K00088
[Presentation] Extending Distributed Control for High-Level Synthesis beyond Borders of Dataflow Graphs2016
- Author(s)
  M. Shimizu and N. Ishiura
- Organizer
  Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2016)
- Place of Presentation
  京都リサーチパーク (京都府京都市)
- Year and Date
  2016-10-25
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16K00088
[Presentation] 電力解析攻撃/故障利用攻撃耐性RSA 復号回路の高位合成2016
- Author(s)
  太田小百合, 由良駿, 石浦菜岐佐
- Organizer
  電子情報通信学会ソサイエティ大会
- Place of Presentation
  北海道大学 (北海道札幌市)
- Year and Date
  2016-09-20
- Data Source
  KAKENHI-PROJECT-16K00088
[Presentation] 高位合成のバインディングの整数線形計画法による分割解法における実数制約の導入2016
- Author(s)
  大迫裕樹, 石浦菜岐佐
- Organizer
  電子情報通信学会ソサイエティ大会
- Place of Presentation
  北海道大学 (北海道札幌市)
- Year and Date
  2016-09-20
- Data Source
  KAKENHI-PROJECT-16K00088
[Presentation] Random Testing Back-end of Compiler Infrastructure LLVM (short paper)2016
- Author(s)
  K. Tanaka, N. Ishiura, M. Nishimura, and A. Fukui
- Organizer
  Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2016)
- Place of Presentation
  京都リサーチパーク (京都府京都市)
- Year and Date
  2016-10-24
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25330073
[Presentation] 等価変換に基づくテストプログラム生成を用いたCコンパイラのランダムテスト2016
- Author(s)
  中村和博, 石浦菜岐佐
- Organizer
  電子情報通信学会VLSI設計技術研究会
- Place of Presentation
  沖縄県青年会館 (沖縄県・那覇市)
- Year and Date
  2016-02-29
- Data Source
  KAKENHI-PROJECT-25330073
[Presentation] High-Level Synthesis of Embedded Systems Controller from Erlang2016
- Author(s)
  H. Takebayashi, N. Ishiura, K. Azuma, N. Yoshida, and H. Kanbara
- Organizer
  Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2016)
- Place of Presentation
  京都リサーチパーク (京都府京都市)
- Year and Date
  2016-10-25
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-16K00088
[Presentation] コンパイラ基盤 LLVM バックエンドのランダムテスト2016
- Author(s)
  田中健司, 石浦菜岐佐, 西村啓成, 福井昭也
- Organizer
  電子情報通信学会総合大会
- Place of Presentation
  九州大学 (福岡県・福岡市)
- Year and Date
  2016-03-17
- Data Source
  KAKENHI-PROJECT-25330073
[Presentation] Cコンパイラの最適化のリグレッションテストのためのアセンブリコード比較法2016
- Author(s)
  北浦幸太, 岩辻光功, 石浦菜岐佐
- Organizer
  電子情報通信学会ソサイエティ大会
- Place of Presentation
  北海道大学 (北海道札幌市)
- Year and Date
  2016-09-21
- Data Source
  KAKENHI-PROJECT-25330073
[Presentation] Detecting Missed Arithmetic Optimization in C Compilers by Differential Random Testing (short paper)2016
- Author(s)
  M. Iwatsuji, A. Hashimoto, and N. Ishiura
- Organizer
  Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2016)
- Place of Presentation
  京都リサーチパーク (京都府京都市)
- Year and Date
  2016-10-24
- Int'l Joint Research
- Data Source
  KAKENHI-PROJECT-25330073
[Presentation] C コンパイラ用テストスイート CF3 の検出能力向上2015
- Author(s)
  池尾弘史, 石浦菜岐佐
- Organizer
  電子情報通信学会ソサイエティ大会
- Place of Presentation
  東北大学 (宮城県・仙台市)
- Year and Date
  2015-09-10
- Data Source
  KAKENHI-PROJECT-25330073
[Presentation] Cコンパイラの算術最適化を対象としたテストスイートCF32015
- Author(s)
  日比野佑亮, 石浦菜岐佐
- Organizer
  電子情報通信学会VLSI設計技術研究会
- Place of Presentation
  慶應義塾大学 (神奈川県・横浜市)
- Year and Date
  2015-01-29
- Data Source
  KAKENHI-PROJECT-25330073
[Presentation] 差分ランダムテストに基づくコンパイラの最適化機会の検出2015
- Author(s)
  岩辻光功, 橋本淳史, 石浦菜岐佐
- Organizer
  電子情報通信学会ソサイエティ大会
- Place of Presentation
  東北大学 (宮城県・仙台市)
- Year and Date
  2015-09-10
- Data Source
  KAKENHI-PROJECT-25330073
[Presentation] Introducing Loop Statements in Random Testing of C Compilers Based on Expected Value Calculation (short paper)2015
- Author(s)
  K. Nakamura and N. Ishiura
- Organizer
  Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2015)
- Place of Presentation
  宜蘭(台湾)
- Year and Date
  2015-03-17
- Data Source
  KAKENHI-PROJECT-25330073
[Presentation] ランダムテストによるCコンパイラの算術最適化機会の検出2015
- Author(s)
  橋本淳史, 石浦菜岐佐
- Organizer
  電子情報通信学会VLSI設計技術研究会
- Place of Presentation
  慶應義塾大学 (神奈川県・横浜市)
- Year and Date
  2015-01-30
- Data Source
  KAKENHI-PROJECT-25330073
[Presentation] 高位合成における可変スケジューリングの近似手法2011
- Author(s)
  曽根康介,石浦菜岐佐
- Organizer
  電子情報通信学会VLSI 設計技術研究会
- Place of Presentation
  慶応義塾大学(神奈川県)
- Year and Date
  2011-01-17
- Data Source
  KAKENHI-PROJECT-20500058
[Presentation] CPUと密に結合したコプロセッサに基づくハードウェア/ソフトウェア協調設計2010
- Author(s)
  戸田勇希,石浦菜岐佐,神原弘之,冨山宏之
- Organizer
  情報処理学会組込みシステム研究会
- Place of Presentation
  株式会社東芝(東京都)
- Year and Date
  2010-01-29
- Data Source
  KAKENHI-PROJECT-20500058
[Presentation] MIPSアセンブリを中間表現とする高位合成システムの実装2010
- Author(s)
  入谷賢孝,池上達也,石浦菜岐佐,神原弘之,冨山宏之
- Organizer
  情報処理学会組込みシステム研究会
- Place of Presentation
  八丈シーパークリゾート(東京都)
- Year and Date
  2010-03-28
- Data Source
  KAKENHI-PROJECT-20500058
[Presentation] 高位合成における可変スケジューリングの近似アルゴリズム2009
- Author(s)
  曽根康介,石浦菜岐佐,入谷賢孝,戸田勇希
- Organizer
  情報処理学会関西支部大会, A-06
- Place of Presentation
  神戸大学(兵庫県)
- Year and Date
  2009-09-29
- Data Source
  KAKENHI-PROJECT-20500058
[Presentation] 高位合成システムCCAPのAMPマルチコアシステム設計のための拡張2009
- Author(s)
  石守祥之,石浦菜岐佐,冨山宏之,神原弘之
- Organizer
  電子情報通信学会VLSI設計技術研究会
- Place of Presentation
  慶応義塾大学(神奈川県)
- Year and Date
  2009-01-29
- Data Source
  KAKENHI-PROJECT-20500058
[Presentation] 不定サイクル演算を考慮した高位合成の可変スケジューリング・バインディング2008
- Author(s)
  戸田勇希,石浦菜岐佐,曽根康介
- Organizer
  電子情報通信学会VLSI設計技術研究会
- Place of Presentation
  北九州市学術研究都市(福岡県)
- Year and Date
  2008-11-19
- Data Source
  KAKENHI-PROJECT-20500058
[Presentation] Cコンパイラの算術最適化のランダムテストにおける浮動小数点演算の導入
- Author(s)
  橋本淳史, 石浦菜岐佐
- Organizer
  電子情報通信学会ソサイエティ大会
- Place of Presentation
  福岡工業大学 (福岡市)
- Data Source
  KAKENHI-PROJECT-25330073
[Presentation] Scaling up Size and Number of Expressions in Random Testing of Arithmetic Optimization of C Compilers Workshop on Synthesis And System Integration of Mixed Information Technologies
- Author(s)
  E. Nagai, A. Hashimoto, and N. Ishiura
- Organizer
  Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2013)
- Place of Presentation
  ホテル札幌ガーデンパレス (札幌市)
- Data Source
  KAKENHI-PROJECT-25330073

1. HIRAISHI Hiromi (40093299)

# of Collaborated Projects: 6 results

# of Collaborated Products: 0 results
2. SHIAKAWA Isao (10029100)

# of Collaborated Projects: 5 results

# of Collaborated Products: 0 results
3. OGINO Hiroyuki (40144323)

# of Collaborated Projects: 5 results

# of Collaborated Products: 0 results
4. TAKAGI Naofumi (10171422)

# of Collaborated Projects: 5 results

# of Collaborated Products: 0 results
5. YAJIMA Shuzo (20025901)

# of Collaborated Projects: 4 results

# of Collaborated Products: 0 results
6. ONOYE Takao (60252590)

# of Collaborated Projects: 4 results

# of Collaborated Products: 0 results
7. YAMAUCHI Hitoshi (10275373)

# of Collaborated Projects: 3 results

# of Collaborated Products: 0 results
8. KANBARA Hiroyuki (80373497)

# of Collaborated Projects: 3 results

# of Collaborated Products: 15 results
9. TOMIYAMA Hiroyuki (80362292)

# of Collaborated Projects: 2 results

# of Collaborated Products: 4 results
10. KAWAKUBO Kazuo (10186067)

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
11. IWAMA Kazuo (50131272)

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
12. SHIGEHIRO Yuji (40243175)

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
13. FUJITA Gen (30304025)

# of Collaborated Projects: 2 results

# of Collaborated Products: 0 results
14. 吉田信明 (00373506)

# of Collaborated Projects: 2 results

# of Collaborated Products: 6 results
15. TAKENAGA Yasuhiko (20236491)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
16. DEGUCHI Hiroshi (30197826)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
17. ARAKI Toshiro (70107077)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
18. KUMAGAI Sadatoshi (10093410)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
19. MIYAHARA Hideo (90029314)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
20. TAKAHASHI Kazuko (30330400)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
21. MIWA Hiroyoshi (40351738)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
22. YASUURA Hiroto (80135540)

# of Collaborated Projects: 1 results

# of Collaborated Products: 0 results
23. Shimizu Miho

# of Collaborated Projects: 1 results

# of Collaborated Products: 3 results
24. Azuma Kagumi

# of Collaborated Projects: 1 results

# of Collaborated Products: 4 results
25. Oosako Yuuki

# of Collaborated Projects: 1 results

# of Collaborated Products: 7 results
26. Ota Sayuri

# of Collaborated Projects: 1 results

# of Collaborated Products: 4 results
27. Nakano Wakako

# of Collaborated Projects: 1 results

# of Collaborated Products: 3 results

ISHIURA Nagisa 石浦 菜岐佐

Nagisa ISHIURA 石浦 菜岐佐

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Synthesis of Full Hardware Implementation of RTOS-Based SystemsPrincipal InvestigatorOngoing

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Interrupt handling and dynamic scheduling for binary synthesisPrincipal Investigator

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Random testing of compilers based on precise computation of expected values and symbolic execution of generated codesPrincipal Investigator

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High-Level Synthesis System Autogenerating Software Compatible HardwarePrincipal Investigator

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Research on retargetable code generation for custom VLIW DSPsPrincipal Investigator

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Codesign Methodology of Application Specific DSPs Based on a Retargetable CompilerPrincipal Investigator

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Research on Code Generation Algorithms for Retargetable Compilers for DSPsPrincipal Investigator

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Research on Control Dominant High-Level SynthesisPrincipal Investigator

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条件分岐と繰り返し構造を含む動作記述からの高位合成手法に関する研究Principal Investigator

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論理関数処理による記号シミュレーションと無解釈評価に基づくプロセッサの形式的検証Principal Investigator

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ISHIURA Nagisa 石浦菜岐佐

Nagisa ISHIURA 石浦菜岐佐