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Onodera Hidetoshi  小野寺 秀俊

ORCIDConnect your ORCID iD *help
… Alternative Names

ONODERA Hidetoshi  小野寺 秀俊

小野寺 英俊  オノデラ ヒデトシ

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Researcher Number 80160927
Other IDs
External Links
Affiliation (Current) 2025: 京都大学, 情報学研究科, 教授
Affiliation (based on the past Project Information) *help 2012 – 2020: 京都大学, 情報学研究科, 教授
2011: 京都大学, 情報研究科, 教授
2007 – 2010: Kyoto University, 情報学研究科, 教授
2000 – 2004: Department of Communications and Computer Engineering, KYOTO UNIVERSITY Professor, 情報学研究科, 教授
1999 – 2001: Kyoto Univ., Graduate Sch. Engin. Prof, 工学研究科, 教授 … More
1999: 京都大学, 大学院・情報学研究科, 教授
1998: 京都大学, 情報学研研究科, 助教授
1998: Kyoto University, Dept.of Communications and Computer Engineering, Associate Professor, 情報学研究科, 助教授
1996 – 1997: 京都大学, 工学部, 助教授
1995 – 1997: Kyoto University, Graduate School of Engineering, Associate Professor, 工学研究科, 助教授
1991 – 1994: Kyoto Univ., Faculty of Engineering, Assoc. Professor, 工学部, 助教授
1986 – 1991: 京都大学, 工学部, 助手 Less
Review Section/Research Field
Principal Investigator
電子デバイス・機器工学 / 計算機科学 / Computer system / Computer system/Network / Science and Engineering
Except Principal Investigator
計算機科学 / 情報工学 / 電子通信系統工学 / 電子デバイス・機器工学 / 計算機工学 / Computer system
Keywords
Principal Investigator
VLSI / 低消費電力化 / ASIC / 集積回路 / SerDes / LSI / DSP / Statistical Analysis / Analog Circuit / アナログ回路 … More / システムオンチップ / 低消費電力設計 / 低電圧動作 / ばらつき / スタンダードセル / 統計的遅延解析 / ばらつき考慮設計 / 製造容易化設計 / 製造ばらつき / 低消費電力技術 / ディペンダブル・コンピューティング / 省エネルギー / 電子デバイス・機器 / オンチップモニタ / 消費エネルギー最小化 / 基板電圧制御 / 動的電圧制御 / 最小エネルギー動作 / Signal Transmission / 応答局面法 / スパイラルインダクタ / ドライバ駆動力 / 配線構造 / 伝送線路 / LSI配線 / RLC抽出 / 性能予測 / リング型PLL / LC型PLL / PLL / オンチップ伝送線路 / 高速信号伝達 / 配線特性 / 高速信号伝送 / Hierarchical Design / Inter-Chip Variability / Intra-Chip Variability / Statistical Timing Analysis / Manufacturing Variability / モンテカルロ解析 / 統計モデリング / 設計容易化技術 / ロバスト設計 / 歩留り最大化 / 統計的解析 / 階層設計 / チップ間ばらつき / チップ内ばらつき / 統計解析 / Low-rate / Image Compression / Parallel Processing / Multimedia / 高速バス / 機能メモリ / FMPP / 低ビットレート / 画像圧縮 / 並列処理 / マルチメディア / Input reordering / Gate sizing / Standard cell library / Library generation / Cell-base design / High speed design / Low power design / optimization of detailed design / 最適化設計 / CMOS理論ゲート / 遅延時間モデル / 消費電力モデル / 遅延最適化 / 物理設計 / システムLSI / ディープサブミクロンプロセス / 遅延最小化 / クロストーク / 詳細設計 / 接続最適化 / ゲート寸法最適化 / スタンダードセルライブラリ / ライブラリ生成 / セルベース設計 / 高速化設計 / 低消費電力化設計 / 詳細設計最適化 / Worst Case Analysis / Circuit Simulation / Matching Analysis / Parameter Extraction / Intermediate Model / Statistical Modeling / Scaled MOSFET / 共通モデル / 歩留り / 統計的設計最適化 / パラメータ抽出 / 統計的モデル化 / ばらつきモデル / ワ-ストケース解析 / 回路シミュレーション / 統計的回路解析 / 比精度解析 / モデルパラメータ抽出 / 中間モデル / 統計モデル / MOSFET / Analog HDL / Analog CAD / Circuit Design / Layout Design / Optimization / Analog Layout / アナログHDL / アナログCAD / 回路設計 / レイアウト設計 / 最適化 / アナログレイアウト / Gate Array / Standard Cell / LSI Design / Comprehenseve Benchmarks / LSI CAD / Symbolic Layout / Standard Library / ゲートアレー / LSI設計 / 総合ベンチマークセット / LSIのCAD / シンボリックレイアウト / 標準ライブラリ / 組込システム / ディペンダブルシステム / 組込みシステム / 製造容易化 / ディペンダブルLSI / LSI設計技術 / ディペンダブル VLSI / 耐ばらつき設計 / 製造容易性 / DFY / DFM / NBTI / 経年劣化 / 歩留まり / ディペンダブルVLSI / 高信頼化 / 動画像 / 動きベクトル / ジャイロセンサ / 動き補償 … More
Except Principal Investigator
FPGA / 集積回路 / 低消費電力 / アーキテクチャ / VLSI / 教育用マイクロプロセッサ / 計算機工学教育 / FMPP / Symbolic Layout / アナログLSI / 論理合成 / シンボリックレイアウト / LSI / Design Techniques / Architecture / 設計手法 / プロセッサアレー / 動き補償 / 動画像圧縮 / 光通信 / educational microprocessor / Analog LSI / KUE-CHIP2 / KITE / QP-DLX / 集積回路工学 / Parallel Processing / 並列処理 / Functional Memory / 計算機アーキテクチャ / CAM / 連想メモリ / 機能メモリ / Logic Synthesis / 自動論理合成 / コンパクション / システムオンチップ / 計算機システム / エネルギー効率化 / 低消費電力・高エネルギー密度 / マイクロプロセッサ / 環境発電 / 光導波 / 光集積回路 / 超高速 / 光復調 / 光変調 / 高速光復調 / 高速光変調 / Compaction / Methodology of Block Placement / Layout Editor / Hierarchical Design / CAD System / デバイスシミュレータ / 自動設計 / 回路記述 / 回路解析 / レイアウト / アナログ回路 / オペアンプの自動設計 / ブロック配置手法 / レイアウトエディタ / 階層設計 / CADシステム / Semi-conductor Lasers / Synchronization of Oscilaators / Optical Amplification / 増幅 / 光,レーザー / 同期 / 光 / 半導体レーザー / 発振器同期 / 光増幅 / Energy Recovery / Adiabatic Circuits / Caches / Date Reuse / Low-Power / Processor / 回路設計 / 断熱回路 / エネルギー回復 / プロセッサ / Video Compression / Low Power / Memory Distribution / Motion Estimation / プロセッサ アレー / VLSI design / curriculum / services of chip implementation / cell libraries / education of VLSI dsign / education of computer science / integrated circuit / ゲートアレー / フルカスタム設計 / ゲートアレイ / VLSI設計 / 教育カリキュラム / セルライブラリ / チップ試作サービス / VLSI設計教育 / Image Compression / Low Bit-rate / Vector Quantization / 超並列処理 / 低ビットレート / 画像圧縮 / 高速バス / computer architecture / experiment curriculum / LSI design education / computer engineering education / software education / hardware education / LSI設計 / 実験カリキュラム / LSI設計教育 / ソフトウェア実験 / ハードウェア実験 / LSI Design System / Reuse of Design Knowledge / Knowledge Aquisition / Analog ASIC / Design Methodology of Analog LSI / Reuse of Design Procedure / アナログ回路最適化 / アナログレイアウト合成 / アナログ回路合成 / モジュールジェネレータ / アナログCAD / 設計知識獲得 / LSI設計システム / 知識再利用 / 知識獲得 / アナログASIC / アナログ回路設計手法 / 設計方法の再利用 / CAD Benchmark / Education-purpose Microprosessor / VLSI Engineering / Computer Engineering Education / 集積回路工学教育 / プロトタイプ / CADベンチマ-ク / CADベンチマーク / Geometrical processing / Content addressable memory / Hardware engine / Layout verification / LSI layout / Design rule check / ハードウエアエンジン / 図形演算 / ハードウェアエンジン / デザインルールチェック / レイアウト検証 / LSIレイアウト / 図形処理専用計算機 / Functional Level Simulation / Binary Decision Diagram / Combinational Logic Circuits / Sequential Circuits / Arithmetic Functions / Functional Information Extraction / Design Verification / 回路抽出 / 機能表 / レジスタ転送レベル / SBDD / 統合ベンチマ-ク / マニュアルの作成支援 / ドキュメント / 機能記述言語 / 設計検証 / 機能レベルシミュレ-ションモデル / 算術演算機能 / 2分決定木 / 順序回路 / 組み合わせ論理回路 / 機能情報抽出 / Massively Parallel Processing / Massively Parallel Computation / SIMD / Massively Parallel Algorithm / Content Addressable Memory / Functional Memory Type Parallel Processor Architecture / 神経回路網 / 論理シミュレ-ションエンジン / 並列計算機 / 超並列計算ア-キテクチャ / 超並列計算機アーキテクチャ / 機能メモリ型並列プロセサ / 超並列計算機 / 超並列演算 / 超並列アルゴリズム / 機能メモリ型並列プロセサアーキテクチャ / CAD Framework / Module Generator / LSI CAD / Circuit Synthesis / Automatic Layout / Integrated Analog-Digital CAD System / アナログ-ディジタル統合CAD / アナログ-ディジタル混載LSI / ディジタルLSI / CADデ-タベ-ス / アナログ回路自動合成 / シンポリックレイアウト / アナログ-ディジタル統合CADシステム / CADデザインフレ-ムワ-ク / モジュ-ルジェネレ-タ / LSIのCAD / 回路合成 / 自動レイアウト / アナログーディジタル統合CADシステム / スマートセンサ情報システム / 省エネルギー / 電子デバイス・機器 / 低消費電力設計 Less
  • Research Projects

    (28 results)
  • Research Products

    (160 results)
  • Co-Researchers

    (31 People)
  •  Research on computing infrastructure aimed at realizing an IoT society to come

    • Principal Investigator
      Ishihara Tohru
    • Project Period (FY)
      2017 – 2019
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      Computer system
    • Research Institution
      Nagoya University
  •  LSI Design Method for Minimum Energy OperationPrincipal Investigator

    • Principal Investigator
      Onodera Hidetoshi
    • Project Period (FY)
      2016 – 2019
    • Research Category
      Grant-in-Aid for Scientific Research (A)
    • Research Field
      Computer system
    • Research Institution
      Kyoto University
  •  A Study on Energy Harvesting Embedded Computers as a Social Infrastructure

    • Principal Investigator
      Ishihara Tohru
    • Project Period (FY)
      2014 – 2016
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      Computer system
    • Research Institution
      Kyoto University
  •  LSI design methodology that enables robust operation under the supply as low as threshold voltage by self-compensating performance variabilityPrincipal Investigator

    • Principal Investigator
      ONODERA Hidetoshi
    • Project Period (FY)
      2013 – 2016
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      Computer system
    • Research Institution
      Kyoto University
  •  Integrated Circuit Design for Robust Operation under Low Supply VoltagePrincipal Investigator

    • Principal Investigator
      ONODERA Hidetoshi
    • Project Period (FY)
      2010 – 2012
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      Computer system/Network
    • Research Institution
      Kyoto University
  •  Variation and Defect Aware Design of Integrated CircuitsPrincipal Investigator

    • Principal Investigator
      ONODERA Hidetoshi
    • Project Period (FY)
      2007 – 2009
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      Computer system/Network
    • Research Institution
      Kyoto University
  •  Research of a High-speed Signal Transmission Scheme for Integrated CircuitsPrincipal Investigator

    • Principal Investigator
      ONODERA Hidetoshi
    • Project Period (FY)
      2002 – 2004
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      電子デバイス・機器工学
    • Research Institution
      KYOTO UNIVERSITY
  •  動き補償を利用した動画像の実時間背景・対象物分離アルゴリズムとハードウエアの開発Principal Investigator

    • Principal Investigator
      小野寺 秀俊
    • Project Period (FY)
      2001 – 2002
    • Research Category
      Grant-in-Aid for Scientific Research on Priority Areas
    • Review Section
      Science and Engineering
    • Research Institution
      Kyoto University
  •  Development of Statistical Performance Analysis and Optimization Methods for Large Scale Integrated CircuitsPrincipal Investigator

    • Principal Investigator
      ONODERA Hidetoshi
    • Project Period (FY)
      1999 – 2001
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      電子デバイス・機器工学
    • Research Institution
      KYOTO UNIVERSITY
  •  Development of a Energy-Recovering Low-Power Processor Architecture.

    • Principal Investigator
      MOSHNYAGA Vasily
    • Project Period (FY)
      1999 – 2001
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      計算機科学
    • Research Institution
      Fukuoka University
  •  Development of a Functional LSI Achieving Low-rate Multimedia Data Transmission.Principal Investigator

    • Principal Investigator
      ONODERA Hidetoshi, 田丸 啓吉
    • Project Period (FY)
      1998 – 2000
    • Research Category
      Grant-in-Aid for Scientific Research (B).
    • Research Field
      電子デバイス・機器工学
    • Research Institution
      KYOTO UNIVERSITY
  •  Development of a Memory-Based Low-Energy Processor for Real-Time Motion

    • Principal Investigator
      MOSHNYAGA Vashily
    • Project Period (FY)
      1998 – 1999
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Research Field
      電子デバイス・機器工学
    • Research Institution
      Fukuoka University
  •  Optimization of detailed design for UDSM (ultra deep submicron) integrated circuitsPrincipal Investigator

    • Principal Investigator
      ONODERA Hidetoshi
    • Project Period (FY)
      1997 – 1998
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Research Field
      電子デバイス・機器工学
    • Research Institution
      KYOTO UNIVERSITY
  •  Statistical modeling method for scaled MOSFETPrincipal Investigator

    • Principal Investigator
      ONODERA Hidetoshi
    • Project Period (FY)
      1996 – 1997
    • Research Category
      Grant-in-Aid for Scientific Research (A)
    • Research Field
      電子デバイス・機器工学
    • Research Institution
      KYOTO UNIVERSITY
  •  Development of Curriculums for Education of VLSI System Design.

    • Principal Investigator
      YASUURA Hiroto
    • Project Period (FY)
      1996 – 1997
    • Research Category
      Grant-in-Aid for Scientific Research (A)
    • Research Field
      計算機科学
    • Research Institution
      KYUSHU UNIVERSITY
  •  Development of a Computing System by a Functional Memory Type Parallel Processor.

    • Principal Investigator
      TAMARU Keikichi
    • Project Period (FY)
      1995 – 1997
    • Research Category
      Grant-in-Aid for Scientific Research (A)
    • Research Field
      計算機科学
    • Research Institution
      KYOTO UNIVERSITY
  •  Development of Comprehensive Set of LSI CAD BenchmarksPrincipal Investigator

    • Principal Investigator
      ONODERA Hidetoshi
    • Project Period (FY)
      1994 – 1995
    • Research Category
      Grant-in-Aid for Developmental Scientific Research (B)
    • Research Field
      計算機科学
    • Research Institution
      KYOTO UNIVERSITY
  •  Development of Educational Microprocessors for Computer Science Education

    • Principal Investigator
      YASUURA Hiroto
    • Project Period (FY)
      1994 – 1995
    • Research Category
      Grant-in-Aid for Developmental Scientific Research (B)
    • Research Field
      計算機科学
    • Research Institution
      Kyushu University
  •  Simultaneous Circuit and Layout Design Method for Analog LSIs under Performance ConstraintsPrincipal Investigator

    • Principal Investigator
      ONODERA Hidetoshi
    • Project Period (FY)
      1994 – 1995
    • Research Category
      Grant-in-Aid for General Scientific Research (C)
    • Research Field
      計算機科学
    • Research Institution
      KYOTO UNIVERSITY
  •  Effective Design Methodology for Analog LSIs that Acquires and Reuses Design

    • Principal Investigator
      TAMARU Keikichi
    • Project Period (FY)
      1993 – 1995
    • Research Category
      Grant-in-Aid for General Scientific Research (B)
    • Research Field
      電子デバイス・機器工学
    • Research Institution
      KYOTO UNIVERSITY
  •  Development of a Computer Specific to LSI Geometrical Processing

    • Principal Investigator
      TAMARU Keikichi
    • Project Period (FY)
      1992 – 1994
    • Research Category
      Grant-in-Aid for Developmental Scientific Research (B)
    • Research Field
      情報工学
    • Research Institution
      KYOTO UNIVERSITY
  •  Development of Education-Microprocessor for Computer Engineering and VLSI Engineering.

    • Principal Investigator
      YASUURA Hiroshi
    • Project Period (FY)
      1992 – 1993
    • Research Category
      Grant-in-Aid for Developmental Scientific Research (B)
    • Research Field
      情報工学
    • Research Institution
      KYUSHU UNIVERSITY
  •  Studies on Functional Memory Type Parallel Processor Architectures and Their Massively Parallel Algorithms.

    • Principal Investigator
      TAMARU Keikichi
    • Project Period (FY)
      1990 – 1992
    • Research Category
      Grant-in-Aid for General Scientific Research (B)
    • Research Field
      情報工学
    • Research Institution
      KYOTO UNIVERSITY
  •  Research on High-Level Information Extraction in Integrated Circuit Design

    • Principal Investigator
      YASUURA Hiroto
    • Project Period (FY)
      1990 – 1991
    • Research Category
      Grant-in-Aid for General Scientific Research (C)
    • Research Field
      情報工学
    • Research Institution
      Kyoto University
  •  Development of an Integrated Analog-Digital CAD System

    • Principal Investigator
      TAMARU Keikichi
    • Project Period (FY)
      1989 – 1991
    • Research Category
      Grant-in-Aid for Developmental Scientific Research
    • Research Field
      計算機工学
    • Research Institution
      Kyoto University
  •  新しい超高速変調・復調光通信システムに関する基礎研究

    • Principal Investigator
      中島 将光 (中島 將光)
    • Project Period (FY)
      1988 – 1990
    • Research Category
      Grant-in-Aid for General Scientific Research (B)
    • Research Field
      電子通信系統工学
    • Research Institution
      Kyoto University
  •  Studies on a Hierarchical CAD System for Analog LSIs

    • Principal Investigator
      TAMARU Keikichi
    • Project Period (FY)
      1987 – 1988
    • Research Category
      Grant-in-Aid for General Scientific Research (B)
    • Research Field
      計算機工学
    • Research Institution
      Kyoto University
  •  A Basic Study on Optical Amplification by use of Synchronization of Coupled Laser Oscillators

    • Principal Investigator
      NAKAJIMA Masamitsu
    • Project Period (FY)
      1985 – 1987
    • Research Category
      Grant-in-Aid for General Scientific Research (B)
    • Research Field
      電子通信系統工学
    • Research Institution
      Kyoto University

All 2021 2020 2019 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 2008 2007 2005 2004 2003 Other

All Journal Article Presentation

  • [Journal Article] A DLL-based Body Bias Generator with Independent P-well and N-well Biasing for Minimum Energy Operation2021

    • Author(s)
      Kentaro Nagai, Jun Shiomi, Hidetoshi Onodera
    • Journal Title

      IEICE Trans. on Electronics,

      Volume: Vol. E104

    • NAID

      130008095562

    • Peer Reviewed / Open Access
    • Data Source
      KAKENHI-PROJECT-16H01713
  • [Journal Article] Circuit Techniques for Device-Circuit Interaction toward Minimum Energy Operation2019

    • Author(s)
      Islam A.K.M. Mahfuzul、Onodera Hidetoshi
    • Journal Title

      IPSJ Transactions on System LSI Design Methodology

      Volume: 12 Issue: 0 Pages: 2-12

    • DOI

      10.2197/ipsjtsldm.12.2

    • NAID

      130007603207

    • ISSN
      1882-6687
    • Language
      English
    • Peer Reviewed / Open Access
    • Data Source
      KAKENHI-PROJECT-16H01713
  • [Journal Article] On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing2019

    • Author(s)
      XU Hongjie、SHIOMI Jun、ISHIHARA Tohru、ONODERA Hidetoshi
    • Journal Title

      IEICE Trans. Fundamentals

      Volume: E102.A Issue: 12 Pages: 1741-1750

    • DOI

      10.1587/transfun.E102.A.1741

    • NAID

      130007754040

    • ISSN
      0916-8508, 1745-1337
    • Year and Date
      2019-12-01
    • Language
      English
    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-17H01712
  • [Journal Article] A Design Method of a Cell-Based Amplifier for Body Bias Generation2019

    • Author(s)
      KOYANAGI Takuya、SHIOMI Jun、ISHIHARA Tohru、ONODERA Hidetoshi
    • Journal Title

      IEICE Trans. Electron.

      Volume: E102.C Issue: 7 Pages: 565-572

    • DOI

      10.1587/transele.2018CTP0014

    • NAID

      130007671364

    • ISSN
      0916-8524, 1745-1353
    • Year and Date
      2019-07-01
    • Language
      English
    • Peer Reviewed / Open Access
    • Data Source
      KAKENHI-PROJECT-16H01713, KAKENHI-PROJECT-17H01712
  • [Journal Article] A temperature monitor circuit with small voltage sensitivity using a topology-reconfigurable ring oscillator2018

    • Author(s)
      Kishimoto Tadashi、Ishihara Tohru、Onodera Hidetoshi
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: 57 Issue: 4S Pages: 04FF09-04FF09

    • DOI

      10.7567/jjap.57.04ff09

    • NAID

      210000148923

    • Peer Reviewed / Open Access
    • Data Source
      KAKENHI-PROJECT-16H01713, KAKENHI-PROJECT-17H01712
  • [Journal Article] Minimum Energy Point Tracking with All-Digital On-Chip Sensors2018

    • Author(s)
      Shiomi Jun、Hokimoto Shu、Ishihara Tohru、Onodera Hidetoshi
    • Journal Title

      Journal of Low Power Electronics

      Volume: 14 Issue: 2 Pages: 227-235

    • DOI

      10.1166/jolpe.2018.1561

    • Peer Reviewed / Open Access
    • Data Source
      KAKENHI-PROJECT-16H01713, KAKENHI-PROJECT-17H01712
  • [Journal Article] Area-Efficient Fully Digital Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing2017

    • Author(s)
      Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
    • Journal Title

      Integration, the VLSI Journal

      Volume: N/A Pages: 201-210

    • DOI

      10.1016/j.vlsi.2017.07.001

    • Peer Reviewed / Open Access
    • Data Source
      KAKENHI-PROJECT-16J08694, KAKENHI-PROJECT-16H01713, KAKENHI-PROJECT-17H01712
  • [Journal Article] A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation2017

    • Author(s)
      Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
    • Journal Title

      IEICE Trans. Fundamentals

      Volume: E100.A Issue: 12 Pages: 2764-2775

    • DOI

      10.1587/transfun.E100.A.2764

    • NAID

      130006236534

    • ISSN
      0916-8508, 1745-1337
    • Language
      English
    • Peer Reviewed / Open Access
    • Data Source
      KAKENHI-PROJECT-16J08694, KAKENHI-PROJECT-16H01713, KAKENHI-PROJECT-17H01712
  • [Journal Article] A Minimum Energy Point Tracking Algorithm Based on Dynamic Voltage Scaling and Adaptive Body Biasing2017

    • Author(s)
      HOKIMOTO Shu、ISHIHARA Tohru、ONODERA Hidetoshi
    • Journal Title

      IEICE Trans. Fundamentals

      Volume: E100.A Issue: 12 Pages: 2776-2784

    • DOI

      10.1587/transfun.E100.A.2776

    • NAID

      130006236535

    • ISSN
      0916-8508, 1745-1337
    • Language
      English
    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-17H01712
  • [Journal Article] Analytical Stability Modeling for CMOS Latches in Low Voltage Operation2016

    • Author(s)
      Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
    • Journal Title

      IEICE Trans. Fundamentals

      Volume: E99.A Issue: 12 Pages: 2463-2472

    • DOI

      10.1587/transfun.E99.A.2463

    • NAID

      130005170525

    • ISSN
      0916-8508, 1745-1337
    • Language
      English
    • Peer Reviewed / Acknowledgement Compliant / Open Access
    • Data Source
      KAKENHI-PROJECT-25280014, KAKENHI-PROJECT-26280013
  • [Journal Article] A Forward/Reverse Body Bias Generator with Wide Supply-Range down to Threshold Voltage2015

    • Author(s)
      N. Kamae, A. Tsuchiya, H. Onodera
    • Journal Title

      IEICE Trans. Electron.

      Volume: E98.C Issue: 6 Pages: 504-511

    • DOI

      10.1587/transele.E98.C.504

    • NAID

      130005072389

    • ISSN
      0916-8524, 1745-1353
    • Language
      English
    • Peer Reviewed / Acknowledgement Compliant / Open Access
    • Data Source
      KAKENHI-PROJECT-25280014
  • [Journal Article] Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell2015

    • Author(s)
      Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
    • Journal Title

      IPSJ Transactions on System LSI Design Methodology

      Volume: 8 Issue: 0 Pages: 131-135

    • DOI

      10.2197/ipsjtsldm.8.131

    • NAID

      130005091214

    • ISSN
      1882-6687
    • Language
      English
    • Peer Reviewed / Acknowledgement Compliant / Open Access
    • Data Source
      KAKENHI-PROJECT-25280014
  • [Journal Article] Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization2015

    • Author(s)
      Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
    • Journal Title

      IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

      Volume: Vol. E98-A

    • NAID

      130005085789

    • Peer Reviewed / Acknowledgement Compliant
    • Data Source
      KAKENHI-PROJECT-26280013
  • [Journal Article] Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization2015

    • Author(s)
      Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
    • Journal Title

      IEICE Trans. Fundamentals

      Volume: E98.A Issue: 7 Pages: 1455-1466

    • DOI

      10.1587/transfun.E98.A.1455

    • NAID

      130005085789

    • ISSN
      0916-8508, 1745-1337
    • Language
      English
    • Peer Reviewed / Acknowledgement Compliant / Open Access
    • Data Source
      KAKENHI-PROJECT-25280014, KAKENHI-PROJECT-26280013
  • [Journal Article] Radiation-Hardened PLL with a Switchable Dual Modular Redundancy Structure2014

    • Author(s)
      SinNyoung Kim, Akira Tsuchiya, and Hidetoshi Onodera
    • Journal Title

      IEICE Trans. Electron.

      Volume: E97.C Issue: 4 Pages: 325-331

    • DOI

      10.1587/transele.E97.C.325

    • NAID

      130003394725

    • ISSN
      0916-8524, 1745-1353
    • Language
      English
    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-25280014
  • [Journal Article] A Body Bias Generator with Low Supply Voltage for Within-Die Variability Compensation2014

    • Author(s)
      Norihiro KAMAE, Akira TSUCHIYA, Hidetoshi ONODERA
    • Journal Title

      IEICE Trans. Fundamentals

      Volume: E97.A Issue: 3 Pages: 734-740

    • DOI

      10.1587/transfun.E97.A.734

    • NAID

      130003394776

    • ISSN
      0916-8508, 1745-1337
    • Language
      English
    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-25280014
  • [Journal Article] Analysis of Radiation-Induced Clock-Perturbation in Phase-Locked Loop2014

    • Author(s)
      SinNyoung Kim, Akira Tsuchiya, and Hidetoshi Onodera
    • Journal Title

      IEICE Trans. Fundamentals

      Volume: E97.A Issue: 3 Pages: 768-776

    • DOI

      10.1587/transfun.E97.A.768

    • NAID

      130003394780

    • ISSN
      0916-8508, 1745-1337
    • Language
      English
    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-25280014
  • [Journal Article] On-chip Measurement of Rise/Fall Gate Delay Using Reconfigurable Ring Oscillator2014

    • Author(s)
      Bishnu Prasad Das, Hidetoshi Onodera
    • Journal Title

      IEEE Transactions on Circuits and Systems II

      Volume: 61 Pages: 183-187

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-25280014
  • [Journal Article] On-Chip Detection of Process Shift and Process Spread for Post-Silicon Diagnosis and Model-Hardware Correlation2013

    • Author(s)
      A.K.M. Mahfuzul Islam, and Hidetoshi Onodera
    • Journal Title

      IEICE Trans. Inf. & Syst.

      Volume: E96.D Issue: 9 Pages: 1971-1979

    • DOI

      10.1587/transinf.E96.D.1971

    • NAID

      130003370985

    • ISSN
      0916-8532, 1745-1361
    • Language
      English
    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-25280014
  • [Journal Article] Impact of Body-Biasing Technique on Random Telegraph Noise Induced Delay Fluctuation2013

    • Author(s)
      Takashi Matsumoto, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Journal Title

      Japanese Journal of Applied Physics (JJAP)

      Volume: vol 52, no 4 Issue: 4S Pages: 1-3

    • DOI

      10.7567/jjap.52.04ce05

    • NAID

      210000142035

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Journal Article] Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation2013

    • Author(s)
      Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
    • Journal Title

      IEICE Trans. Fundamentals

      Volume: E96.A Issue: 12 Pages: 2499-2507

    • DOI

      10.1587/transfun.E96.A.2499

    • NAID

      130003385302

    • ISSN
      0916-8508, 1745-1337
    • Language
      English
    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-25280014
  • [Journal Article] Variation-sensitive Monitor Circuits for Estimation of Global Process Parameter Variation2012

    • Author(s)
      Islam A.K.M. Mahfuzul, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Journal Title

      IEEE Trans. Semiconductor Manufacturing

      Volume: vol 25, no 4 Issue: 4 Pages: 571-580

    • DOI

      10.1109/tsm.2012.2198677

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Journal Article] Multicore Large-Scale Integration Lifetime Extention by Negative Bias Temperature Instability Recovery-Based Self-Healing2012

    • Author(s)
      Takashi Matsumoto, Hiroaki Makino, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: vol.51(印刷中)

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Journal Article] A 65 nm Complementary Metal-Oxide-Semiconductor 400 ns Measurement Delay Negative-Bias-Temperature-Instability Recovery Sensor with Minimum Assist Circuit2011

    • Author(s)
      Takashi Matsumoto, Hiroaki Makino, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: vol.50

    • NAID

      210000070301

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Journal Article] Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells2010

    • Author(s)
      H.Sunagawa, H.Terada, A.Tsuchiya, K.Kobayashi, H.Onodera
    • Journal Title

      IPSJ Transactions on System LSI Design Methodology Vol. 3

      Pages: 130-139

    • NAID

      130000251502

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-19300010
  • [Journal Article] Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells2010

    • Author(s)
      Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Journal Title

      IPSJ Transactions on System LSI Design Methodology vol.3

      Pages: 130-139

    • NAID

      130000251502

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-19300010
  • [Journal Article] Statistical Gate Delay Model for Multiple Input Switching2009

    • Author(s)
      Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera
    • Journal Title

      IEICE Transact-ions on Fundamentals E92-A

      Pages: 3070-3078

    • NAID

      10026861436

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-19300010
  • [Journal Article] Statistical Gate Delay Model for Multiple Input Switching2009

    • Author(s)
      Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera
    • Journal Title

      IEICE Transactions on Fundamentals vol.E92-A,no.12

      Pages: 3070-3078

    • NAID

      10026861436

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-19300010
  • [Journal Article] Accurate Estimation of the Worst-case Delay in Statistical Static Timing Analysis2008

    • Author(s)
      Haruhiko Terada, Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera
    • Journal Title

      IPSJ Transactions on System LSI Design Methodology 1

      Pages: 116-125

    • NAID

      130002073186

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-19300010
  • [Journal Article] Manufacturability-Aware Design of Standard Cells2008

    • Author(s)
      Hirokazu Muta, Hidetoshi Onodera
    • Journal Title

      IEICE Transactions on Electronics E90-A

      Pages: 2682-2690

    • NAID

      110007538012

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-19300010
  • [Journal Article] Design and Measurement of 6.4Gbps 8:1 Multiplexer in 0.18um CMOS Process2005

    • Author(s)
      A.Shinmyo, M.Gashimoto, H.Onodera
    • Journal Title

      Proc.ASP-DAC

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-14350186
  • [Journal Article] A Performance Prediction of Clock Generation PLLs:2005

    • Author(s)
      T.Miyazaki, M.Hasimoto, H.Onodera
    • Journal Title

      IEICE Trans.on Electronics E88-C, no.3(to appear)

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-14350186
  • [Journal Article] Design and Measurement of 6.4Gbps 8:1 Multiplexer in 0.18um CMOS Process2005

    • Author(s)
      A.Shinmyo, M.Hashimoto, H.Onodera
    • Journal Title

      Proc.ASP-DAC D-9-11

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-14350186
  • [Journal Article] Design and Measurement of 6.4Gbps 8:1 Multiplexer in 0.18um CMOS Process2005

    • Author(s)
      A.Shinmyo, M.Hashimoto, H.Onodera
    • Journal Title

      Proc.ASP-DAC

    • Data Source
      KAKENHI-PROJECT-14350186
  • [Journal Article] Return Path Selection for Loop RL Extraction2005

    • Author(s)
      A.Tsuchiya, M.Hashimoto, H.Onodera
    • Journal Title

      Proc.ASP-DAC

      Pages: 1078-1081

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-14350186
  • [Journal Article] A Performance Prediction of Clock Generation PLLs :2005

    • Author(s)
      T.Miyazaki, M.Hasimoto, H.Onodera
    • Journal Title

      IEICE Trans.on Electronics E88-C, no.3 (to appear)

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-14350186
  • [Journal Article] On-Chip Global Signaling by Wave Pipelining2004

    • Author(s)
      M.Hashimoto, A.Tsuchiya, H.Onodera
    • Journal Title

      Proc.of IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging

      Pages: 311-314

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-14350186
  • [Journal Article] Performance Prediction of On-chip Global Signaling2004

    • Author(s)
      M.Hashimoto, A.Tsuchiya, A.Shinmyo, H.Onodera
    • Journal Title

      Proc.of IEEE Electrical Design of Advanced Packaging and Systems

      Pages: 87-100

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-14350186
  • [Journal Article] Representative Frequency for Interconnect R(f)L(f)C Extraction2003

    • Author(s)
      A.Rsuchiya, M.Hashimoto, H.Onodera
    • Journal Title

      IEICE Trans.on Fundamentals E86-A, no.12

      Pages: 2942-2951

    • NAID

      110003212574

    • Description
      「研究成果報告書概要(和文)」より
    • Data Source
      KAKENHI-PROJECT-14350186
  • [Journal Article] Representative Frequency for Interconnect R(f)L(f)C Extraction :2003

    • Author(s)
      A.Tsuchiya, M.Hashimoto, H.Onodera
    • Journal Title

      IEICE Trans.on Fundamentals E86-A, no.12

      Pages: 2942-2951

    • NAID

      110003212574

    • Description
      「研究成果報告書概要(欧文)」より
    • Data Source
      KAKENHI-PROJECT-14350186
  • [Presentation] Dynamic Supply and Threshold Voltage Scaling towards Runtime Energy Optimization over a Wide Operating Performance Region2020

    • Author(s)
      Shoya Sonoda, Jun Shiomi, Hidetoshi Onodera
    • Organizer
      2020 IEEE International SOC Conference (SOCC)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H01713
  • [Presentation] A DLL-based Body Bias Generator for Minimum Energy Operation with Independent P-well and N-well Bias2020

    • Author(s)
      Kentaro Nagai, Jun Shiomi and Hidetoshi Onodera
    • Organizer
      2020 the 16th IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H01713
  • [Presentation] Analysis of Random Telegraph Noise (RTN) at Near-Threshold Operation by Measuring 154k Ring Oscillators2019

    • Author(s)
      A.K.M. Mahfuzul Islam, Ryota Shimizu, Hidetoshi Onodera
    • Organizer
      2019 IEEE International Reliability Physics Symposium (IRPS)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H01713
  • [Presentation] A Process-Scheduler-Based Approach to Minimum Energy Point Tracking2019

    • Author(s)
      Shengyu Liu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
    • Organizer
      DAシンポジウム
    • Data Source
      KAKENHI-PROJECT-17H01712
  • [Presentation] 広範囲な電圧領域で動作するフリップフロップのタイミング特性モデル2019

    • Author(s)
      内田翼、塩見準、石原亨、小野寺秀俊
    • Organizer
      DAシンポジウム
    • Data Source
      KAKENHI-PROJECT-17H01712
  • [Presentation] Independent N-well and P-well Biasing for Minimum Leakage Energy Operation2018

    • Author(s)
      Yosuke Okamura, Tohru Ishihara, Hidetoshi Onodera
    • Organizer
      The International Symposium on On-Line Testing and Robust System Design
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H01713
  • [Presentation] アルタイム電圧最適化によるマルチタスク処理の消費エネルギー最小化2018

    • Author(s)
      塩見準,石原亨,小野寺秀俊
    • Organizer
      情報処理学会システムとLSIの設計技術研究会
    • Data Source
      KAKENHI-PROJECT-17H01712
  • [Presentation] PVT^2: Process, Voltage, Temperature and Time-dependent Variability in Scaled CMOS Process2018

    • Author(s)
      A.K.M. Mahfuzul Islam and Hidetoshi Onodera
    • Organizer
      IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN
    • Invited / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H01713
  • [Presentation] Independent N-Well And P-Well Biasing For Minimum Leakage Energy Operation2018

    • Author(s)
      Okamura Yosuke、Ishihara Tohru、Onodera Hidetoshi
    • Organizer
      International Symposium on On-Line Testing and Robust System Design
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-17H01712
  • [Presentation] A Hybrid Caching System Using SRAM and Standard-Cell Memory for Energy-Efficient Near-Threshold Circuits2018

    • Author(s)
      Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
    • Organizer
      The 21st Workshop on Synthesis And System Integration of Mixed Information technologies
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-17H01712
  • [Presentation] On-Chip Reconfigurable Monitor Circuit for Process Variation and Temperature Estimation2018

    • Author(s)
      Tadashi Kishimoto, Tohru Ishihara and Hidetoshi Onodera
    • Organizer
      International Conference on Microelectronic Test Structures
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H01713
  • [Presentation] 幅広い動作環境にわたってLSIの最大遅延特性を追跡するクリティカルパスレプリカの構成法2018

    • Author(s)
      福田展和, 塩見準, 石原亨, 小野寺秀俊
    • Organizer
      情報処理学会システムとLSIの設計技術研究発表会
    • Data Source
      KAKENHI-PROJECT-17H01712
  • [Presentation] Process Variation Aware D-Flip-Flop Design using Regression Analysis2018

    • Author(s)
      Shinichi Nishizawa, Hidetoshi Onodera
    • Organizer
      International Symposium on Quality Electronic Design
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H01713
  • [Presentation] Individual Voltage Scaling in Logic and Memory Circuits towards Runtime Energy Optimization in Processors2018

    • Author(s)
      Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
    • Organizer
      International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-17H01712
  • [Presentation] A Software Implementation of Minimum Energy Point Tracking Algorithm for Microprocessors2018

    • Author(s)
      Shengyu Liu,Jun Shiomi,Tohru Ishihara,Hidetoshi Onodera
    • Organizer
      情報処理学会DAシンポジウム
    • Data Source
      KAKENHI-PROJECT-17H01712
  • [Presentation] 選択的活性化によるスタンダードセルメモリの低消費エネルギー化2018

    • Author(s)
      塩見準,石原亨,小野寺秀俊
    • Organizer
      情報処理学会システムとLSIの設計技術研究会
    • Data Source
      KAKENHI-PROJECT-17H01712
  • [Presentation] All-digital on-chip heterogeneous sensors for tracking the minimum energy point of processors2018

    • Author(s)
      Hokimoto Shu、Shiomi Jun、Ishihara Tohru、Onodera Hidetoshi
    • Organizer
      International Conference on Microelectronic Test Structures
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-17H01712
  • [Presentation] On-chip reconfigurable monitor circuit for process variation and temperature estimation2018

    • Author(s)
      Kishimoto Tadashi、Ishihara Tohru、Onodera Hidetoshi
    • Organizer
      International Conference on Microelectronic Test Structures
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-17H01712
  • [Presentation] Maximizing Energy Efficiency of on-Chip Caches Exploiting Hybrid Memory Structure2018

    • Author(s)
      Xu Hongjie、Shiomi Jun、Ishihara Tohru、Onodera Hidetoshi
    • Organizer
      The 28th International Symposium on Power and Timing Modeling, Optimization and Simulation
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-17H01712
  • [Presentation] 複数電源ドメインの実行時電圧制御によるCMOS LSIの消費エネルギー最小化2018

    • Author(s)
      塩見準,石原亨,小野寺秀俊
    • Organizer
      情報処理学会DAシンポジウム
    • Data Source
      KAKENHI-PROJECT-17H01712
  • [Presentation] セルベース設計に適合した基板バイアス制御用増幅回路の設計手法2018

    • Author(s)
      小柳卓也, 塩見準, 石原亨, 小野寺秀俊
    • Organizer
      情報処理学会DAシンポジウム
    • Data Source
      KAKENHI-PROJECT-17H01712
  • [Presentation] Effect of supply voltage on random telegraph noise of transistors under switching condition2017

    • Author(s)
      A.K.M. Mahfuzul Islam, Hidetoshi Onodera
    • Organizer
      2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H01713
  • [Presentation] トポロジー可変リングオシレータを用いた電圧感度の小さい動作温度モニタ2017

    • Author(s)
      岸本 真,石原亨,小野寺秀俊
    • Organizer
      情報処理学会DAシンポジウム
    • Data Source
      KAKENHI-PROJECT-17H01712
  • [Presentation] On-Chip Temperature and Process Variation Sensing using a Reconfigurable Ring Oscillator2017

    • Author(s)
      Tadashi Kishimoto, Tohru Ishihara, and Hidetoshi Onodera
    • Organizer
      2017 International Symposium on VLSI Design, Automation and Test
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H01713
  • [Presentation] リークエネルギーを最小化するP/N基板電圧の設定手法2017

    • Author(s)
      岡村陽介,石原亨,小野寺秀俊
    • Organizer
      情報処理学会DAシンポジウム
    • Data Source
      KAKENHI-PROJECT-17H01712
  • [Presentation] A Statistical Modeling Methodology of RTN Gate Size Dependency Based on Skewed Ring Oscillators2017

    • Author(s)
      A.K.M. Mahfuzul Islam, Tatsuya Nakai, Hidetoshi Onodera
    • Organizer
      2017 IEEE International Conference on Microelectronic Test Structures
    • Place of Presentation
      Grenoble(France)
    • Year and Date
      2017-03-27
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H01713
  • [Presentation] On-Chip Temperature and Process Variation Sensing using a Reconfigurable Ring Oscillator2017

    • Author(s)
      Tadashi Kishimoto, Tohru Ishihara, and Hidetoshi Onodera
    • Organizer
      International Symposium on VLSI Design, Automation and Test
    • Place of Presentation
      Shinchu, Taiwan
    • Year and Date
      2017-04-24
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-26280013
  • [Presentation] 最小エネルギー動作点追跡アルゴリズムの実チップ評価2017

    • Author(s)
      保木本 修, 塩見準,石原亨,小野寺秀俊
    • Organizer
      情報処理学会DAシンポジウム
    • Data Source
      KAKENHI-PROJECT-17H01712
  • [Presentation] A Statistical Modeling Methodology of RTN Gate Size Dependency Based on Skewed Ring Oscillators2017

    • Author(s)
      A.K.M. Mahfuzul Islam, Tatsuya Nakai, Hidetoshi Onodera
    • Organizer
      2017 IEEE International Conference on Microelectronic Test Structures
    • Place of Presentation
      Grenoble(France)
    • Year and Date
      2017-03-28
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-25280014
  • [Presentation] On-chip temperature and process variation sensing using a reconfigurable Ring Oscillator2017

    • Author(s)
      Kishimoto Tadashi、Ishihara Tohru、Onodera Hidetoshi
    • Organizer
      International Symposium on VLSI Design, Automation and Test
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-17H01712
  • [Presentation] アクセス頻度に応じた電圧調節によるオンチップメモリの消費エネルギー最小化2017

    • Author(s)
      塩見準,石原亨,小野寺秀俊
    • Organizer
      情報処理学会DAシンポジウム
    • Data Source
      KAKENHI-PROJECT-17H01712
  • [Presentation] A Temperature Monitor Circuit with Small Voltage Sensitivity using a Topology Reconfigurable Ring Oscillator2017

    • Author(s)
      Tadashi Kishimotoy, Tohru Ishiharay, and Hidetoshi Onodera
    • Organizer
      2017 International Conference on Solid State Devices and Materials
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H01713
  • [Presentation] Fully Digital On-Chip Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing2016

    • Author(s)
      Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
    • Organizer
      International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)
    • Place of Presentation
      Bremen(Germany)
    • Year and Date
      2016-09-21
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H01713
  • [Presentation] A Processor Architecture Integrating Voltage Scalable On-Chip Memories for Individual Tracking of Minimum Energy Points in Logic and Memory2016

    • Author(s)
      Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
    • Organizer
      The 20th Workshop on Synthesis And System Integration of Mixed Information technologies
    • Place of Presentation
      京都リサーチパーク、京都府京都市
    • Year and Date
      2016-09-24
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-26280013
  • [Presentation] A Closed-Form Stability Model for Cross-Coupled Inverters Operating in Sub-Threshold Voltage Region2016

    • Author(s)
      Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
    • Organizer
      21st Asia and South Pacific Design Automation Conference (ASP-DAC)
    • Place of Presentation
      Macao(China)
    • Year and Date
      2016-01-25
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-25280014
  • [Presentation] 広範囲な動作性能領域においてエネルギー最小点追跡を可能にするオンチップメモリ2016

    • Author(s)
      塩見準、石原亨、小野寺秀俊
    • Organizer
      情報処理学会DAシンポジウム
    • Place of Presentation
      山代温泉 ゆのくに天祥、石川県加賀市
    • Year and Date
      2016-09-14
    • Data Source
      KAKENHI-PROJECT-26280013
  • [Presentation] 回路トポロジー可変なリングオシレータを用いたプロセス変動量と動作温度の推定方法2016

    • Author(s)
      岸本真、石原亨、小野寺秀俊
    • Organizer
      情報処理学会DAシンポジウム
    • Place of Presentation
      山代温泉 ゆのくに天祥、石川県加賀市
    • Year and Date
      2016-09-14
    • Data Source
      KAKENHI-PROJECT-26280013
  • [Presentation] Minimum Energy Point Tracking Using Combined Dynamic Voltage Scaling and Adaptive Body Biasing2016

    • Author(s)
      Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera
    • Organizer
      IEEE International System-on-Chip Conference
    • Place of Presentation
      Seattle, USA
    • Year and Date
      2016-09-06
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-26280013
  • [Presentation] プロセッサにおける電源電圧と基板電圧の同時調節によるエネルギー最小点追跡手法2016

    • Author(s)
      保木本修、石原亨、小野寺秀俊
    • Organizer
      情報処理学会DAシンポジウム
    • Place of Presentation
      山代温泉 ゆのくに天祥、石川県加賀市
    • Year and Date
      2016-09-14
    • Data Source
      KAKENHI-PROJECT-26280013
  • [Presentation] A Closed-Form Stability Model for Cross-Coupled Inverters Operating in Sub-Threshold Voltage Region2016

    • Author(s)
      Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
    • Organizer
      Asia and South Pacific Design Automation Conference
    • Place of Presentation
      Sands Cotai, Macau
    • Year and Date
      2016-01-26
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-26280013
  • [Presentation] Minimum Energy Point Tracking under a Wide Range of PVT Conditions2016

    • Author(s)
      Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera
    • Organizer
      The 20th Workshop on Synthesis And System Integration of Mixed Information technologies
    • Place of Presentation
      京都リサーチパーク、京都府京都市
    • Year and Date
      2016-10-24
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-26280013
  • [Presentation] A Processor Architecture Integrating Voltage Scalable On-Chip Memories for Individual Tracking of Minimum Energy Points in Logic and Memory2016

    • Author(s)
      Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
    • Organizer
      The 20th Workshop on Synthesis And System Integration of Mixed Information technologies
    • Place of Presentation
      KRP(京都)
    • Year and Date
      2016-10-24
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H01713
  • [Presentation] Statistical Analysis and Modeling of Random Telegraph Noise Based on Gate Delay Variation Measurement2016

    • Author(s)
      A.K.M. Mahfuzul Islam, Tatsuya Nakai, and Hidetoshi Onodera
    • Organizer
      International Conference on Microelectronic Test Structures
    • Place of Presentation
      メルパルク横浜(神奈川県・横浜市)
    • Year and Date
      2016-03-28
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-25280014
  • [Presentation] Guidelines for Effective and Simplified Dynamic Supply and Threshold Voltage Scaling2016

    • Author(s)
      Toshihiro Takeshita, Tohru ISHIHARA, Hidetoshi Onodera
    • Organizer
      International Symposium on VLSI Design, Automation and Test
    • Place of Presentation
      Hsinchu, Taiwan
    • Year and Date
      2016-04-25
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-26280013
  • [Presentation] On-Chip Temperature Sensing using a Reconfigurable Ring Oscillator2016

    • Author(s)
      Tadashi Kishimoto, Hidetoshi Onodera
    • Organizer
      The 20th Workshop on Synthesis And System Integration of Mixed Information technologies
    • Place of Presentation
      KRP(京都)
    • Year and Date
      2016-10-24
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-16H01713
  • [Presentation] Fully Digital On-Chip Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing2016

    • Author(s)
      Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
    • Organizer
      International Workshop on Power and Timing Modeling, Optimization and Simulation
    • Place of Presentation
      Bremen, Germany
    • Year and Date
      2016-09-21
    • Invited / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-26280013
  • [Presentation] On-chip Monitoring and Compensation Scheme with Fine-grain Body Biasing for Robust and Energy-Efficient Operations2016

    • Author(s)
      A.K.M. Mahfuzul Islam and Hidetoshi Onodera
    • Organizer
      21st Asia and South Pacific Design Automation Conference (ASP-DAC)
    • Place of Presentation
      Macao(China)
    • Year and Date
      2016-01-25
    • Invited / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-25280014
  • [Presentation] CMOS LSIにおけるエネルギー最小点追跡のための電源電圧としきい値電圧の動的調節指針2016

    • Author(s)
      竹下俊宏, 塩見準,石原亨,小野寺秀俊
    • Organizer
      情報処理学会 システムLSI設計技術研究会 研究報告, 2016-SLDM-175(32)
    • Place of Presentation
      福江文化会館、長崎県福江市
    • Year and Date
      2016-03-24
    • Data Source
      KAKENHI-PROJECT-26280013
  • [Presentation] Variability- and Correlation-Aware Logical Effort for Near-Threshold Circuit Design2016

    • Author(s)
      Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
    • Organizer
      International Symposium on Quality Electronic Design
    • Place of Presentation
      Santa Clara, California, USA
    • Year and Date
      2016-03-15
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-26280013
  • [Presentation] 電源電圧としきい値電圧の同時最適化が集積回路の消費エネルギーに与える影響の解析2015

    • Author(s)
      竹下俊宏、西澤真一、Islam AKM Mahfuzul、石原 亨、小野寺秀俊
    • Organizer
      電子情報通信学会VLSI設計技術研究会
    • Place of Presentation
      慶應義塾大学日吉キャンパス来往舎、神奈川県横浜市
    • Year and Date
      2015-01-29
    • Data Source
      KAKENHI-PROJECT-26280013
  • [Presentation] Dependable VLSI Platform with Variability and Soft-Error Resilience2015

    • Author(s)
      Hidetoshi Onodera
    • Organizer
      International Conference on Integrated Circutis, Design, and Verification
    • Place of Presentation
      Ho Chi Minh City(Vietnam)
    • Year and Date
      2015-08-10
    • Invited / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-25280014
  • [Presentation] An impact of process variation on supply voltage dependence of logic path delay variation2015

    • Author(s)
      S. Nishizawa, T. Ishihara, H. Onodera
    • Organizer
      International Symposium on VLSI Design, Automation and Test
    • Place of Presentation
      Hsinchu, Taiwan
    • Year and Date
      2015-04-27
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-26280013
  • [Presentation] Slew- and Variability-Aware Logical Effort for Near-Threshold Circuit Design2015

    • Author(s)
      Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
    • Organizer
      International Workshop on Variability Modeling and Characterization
    • Place of Presentation
      San Jose, California, USA
    • Year and Date
      2015-11-05
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-26280013
  • [Presentation] Design Challenges and Solutions in the era of IoT2015

    • Author(s)
      Hidetoshi Onodera
    • Organizer
      IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
    • Place of Presentation
      Daejeon(Korea)
    • Year and Date
      2015-10-05
    • Invited / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-25280014
  • [Presentation] An impact of process variation on supply voltage dependence of logic path delay variation2015

    • Author(s)
      S. Nishizawa, T. Ishihara, H. Onodera
    • Organizer
      International Symposium on VLSI Design, Automation and Test
    • Place of Presentation
      Hsinchu(Taiwan)
    • Year and Date
      2015-04-27
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-25280014
  • [Presentation] Energy-Efficient Computing with Algorithm Embedded Hardware2015

    • Author(s)
      Hidetoshi Onodera
    • Organizer
      International Workshop on Cross-Layer Resilience
    • Place of Presentation
      Munich(Germany)
    • Year and Date
      2015-07-20
    • Invited / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-25280014
  • [Presentation] 統計的タイミングモデルに基づくニアスレッショルド回路のゲートサイジング2015

    • Author(s)
      塩見準,石原亨,小野寺秀俊
    • Organizer
      情報処理学会DAシンポジウム2015
    • Place of Presentation
      温泉ゆのくに天祥、石川県加賀市
    • Year and Date
      2015-08-26
    • Data Source
      KAKENHI-PROJECT-26280013
  • [Presentation] サブスレッショルド領域におけるラッチ回路の動作安定性モデル2015

    • Author(s)
      鎌苅竜也,塩見準,石原亨,小野寺秀俊
    • Organizer
      情報処理学会DAシンポジウム2015
    • Place of Presentation
      温泉ゆのくに天祥、石川県加賀市
    • Year and Date
      2015-08-26
    • Data Source
      KAKENHI-PROJECT-26280013
  • [Presentation] In-Situ Variability Characterization of Individual Transistors Using Topology-Reconfigurable Ring Oscillators2014

    • Author(s)
      A.K.M. Mahfuzul Islam, and Hidetoshi Onodera
    • Organizer
      International Conference on Microelectronic Test Structures
    • Place of Presentation
      Udine, Italy
    • Data Source
      KAKENHI-PROJECT-25280014
  • [Presentation] Variation Tolerant Design of D-Flip-Flops for Low Voltage Circuit Operation2014

    • Author(s)
      Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
    • Organizer
      International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)
    • Place of Presentation
      Santa Cruz, CA, USA
    • Data Source
      KAKENHI-PROJECT-25280014
  • [Presentation] Computer Simulation of Radiation-Induced Clock-Perturbation in Phase-Locked Loop with Analog Behavioral Model2014

    • Author(s)
      Tomohiro Fujita, SinNyoung Kim, and Hidetoshi Onodera
    • Organizer
      International Symposium on Quality Electronic Design(ISQED)
    • Place of Presentation
      Santa Clara, CA, USA
    • Data Source
      KAKENHI-PROJECT-25280014
  • [Presentation] A Lognormal Timing Model and Design Guidelines for Near-Threshold Circuits2014

    • Author(s)
      Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
    • Organizer
      International Workshop on Variability Modeling and Charactorization
    • Place of Presentation
      San Jose, California, USA
    • Year and Date
      2014-11-06
    • Data Source
      KAKENHI-PROJECT-26280013
  • [Presentation] Cell-based Physical Design Automation for Analog and Mixed Signal Application2014

    • Author(s)
      Norihiro Kamae, Islam A.K.M Mahfuzul, Akira Tsuchiya, Hidetoshi Onodera
    • Organizer
      International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)
    • Place of Presentation
      Santa Cruz, CA, USA
    • Data Source
      KAKENHI-PROJECT-25280014
  • [Presentation] Reconfigurable Delay Cell for Area-efficient Implementation of On-chip MOSFET Monitor Schemes2013

    • Author(s)
      A.K.M. Mahfuzul Islam, Tohru Ishihara, and Hidetoshi Onodera
    • Organizer
      IEEE Asian Solid State Circuits Conference
    • Place of Presentation
      Singapore
    • Data Source
      KAKENHI-PROJECT-25280014
  • [Presentation] Area-efficient Reconfigurable Ring Oscillator for Characterization of Static and Dynamic Variations2013

    • Author(s)
      A.K.M. Mahfuzul Islam, and Hidetoshi Onodera
    • Organizer
      International Conference on Solid State Devices and Materials
    • Place of Presentation
      Fukuoka
    • Data Source
      KAKENHI-PROJECT-25280014
  • [Presentation] A Body Bias Generator Compatible with Cell-based Design Flow for Within-die Variability Compensation2012

    • Author(s)
      Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera
    • Organizer
      IEEE Asian Solid-State Circuits Conference
    • Place of Presentation
      神戸
    • Year and Date
      2012-11-14
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] A Built-in Self-adjustment Scheme with Adaptive Body Bias using P/N-sensitive Digital Monitor Circuits2012

    • Author(s)
      Islam A.K.M Mahfuzul, Norihiro Kamae, Tohru Ishihara, and Hidetoshi Onodera
    • Organizer
      IEEE Asian Solid-State Circuits Conference
    • Place of Presentation
      神戸
    • Year and Date
      2012-11-13
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] Inhomogenious Ring Oscillator for WID Variability and RTN Characterization2012

    • Author(s)
      Shuichi Fujimoto, Takashi Matsumoto Hidetoshi Onodera
    • Organizer
      International Conference on Microelectronic Test structures
    • Place of Presentation
      San Diego(アメリカ合衆国)
    • Year and Date
      2012-03-20
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] Japan Science and Technology Agency (JST) program on Dependable VLSI Platform project2012

    • Author(s)
      Hidetoshi Onodera
    • Organizer
      Design, Automation & Test in Europe
    • Place of Presentation
      Dresden(ドイツ)(Invited)
    • Year and Date
      2012-03-16
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] Ring Oscillator with Calibration Circuit for Accurate On-Chip IR-drop Measurement2012

    • Author(s)
      Shinichi Nishizawa, Hidetoshi Onodera
    • Organizer
      International Conference on Microelectronic Test Structures
    • Place of Presentation
      San Diego(アメリカ合衆国)
    • Year and Date
      2012-03-20
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] ロバストファブリックを用いたディペンダブルVLSIプラットフォーム2011

    • Author(s)
      小野寺秀俊
    • Organizer
      LSIとシステムのワークショップ2011
    • Place of Presentation
      小倉(招待講演)
    • Year and Date
      2011-05-17
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] Moore Mooreに立ちはだかるCMOSばらつきの理解に向けて2011

    • Author(s)
      小野寺秀俊
    • Organizer
      電子情報通信学会VLSI設計技術研究会
    • Place of Presentation
      那覇(招待講演)
    • Year and Date
      2011-03-02
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] ランダム・テレグラフ・ノイズに起因したディジタル回路遅延ゆらぎについて2011

    • Author(s)
      松本高士, 伊東恭佑, 小林和淑, 小野寺秀俊
    • Organizer
      DAシンポジウム
    • Place of Presentation
      下呂市
    • Year and Date
      2011-08-31
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] Impact of RTN and NBTI on Synchorous Circuit Reliability2011

    • Author(s)
      Takashi Matsumoto, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Organizer
      IEEE/ACM Workshop on Variability Modeling and Characterization
    • Place of Presentation
      San Jose(アメリカ合衆国)
    • Year and Date
      2011-11-10
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] ディジタル回路遅延の経年劣化とそのモデル化について2011

    • Author(s)
      松本高士, 小林和淑, 小野寺秀俊
    • Organizer
      電子情報通信学会基礎・境界ソサイエティ大会
    • Place of Presentation
      札幌
    • Year and Date
      2011-09-13
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] Reconfigurable Array-Based Area-Efficient Test Structure for Standard Cell Characterization2011

    • Author(s)
      Bishnu Prasad Das, Hidetoshi Onodera
    • Organizer
      2011 International Workshop on RTL and Higl Level Testing
    • Place of Presentation
      Jaipur(インド)
    • Year and Date
      2011-11-26
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] Dependable VLSI Program in Japan--Program Overview and the Current status of Dependable VLSI Platform Project--2011

    • Author(s)
      Hidetoshi Onodera
    • Organizer
      2011 Asian Test Symposium
    • Place of Presentation
      New Delhi(インド)(Invited)
    • Year and Date
      2011-11-22
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] An Area Effective Forward/Reverse Body Bias Generator for Within-Die Variability Compensation2011

    • Author(s)
      Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera
    • Organizer
      2011 IEEE Asian Solid-State Circuits Conference
    • Place of Presentation
      Jeju(大韓民国)
    • Year and Date
      2011-11-16
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] NBTI回復現象を利用したマルチコアLSIの自己特性補償法2011

    • Author(s)
      松本高士, 牧野紘明, 小林和淑, 小野寺秀俊
    • Organizer
      電子情報通信学会技術報告(集積回路設計)
    • Place of Presentation
      宮崎
    • Year and Date
      2011-11-29
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] Variation-sensitive Monitor Circuits for Estimation of Die-to-Die Process Variation2011

    • Author(s)
      Islam A.K.M Mahfuzul, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Organizer
      2011 IEEE International Conference on Microelectronic Test structure
    • Place of Presentation
      Amsterdam(オランダ)
    • Year and Date
      2011-04-06
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] トランジスタレベルでの経年劣化補償技術におけるNBTI回復特性の利用について2011

    • Author(s)
      松本高士、牧野裕明、小林和淑、小野寺秀俊
    • Organizer
      LSIとシステムのワークショップ2011
    • Place of Presentation
      小倉
    • Year and Date
      2011-05-18
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] トランジスタレベルでの経年劣化補償技術におけるNBTI回復特性の利用について2011

    • Author(s)
      松本高士, 牧野紘明, 小林和淑, 小野寺秀俊
    • Organizer
      システムLSIワークショップ
    • Place of Presentation
      北九州市
    • Year and Date
      2011-05-17
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] The Impact of RTN on Performance Flucuation in CMOS Logic Circuits2011

    • Author(s)
      Kyosuke Ito, Takahi Matsumoto, Shinichi Nishizawa, Hiroki Sunagawa, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Organizer
      2011 IEEE International Reliability Physics Symposium
    • Place of Presentation
      Monterey(アメリカ合衆国)
    • Year and Date
      2011-04-13
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] Modeling of Random Telegraph Noise under Circuit Operation-Simulation and Measurement of RTN-induced delay fluctuation-2011

    • Author(s)
      Kyosuke Ito, Takashi Matsumoto, Shinichi Nishizawa, Hiroki Sunagawa, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Organizer
      2011 International Symposium on Quality Electronic Design (ISQED)
    • Place of Presentation
      Santa Clara(アメリカ合衆国)
    • Year and Date
      2011-03-15
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] Multi-core LSI Lifetime Extension by NBTI-Recovery-bases Self-healing2011

    • Author(s)
      Takashi Matsumoto, Hiroaki Makino, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Organizer
      International Conference on Solid state Devices and Materials
    • Place of Presentation
      名古屋
    • Year and Date
      2011-09-29
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] パッケージとの接続抵抗を考慮したチップ内電源ネットワークの構成手法2011

    • Author(s)
      西澤真一, 小林和淑, 小野寺秀俊
    • Organizer
      DAシンポジウム
    • Place of Presentation
      下呂市
    • Year and Date
      2011-08-31
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] Variability Characterization Using an RO-array Test Structure2010

    • Author(s)
      Shinichi Nishizawa, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Organizer
      4th IEEE International Workshop on Design for Manufacturability & Yield
    • Place of Presentation
      Anaheim(アメリカ合衆国)
    • Year and Date
      2010-06-14
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] D-FlipFlop Design for Enhanced Tolerance to Within-Die Variation2010

    • Author(s)
      Hidetoshi Onodera, Hiroki Sunagawa
    • Organizer
      4th IEEE International Workshop on Design for Manufacturability & Yield
    • Place of Presentation
      Anaheim(アメリカ合衆国)
    • Year and Date
      2010-06-14
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] 組み合わせ回路におけるランダム・テレグラフ・ノイズの影響の評価2010

    • Author(s)
      伊東恭佑、松本高士、小林和淑、小野寺秀俊
    • Organizer
      DAシンポジウム2010
    • Place of Presentation
      豊橋
    • Year and Date
      2010-09-03
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] 基板電圧の制御回路とその面積オーバヘッド2010

    • Author(s)
      釜江典裕、土谷亮、小野寺秀俊
    • Organizer
      2010年電子情報通信学会ソサイエティ大会
    • Place of Presentation
      堺
    • Year and Date
      2010-09-16
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] A 65nm CMOS 400ns Measurement Delay NBTI-Recovery Sensor by Minimum Assist Circuit2010

    • Author(s)
      Takashi Matsumoto, Hiroaki Makino, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Organizer
      International Conference on Solid State Devices and Materials (SSDM 2010)
    • Place of Presentation
      東京
    • Year and Date
      2010-09-23
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] Extraction of Variability Sources from Within-die Random Delay Variation2010

    • Author(s)
      Shuichi Fujimoto, Islam A.K.M Mahfuzul, Shinichi Nishizawa, Hidetoshi Onodera
    • Organizer
      4th IEEE International Workshop on Design for Manufacturability & Yield
    • Place of Presentation
      Anaheim(アメリカ合衆国)
    • Year and Date
      2010-06-14
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] Variation-Tolerant Design of D FlipFlops2010

    • Author(s)
      Hiroki Sunagawa, Hidetoshi Onodera
    • Organizer
      IEEE International SOC Conference 2010
    • Place of Presentation
      Las Vegas(アメリカ合衆国)
    • Year and Date
      2010-09-28
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] バッファチェインにおけるパルス幅縮小現象を利用したSETパルス幅測定回路2010

    • Author(s)
      古田潤、小林和淑、小野寺秀俊
    • Organizer
      DAシンポジウム2010
    • Place of Presentation
      豊橋
    • Year and Date
      2010-09-03
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] Process-sensitive Monitor Circuits for Estimation of Die-to-Die Process Variability2010

    • Author(s)
      A.K.M. Mahfuzul Islam, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Organizer
      TAU Workshop 2010
    • Place of Presentation
      San Francisco
    • Year and Date
      2010-03-18
    • Data Source
      KAKENHI-PROJECT-19300010
  • [Presentation] Warning Prediction Sequential for Transient Error Prevention2010

    • Author(s)
      Bishnu Prasad Das, Hidetoshi Onodera
    • Organizer
      2010 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
    • Place of Presentation
      京都
    • Year and Date
      2010-10-08
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] レイアウト制約が性能と製造性に与える影響2010

    • Author(s)
      北島和彦、砂川洋輝、土谷亮、小野寺秀俊
    • Organizer
      DAシンポジウム2010
    • Place of Presentation
      豊橋
    • Year and Date
      2010-09-03
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] チップ内ばらつきの成分解析手法2010

    • Author(s)
      藤本秀一、Islam A.K.M.Mahfuzul、西澤真一、小野寺秀俊
    • Organizer
      DAシンポジウム2010
    • Place of Presentation
      豊橋
    • Year and Date
      2010-09-03
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] Modeling of Random Telegraph Noise under Circuit Operation-Simulation and Measurement of RTN-induced Delay Fluctuation2010

    • Author(s)
      Kyosuke Ito, Takashi Matsumoto, Shinichi Nishizawa, Hiroki Sunagawa, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Organizer
      Workshop on variability modeling and characterization (VMC)
    • Place of Presentation
      San Jose, CA(アメリカ合衆国)
    • Year and Date
      2010-11-11
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] Characterization of WID Delay Variability Using RO-array Test Structures2009

    • Author(s)
      Hidetoshi Onodera, Haruhiko Terada
    • Organizer
      Proceedings 2009 8th IEEE International Conference on ASIC
    • Place of Presentation
      Changsha
    • Year and Date
      2009-10-21
    • Data Source
      KAKENHI-PROJECT-19300010
  • [Presentation] Characterization of WID Delay Variability Using RO-array Test Structures2009

    • Author(s)
      Hidetoshi Onodera, Haruhiko Terada
    • Organizer
      2009 8th IEEE International Conference on ASIC
    • Place of Presentation
      Changsha, China
    • Year and Date
      2009-10-19
    • Data Source
      KAKENHI-PROJECT-19300010
  • [Presentation] Variability Modeling and Impact on Design2008

    • Author(s)
      Hidetoshi Onodera
    • Organizer
      2008 International Electron Devices Meeting
    • Place of Presentation
      サンフランシスコ
    • Year and Date
      2008-12-17
    • Data Source
      KAKENHI-PROJECT-19300010
  • [Presentation] Statistical Gate Delay Model for Multiple Input Switching2008

    • Author(s)
      Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera
    • Organizer
      The 13th Asia and South Pacific Design Automation Conference
    • Place of Presentation
      Seoul, Korea
    • Year and Date
      2008-01-23
    • Data Source
      KAKENHI-PROJECT-19300010
  • [Presentation] Toward Variability-Aware Design2007

    • Author(s)
      Hidetoshi Onodera
    • Organizer
      2007 Symposium on VLSI Technology
    • Place of Presentation
      Kyoto, Japan
    • Year and Date
      2007-06-13
    • Data Source
      KAKENHI-PROJECT-19300010
  • [Presentation] Regularity-Enhanced Layout of Standard Cells2007

    • Author(s)
      Hidetoshi Onodera, Hiroaki Muta
    • Organizer
      2nd IEEE International Workshop on Design for Manufacturability and Yield
    • Place of Presentation
      Santa Clara, CA
    • Year and Date
      2007-10-25
    • Data Source
      KAKENHI-PROJECT-19300010
  • [Presentation] 統計的遅延解析における遅延分布間の最大値計算手法2007

    • Author(s)
      寺田 晴彦, 福岡 孝之, 土谷 亮, 小野寺 秀俊
    • Organizer
      DAシンポジウム2007
    • Place of Presentation
      浜松
    • Year and Date
      2007-08-29
    • Data Source
      KAKENHI-PROJECT-19300010
  • [Presentation] 同時スイッチングの影響を考慮した統計的遅延解析2007

    • Author(s)
      福岡 孝之, 土谷 亮, 小野寺 秀俊
    • Organizer
      DAシンポジウム2007
    • Place of Presentation
      浜松
    • Year and Date
      2007-08-29
    • Data Source
      KAKENHI-PROJECT-19300010
  • [Presentation] Microarchitectural-Level Statistical Timing Models for Near-Threshold Circuit Design

    • Author(s)
      Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
    • Organizer
      20th Asia and South Pacific Design Automation Conference
    • Place of Presentation
      幕張メッセ、千葉県千葉市
    • Year and Date
      2015-01-19 – 2015-01-22
    • Data Source
      KAKENHI-PROJECT-26280013
  • [Presentation] ニアスレッショルド回路設計のための基本定理

    • Author(s)
      塩見準,石原亨,小野寺秀俊
    • Organizer
      電子情報通信学会VLSI設計技術研究会
    • Place of Presentation
      沖縄県青年会館、沖縄県那覇市
    • Year and Date
      2015-03-02 – 2015-03-04
    • Data Source
      KAKENHI-PROJECT-26280013
  • [Presentation] Dependable VLSI Platform using Robust Fabrics

    • Author(s)
      Hidetoshi Onodera
    • Organizer
      18th Asia and South Pacific Design Automation Conference (ASP-DAC) 2013
    • Place of Presentation
      Yokohama
    • Invited
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] Characterization and compensation of performance variability using on-chip monitors

    • Author(s)
      A.K.M. Mahfuzul Islam, and Hidetoshi Onodera
    • Organizer
      2014 International Symposium on VLSI Design, Automation and Test
    • Place of Presentation
      Hsinchu, Taiwan
    • Year and Date
      2014-04-28 – 2014-04-30
    • Invited
    • Data Source
      KAKENHI-PROJECT-25280014
  • [Presentation] 電源電圧に応じてトランジスタサイズを最適化可能なセルライブラリの生成システム

    • Author(s)
      西澤真一, 石原 亨, 小野寺秀俊
    • Organizer
      情報処理学会DAシンポジウム2014
    • Place of Presentation
      ホテル下呂温泉水明館、岐阜県下呂市
    • Year and Date
      2014-08-28 – 2014-08-29
    • Data Source
      KAKENHI-PROJECT-26280013
  • [Presentation] Energy Reduction by Built-in Body Biasing with Single Supply Voltage Operation

    • Author(s)
      Norihiro Kamae, Akira Tsuchiya, Tohru Ishihara, Hidetoshi Onodera
    • Organizer
      International Symposium on Quality Electronic Design
    • Place of Presentation
      San Jose, California, USA
    • Year and Date
      2015-03-03 – 2015-03-04
    • Data Source
      KAKENHI-PROJECT-26280013
  • [Presentation] PLLの物理レイアウト自動生成を目指した設計手法

    • Author(s)
      釡江 典裕, 土谷 亮, 石原 亨, 小野寺 秀俊
    • Organizer
      情報処理学会DAシンポジウム2014
    • Place of Presentation
      ホテル下呂温泉水明館、岐阜県下呂市
    • Year and Date
      2014-08-28 – 2014-08-29
    • Data Source
      KAKENHI-PROJECT-26280013
  • [Presentation] Sensitivity-independent Extraction of Vth Variation Utilizing Log-normal Delay Distribution

    • Author(s)
      A.K.M.Mahfuzul Islam, Hidetoshi Onodera
    • Organizer
      2015 IEEE International Conference on Microelectronic Test Structures
    • Place of Presentation
      Phoenix, AZ, USA
    • Year and Date
      2015-03-24 – 2015-03-26
    • Data Source
      KAKENHI-PROJECT-25280014
  • [Presentation] Design Methodology of Process Variation Tolerant D-Flip-Flops for Low Voltage Circuit Operation

    • Author(s)
      Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
    • Organizer
      IEEE International System-On-Chip Conference
    • Place of Presentation
      Las Vegas, Nevada, USA
    • Year and Date
      2014-09-02 – 2014-09-05
    • Data Source
      KAKENHI-PROJECT-25280014
  • [Presentation] 製造ばらつきを考慮した極低電圧動作向けフリップフロップの設計手法

    • Author(s)
      鎌苅竜也,西澤真一,石原亨,小野寺秀俊
    • Organizer
      情報処理学会DAシンポジウム2014
    • Place of Presentation
      ホテル下呂温泉水明館、岐阜県下呂市
    • Year and Date
      2014-08-28 – 2014-08-29
    • Data Source
      KAKENHI-PROJECT-26280013
  • [Presentation] Design Methodology of Process Variation Tolerant D-Flip-Flops for Low Voltage Circuit Operation

    • Author(s)
      Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
    • Organizer
      IEEE International System-On-Chip Conference
    • Place of Presentation
      Las Vegas, Nevada, USA
    • Year and Date
      2014-09-02 – 2014-09-05
    • Data Source
      KAKENHI-PROJECT-26280013
  • [Presentation] Variation-Aware Flip-Flop Energy Optimization for Ultra Low Voltage Operation

    • Author(s)
      Tatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
    • Organizer
      IEEE International System-On-Chip Conference
    • Place of Presentation
      Las Vegas, Nevada, USA
    • Year and Date
      2014-09-02 – 2014-09-05
    • Data Source
      KAKENHI-PROJECT-25280014
  • [Presentation] Variation-Aware Flip-Flop Energy Optimization for Ultra Low Voltage Operation

    • Author(s)
      Tatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
    • Organizer
      IEEE International System-On-Chip Conference
    • Place of Presentation
      Las Vegas, Nevada, USA
    • Year and Date
      2014-09-02 – 2014-09-05
    • Data Source
      KAKENHI-PROJECT-26280013
  • 1.  KOBAYASHI Kazutoshi (70252476)
    # of Collaborated Projects: 14 results
    # of Collaborated Products: 23 results
  • 2.  TAMARU Keikichi (10127102)
    # of Collaborated Projects: 13 results
    # of Collaborated Products: 0 results
  • 3.  YASUURA Hiroto (80135540)
    # of Collaborated Projects: 9 results
    # of Collaborated Products: 0 results
  • 4.  MOSHNYAGA Vasily (40243050)
    # of Collaborated Projects: 8 results
    # of Collaborated Products: 0 results
  • 5.  TSUCHIYA Akira (20432411)
    # of Collaborated Projects: 5 results
    # of Collaborated Products: 18 results
  • 6.  Ishihara Tohru (30323471)
    # of Collaborated Projects: 4 results
    # of Collaborated Products: 60 results
  • 7.  NAKAJIMA Masamitsu (60025939)
    # of Collaborated Projects: 3 results
    # of Collaborated Products: 0 results
  • 8.  SATOH Masao (30170781)
    # of Collaborated Projects: 3 results
    # of Collaborated Products: 0 results
  • 9.  HASHIMOTO Masanori (80335207)
    # of Collaborated Projects: 3 results
    # of Collaborated Products: 7 results
  • 10.  MURAKAMI Kazuaki (10200263)
    # of Collaborated Projects: 3 results
    # of Collaborated Products: 0 results
  • 11.  YAMAZAKI Katsuhiro (70134260)
    # of Collaborated Projects: 3 results
    # of Collaborated Products: 0 results
  • 12.  UESAKA T (30213333)
    # of Collaborated Projects: 2 results
    # of Collaborated Products: 0 results
  • 13.  IWAIHARA Mizuho (40253538)
    # of Collaborated Projects: 2 results
    # of Collaborated Products: 0 results
  • 14.  SUEHOSHI Toshinori (00117136)
    # of Collaborated Projects: 2 results
    # of Collaborated Products: 0 results
  • 15.  TSURUTA Naoyuki (60227478)
    # of Collaborated Projects: 2 results
    # of Collaborated Products: 0 results
  • 16.  KANBARA Hiroyuki
    # of Collaborated Projects: 2 results
    # of Collaborated Products: 0 results
  • 17.  NISHIZAWA Sinichi (40757522)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 4 results
  • 18.  HAMAGUCHI Seiji (80238055)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 19.  SHUDO Kosho (70078632)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 20.  SUETSUGU Tadashi (60279255)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 21.  UMEDA Hiroyuki (40020218)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 22.  Mahfuzul Islam A. K. M. (80762195)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 9 results
  • 23.  末田 正 (20029408)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 24.  北野 正雄 (70115830)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 25.  塩見 準 (40809795)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 6 results
  • 26.  増田 豊 (60845527)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 27.  SHINPO Shintaro
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 28.  YOSHIDA Toyohiko
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 29.  MATSUZAWA Akira
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 30.  寺井 正幸
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 31.  TERAI M
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results

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