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Hamaguchi Kiyoharu  浜口 清治

ORCIDConnect your ORCID iD *help
… Alternative Names

浜口 清治  ハマグチ キヨハル

HAMAGUCHI Kiyoharu  浜口 清治

濱口 清治  ハマグチ キヨハル

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Researcher Number 80238055
Other IDs
External Links
Affiliation (Current) 2025: 京都橘大学, 工学部, 教授
Affiliation (based on the past Project Information) *help 2022 – 2023: 京都橘大学, 工学部, 教授
2018 – 2020: 島根大学, 学術研究院理工学系, 教授
2012 – 2015: 島根大学, 総合理工学研究科(研究院), 教授
2012: 島根大学, 総合理工学研究科, 教授
2007 – 2011: Osaka University, 大学院・情報科学研究科, 准教授 … More
2006: Osaka University, Gradusate School of Information Science and Technology, Associate Professor, 大学院情報科学研究科, 助教授
2006: 大阪大学, 情報科学研究科, 助教授
2004 – 2005: 大阪大学, 大学院・情報科学研究科, 助教授
2002: 大阪大学, 大学院・情報科学研究科, 助教授
2001: 大阪大学, 大学院・基礎工学研究科, 助教授
1999: 大阪大学, 基礎工学研究科, 助教授
1998: 大阪大学, 基礎工学研究科, 講師
1996: Osaka University, Feculty of Engineering Science, Lecturer, 基礎工学部, 講師
1995: 京都大学, 工学研究科, 講師
1994: Kyoto University, Faculty of Engineering, Lecturer, 工学部, 講師
1992 – 1993: Kyoto University, Faculty of Engineering, Instructor, 工学部, 助手 Less
Review Section/Research Field
Principal Investigator
計算機科学 / Computer system/Network / Basic Section 60040:Computer system-related / Computer system
Except Principal Investigator
計算機科学 / 情報工学
Keywords
Principal Investigator
第一階述語論理 / カバレッジ駆動検証 / SATソルバ / フォーマル検証 / 形式的設計検証 / 二分決定グラフ / 時相論理 / 機械学習 / シミュレーションベース検証 / 高位ハードウェア検証 … More / 設計検証 / 設計自動化 / Satisfiability Checking / High-Level Hardware Verification / First-Order Logic / Formal Verification / 第一階術後論理 / 充足可能性判定 / フォーマル検証技術 / ベイジアンネットワーク / カバレッジ駆動型検証 / シミュレーション検証 / アサーションベース検証 / 制約付きランダムパタン生成 / 有界モデル検査 / SAT ソルバ / 設計検証技術 / 高位ハードウェア設計 / モデル検査 / 第1階述語論理 / 協調設計 / 記号シミュレーション / 高位設計検証 / SW協調検証 / HW / 順序機械 / 機能レベル検証 / 機能レベル設計 / 等式論理 / 論理関致処理 / オートマトンの最小化 / 有限状態機械 / 仕様記述 / モデルチェッキング / 形式的検証 / マイクロプロセッサ / 論理設計 … More
Except Principal Investigator
論理関数処理 / 二分決定グラフ / 時相論理 / モデルチェッキング / Binary Decision Diagram / 形式的設計検証 / FPGA / KUE-CHIP2 / KITE / QP-DLX / temporal logic / 論理設計支援 / 順序回路 / binary decision diagram / logic function manipulation / model checking / First-order Predicate logic / Function level design / Formal design verification / 算術演算回路検証 / 機能レベル検証 / 三分決定グラフ / 二分モーメントグラフ / 調理関数処理 / マイクロプロセッサ / 第一階述語論理 / 機能レベル設計 / Model Checking / Formal Specification / Logic Function Manipulation / Formal Verification / Logic Design / Temporal Logic / 形式的論理設計検証 / 論理開数処理 / 仕様記述 / 形式的検証 / 論理設計 / Combinatorial Problem / Content Addressable Memory / Computational Complexity / Prallel Algorithm / Computer Aided Logic Design / Boolean Function Manipulation / Boolean Function / 組合せ問題 / 内容アドレスメモリ / 計算複雑さ / 並列アルゴリズム / 論理関数 / CAD Benchmark / Education-purpose Microprosessor / VLSI Engineering / Computer Engineering Education / VLSI / 集積回路工学教育 / プロトタイプ / CADベンチマ-ク / CADベンチマーク / 教育用マイクロプロセッサ / 集積回路工学 / 計算機工学教育 / computer-aided logic design / state assignment / logic function optimization / sequential circuits / logic design verification / logic synthesis / 状態割当て / 論理関数簡単化 / 論理設計検証 / 論理合成 Less
  • Research Projects

    (16 results)
  • Research Products

    (17 results)
  • Co-Researchers

    (11 People)
  •  入出力プロトコルに着目した機械学習によるカバレッジ駆動検証システムに関する研究Principal Investigator

    • Principal Investigator
      浜口 清治
    • Project Period (FY)
      2022 – 2024
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Review Section
      Basic Section 60040:Computer system-related
    • Research Institution
      Kyoto Tachibana University
  •  Study on Automated Design Verification Combining a SAT-based Method and a Machine Learning TechniquePrincipal Investigator

    • Principal Investigator
      Hamaguchi Kiyoharu
    • Project Period (FY)
      2018 – 2020
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Review Section
      Basic Section 60040:Computer system-related
    • Research Institution
      Shimane University
  •  Improving Coverage Driven Verification for Hardware Using Machine LearningPrincipal Investigator

    • Principal Investigator
      Hamaguchi Kiyoharu
    • Project Period (FY)
      2013 – 2015
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Research Field
      Computer system
    • Research Institution
      Shimane University
  •  Improving Hardware Verification Efficiency by Fusion of Formal Methods and SimulationPrincipal Investigator

    • Principal Investigator
      HAMAGUCHI Kiyoharu
    • Project Period (FY)
      2010 – 2012
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Research Field
      Computer system/Network
    • Research Institution
      Shimane University
      Osaka University
  •  Study on Model Checking for High-Level Hardware Design DescriptionsPrincipal Investigator

    • Principal Investigator
      HAMAGUCHI Kiyoharu
    • Project Period (FY)
      2007 – 2009
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Research Field
      Computer system/Network
    • Research Institution
      Osaka University
  •  Research on Equivalence Checking for High-Level Hardware Design DescriptionsPrincipal Investigator

    • Principal Investigator
      HAMAGUCHI Kiyoharu
    • Project Period (FY)
      2004 – 2006
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Research Field
      Computer system/Network
    • Research Institution
      Osaka University
  •  動作レベルおよびレジスタ転送レベルのハードウェア記述に対する形式的検証手法の研究Principal Investigator

    • Principal Investigator
      濱口 清治
    • Project Period (FY)
      2001 – 2002
    • Research Category
      Grant-in-Aid for Young Scientists (B)
    • Research Field
      計算機科学
    • Research Institution
      Osaka University
  •  ハードウェアの機能レベル設計に対する形式的検証手法に関する研究Principal Investigator

    • Principal Investigator
      濱口 清治
    • Project Period (FY)
      1998 – 1999
    • Research Category
      Grant-in-Aid for Encouragement of Young Scientists (A)
    • Research Field
      計算機科学
    • Research Institution
      Osaka University
  •  等式論理による機能レベル設計の形式的検証に関する研究Principal Investigator

    • Principal Investigator
      濱口 清治
    • Project Period (FY)
      1996
    • Research Category
      Grant-in-Aid for Encouragement of Young Scientists (A)
    • Research Field
      計算機科学
    • Research Institution
      Osaka University
  •  規則性を持つ大規模な有限状態機械の形式的設計検証に関する研究Principal Investigator

    • Principal Investigator
      濱口 清治
    • Project Period (FY)
      1995
    • Research Category
      Grant-in-Aid for Encouragement of Young Scientists (A)
    • Research Field
      計算機科学
    • Research Institution
      Kyoto University
  •  Research on Development of Formal Logic Design Verifier for Microprocessors

    • Principal Investigator
      YAJIMA Shuzo
    • Project Period (FY)
      1995 – 1996
    • Research Category
      Grant-in-Aid for Scientific Research (A)
    • Research Field
      計算機科学
    • Research Institution
      KYOTO UNIVERSITY
  •  マイクロプロセッサの形式的仕様記述・検証に関する研究Principal Investigator

    • Principal Investigator
      濱口 清治
    • Project Period (FY)
      1994
    • Research Category
      Grant-in-Aid for Encouragement of Young Scientists (A)
    • Research Field
      計算機科学
    • Research Institution
      Kyoto University
  •  Basic Research on High-Speed Boolean Function Manipulator

    • Principal Investigator
      YAJIMA Shuzo
    • Project Period (FY)
      1993 – 1994
    • Research Category
      Grant-in-Aid for General Scientific Research (B)
    • Research Field
      計算機科学
    • Research Institution
      KYOTO UNIVERSITY
  •  Research on Formal Verifier of Logic Design Based on Temporal Logic

    • Principal Investigator
      YAJIMA Shuzo
    • Project Period (FY)
      1993 – 1994
    • Research Category
      Grant-in-Aid for Developmental Scientific Research (B)
    • Research Field
      計算機科学
    • Research Institution
      KYOTO UNIVERSITY
  •  Development of Education-Microprocessor for Computer Engineering and VLSI Engineering.

    • Principal Investigator
      YASUURA Hiroshi
    • Project Period (FY)
      1992 – 1993
    • Research Category
      Grant-in-Aid for Developmental Scientific Research (B)
    • Research Field
      情報工学
    • Research Institution
      KYUSHU UNIVERSITY
  •  Research on Development of Logic Synthesizer and Design Verifier for Sequential Circuits Based on Boolean Function Manipulation

    • Principal Investigator
      YAJIMA Shuzo
    • Project Period (FY)
      1991 – 1992
    • Research Category
      Grant-in-Aid for Developmental Scientific Research (B)
    • Research Field
      情報工学
    • Research Institution
      KYOTO UNIVERSITY

All 2023 2021 2019 2018 2015 2012 2011 2010 2009 2008 2007 2006

All Journal Article Presentation

  • [Journal Article] Parallelizing Random and SAT-based Verification Processes for Improving Toggle Coverage2023

    • Author(s)
      Kiyoharu Hamaguchi
    • Journal Title

      IPSJ Transactions on System LSI Design Methodology

      Volume: 16 Issue: 0 Pages: 45-53

    • DOI

      10.2197/ipsjtsldm.16.45

    • ISSN
      1882-6687
    • Language
      English
    • Peer Reviewed / Open Access
    • Data Source
      KAKENHI-PROJECT-22K11962
  • [Journal Article] Applying an SMT Solver to Coverage-Driven Design Verification2018

    • Author(s)
      HAMAGUCHI Kiyoharu
    • Journal Title

      IEICE Trans. Fundamentals

      Volume: E101.A Issue: 7 Pages: 1053-1056

    • DOI

      10.1587/transfun.E101.A.1053

    • NAID

      130007386622

    • ISSN
      0916-8508, 1745-1337
    • Year and Date
      2018-07-01
    • Language
      English
    • Data Source
      KAKENHI-PROJECT-18K11216
  • [Journal Article] Approximate Model Checking using a Subset of First-Order Logic2011

    • Author(s)
      Kiyoharu Hamaguchi, Kazuya Masuda, Toshinobu Kashiwabara
    • Journal Title

      IPSJ Transactions on System LSI Design Methodology 5(In printing)

    • NAID

      130000418475

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-19500043
  • [Journal Article] Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic2010

    • Author(s)
      Hiroaki Shimizu, Kiyoharu Hamaguchi, Toshinobu Kashiwabara
    • Journal Title

      IPSJ Transactions on System LSI Design Methodology 4

      Pages: 105-117

    • NAID

      110009599081

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-19500043
  • [Journal Article] Approximate Model Checking using a Subset of First-Order Logic2010

    • Author(s)
      Kiyoharu Hamaguchi
    • Journal Title

      IPSJ Transactions on System LSI Design Methodology

      Volume: 3 Pages: 268-282

    • NAID

      130000418475

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22500047
  • [Journal Article] Satisfiability Checking for Logic with Equality and Uninterpreted Functions under Equivalence Constraints2007

    • Author(s)
      Hiroaki Kozawa, Kiyoharu Hamaguchi, Toshinobu Kashiwabara
    • Journal Title

      IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences E90-A

      Pages: 2778-2789

    • NAID

      110007538024

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-19500043
  • [Journal Article] Satisfiability Checking under Equivalence Constraints for a Decidable Subclass of First-Order Logic2006

    • Author(s)
      Hiroaki Kozawa, Kiyoharu Hamaguchi, Toshinobu Kashiwabara
    • Journal Title

      Proceedings of the 13th Workshop on Synthesis And System Integration of Mixed Information technologies 13

      Pages: 363-368

    • Data Source
      KAKENHI-PROJECT-16500030
  • [Presentation] Error Detection Capacity of SAT-based Coverage-driven Design Verification2021

    • Author(s)
      Hiroyuki Nakayama, Kiyoharu Hamaguchi
    • Organizer
      23rd Synthesis and Simulation Meeting and International Interchange
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18K11216
  • [Presentation] Parallelizing SAT-based Coverage-Driven Design Verification2019

    • Author(s)
      Kiyoharu Hamaguchi
    • Organizer
      22nd Synthesis and Simulation Meeting and International Interchange
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18K11216
  • [Presentation] SATソルバーを援用したカバレッジ駆動設計検証について2015

    • Author(s)
      浜口清治
    • Organizer
      情報処理学会システムとLSIの設計技術研究発表会
    • Place of Presentation
      長崎県勤労福祉会館
    • Year and Date
      2015-12-01
    • Data Source
      KAKENHI-PROJECT-25330061
  • [Presentation] 動作レベル回路設計記述の等価性判定における複数の論理体系を利用した抽象化2012

    • Author(s)
      浜口清治
    • Organizer
      DAシンポジウム2012
    • Place of Presentation
      岐阜県下呂市 水明館
    • Data Source
      KAKENHI-PROJECT-22500047
  • [Presentation] 石木裕介(発表者),浜口清治,若宮直紀2012

    • Author(s)
      石木裕介(発表者),浜口清治,若宮直紀
    • Organizer
      DA シンポジウム 2012
    • Place of Presentation
      岐阜県下呂市水明館
    • Year and Date
      2012-08-29
    • Data Source
      KAKENHI-PROJECT-22500047
  • [Presentation] SMTソルバーを利用した近似的な非有界モデル検査アルゴリズムにおける複数の論理体系の組み合わせ手法2009

    • Author(s)
      浜口清治
    • Organizer
      組み込みシステムシンポジウム2009
    • Place of Presentation
      国立オリンピック記念青少年総合センター (東京)
    • Year and Date
      2009-10-22
    • Data Source
      KAKENHI-PROJECT-19500043
  • [Presentation] SMTソルバーを利用した近似的な非有界モデル検査アルゴリズムにおける複数の論理体系の組み合わせ手法2009

    • Author(s)
      浜口清治
    • Organizer
      組み込みシステムシンポジウム2009論文集
    • Data Source
      KAKENHI-PROJECT-19500043
  • [Presentation] 第一階述語論理のサブクラスに対する近似的モデル検査アルゴリズム2009

    • Author(s)
      増田和也, 浜口清治, 柏原敏伸
    • Organizer
      情報処理学会研究報告
    • Data Source
      KAKENHI-PROJECT-19500043
  • [Presentation] Toshinobu Kashiwabara Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic2008

    • Author(s)
      Hiroaki Shimizu, Kiyoharu Hamaguchi
    • Organizer
      6th International Conference on Automated Technology for Verification and Analysis
    • Place of Presentation
      LNCS
    • Data Source
      KAKENHI-PROJECT-19500043
  • [Presentation] 第一階述語論理のサブクラスに対する項の高さ縮減を用いた不変条件の近似的検証アルゴリズム2007

    • Author(s)
      清水博章, 浜口清治, 柏原敏伸
    • Organizer
      情報処理学会研究報告
    • Data Source
      KAKENHI-PROJECT-19500043
  • 1.  YAJIMA Shuzo (20025901)
    # of Collaborated Projects: 4 results
    # of Collaborated Products: 0 results
  • 2.  OGINO Hiroyuki (40144323)
    # of Collaborated Projects: 4 results
    # of Collaborated Products: 0 results
  • 3.  TAKENAGA Yasuhiko (20236491)
    # of Collaborated Projects: 4 results
    # of Collaborated Products: 0 results
  • 4.  HIRAISHI Hiromi (40093299)
    # of Collaborated Projects: 3 results
    # of Collaborated Products: 0 results
  • 5.  TAKAGI Naofumi (10171422)
    # of Collaborated Projects: 3 results
    # of Collaborated Products: 0 results
  • 6.  YASUURA Hiroshi (80135540)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 7.  MURAKAMI Kazuaki (10200263)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 8.  SATOH Masao (30170781)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 9.  ONODERA Hidetoshi (80160927)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 10.  YAMAZAKI Katsuhiro (70134260)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 11.  YASUOKA Kouichi (20230211)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results

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