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Kobayashi Kazutoshi  小林 和淑

ORCIDConnect your ORCID iD *help
… Alternative Names

KOBAYASHI Kazutoshi  小林 和淑

KOBAYASHI K  小林 和淑

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Researcher Number 70252476
Other IDs
External Links
Affiliation (Current) 2025: 京都工芸繊維大学, 電気電子工学系, 教授
Affiliation (based on the past Project Information) *help 2016 – 2023: 京都工芸繊維大学, 電気電子工学系, 教授
2015: 京都工芸繊維大学, その他部局等, 教授
2012: 京都工芸繊維大学, 大学院・工芸科学研究科, 教授
2009 – 2011: Kyoto Institute of Technology, 工芸科学研究科, 教授
2007 – 2008: Kyoto University, 情報学研究科, 准教授 … More
2006: 京都大学, 情報学研究科, 助教授
2004: KYOTO UNIVERSITY, Department of Communications and Computer Engineering, Associate Professor, 情報学研究科, 助教授
2002 – 2003: 東京大学, 大規模集積システム設計教育研究センター, 助教授
2002: 東京大学, 大規模集積システム設計教育センター, 助教授
2001: Graduate School of Informatics, Kyoto University, Associate Professor, 情報学研究科, 助教授
2000: Department of Communications and Computer Engineering, KYOTO UNIVERSITY Instructor, 情報学研究科, 助手
1999: 京都大学, 大学院・情報学研究科, 助手
1999: 京都大学, 大学院・情報研究科, 助手
1999: Kyoto Univ., Graduate Sch. Engin. Res. Assoc., 工学研究科, 助手
1998: 京都大学, 情報学研研究科, 助手
1998: Kyoto University, Dept.of Communications and Computer Engineering, Research Asso, 情報学研究科, 助手
1995 – 1997: Kyoto University, Graduate School of Engineering, Instructor, 工学研究科, 助手
1993 – 1994: 京都大学, 工学部, 助手 Less
Review Section/Research Field
Principal Investigator
情報通信工学 / Computer system/Network / 計算機科学 / Computer system
Except Principal Investigator
電子デバイス・機器工学 / 計算機科学 / Computer system/Network / Basic Section 60040:Computer system-related / Computational science / 情報工学 / Science and Engineering
Keywords
Principal Investigator
VLSI / 機能メモリ / 信頼性 / 一時故障 / 超並列処理 / FPGA / スタックトランジスタ / バルク / FDSOI / パワエレ … More / BTI / ランダムテレグラフノイズ / RTN / NBTI / 永久故障 / パワーエレクトロニクス / 経年劣化 / ソフトエラー / IoT / Variation aware / ばらつき / コンフィギャラブル / プロセッサ / 微細プロセス / ハードウエア設計 / System C / 協調設計 / 動作合成 / SystemC / 期待値比較 / EBプローバ / LSIテスタ / テストベクタ / テスト / シミュレーション / 低ビットレート / 画像圧縮 / 高速バス / 並列処理 / FMPP / SIMD / 並列プロセッサ / ベクトル量子化 / 動画像処理 / 再構成可能性 / 柔軟な処理 … More
Except Principal Investigator
VLSI / LSI / ASIC / Parallel Processing / 並列処理 / 集積回路 / 低消費電力化 / SerDes / DSP / Statistical Analysis / Image Compression / 低ビットレート / 画像圧縮 / 高速バス / 機能メモリ / FMPP / Analog Circuit / アナログ回路 / Symbolic Layout / アナログCAD / シンボリックレイアウト / ばらつき / スタンダードセル / 統計的遅延解析 / ばらつき考慮設計 / 経年劣化 / 製造容易化設計 / 製造ばらつき / 動き補償 / IoT / 特性ゆらぎ / 信頼性 / 常時起動デバイス / デバイスシミュレーション / 数値計算手法 / ブレークダウン / 局所打切り誤差 / 主要応答時定数 / 正帰還系シミュレーション / 負の主要応答時定数 / ホモトピー法 / バイアス電圧増分量制限法 / 時間刻み幅制御 / 局所的打切り誤差 / 過渡解析 / ハードブレークダウン / スナップバック / 負の時定数 / Signal Transmission / 応答局面法 / スパイラルインダクタ / ドライバ駆動力 / 配線構造 / 伝送線路 / LSI配線 / RLC抽出 / 性能予測 / リング型PLL / LC型PLL / PLL / オンチップ伝送線路 / 高速信号伝達 / 配線特性 / 高速信号伝送 / Hierarchical Design / Inter-Chip Variability / Intra-Chip Variability / Statistical Timing Analysis / Manufacturing Variability / モンテカルロ解析 / 統計モデリング / 設計容易化技術 / ロバスト設計 / 歩留り最大化 / 統計的解析 / 階層設計 / チップ間ばらつき / チップ内ばらつき / 統計解析 / Video Compression / Low Power / Memory Distribution / Design Techniques / Architecture / Motion Estimation / プロセッサ アレー / 設計手法 / 低消費電力 / アーキテクチャ / プロセッサアレー / 動画像圧縮 / Low-rate / Multimedia / マルチメディア / Input reordering / Gate sizing / Standard cell library / Library generation / Cell-base design / High speed design / Low power design / optimization of detailed design / 最適化設計 / CMOS理論ゲート / 遅延時間モデル / 消費電力モデル / 遅延最適化 / 物理設計 / システムLSI / ディープサブミクロンプロセス / 遅延最小化 / クロストーク / 詳細設計 / 接続最適化 / ゲート寸法最適化 / スタンダードセルライブラリ / ライブラリ生成 / セルベース設計 / 高速化設計 / 低消費電力化設計 / 詳細設計最適化 / Worst Case Analysis / Circuit Simulation / Matching Analysis / Parameter Extraction / Intermediate Model / Statistical Modeling / Scaled MOSFET / 共通モデル / 歩留り / 統計的設計最適化 / パラメータ抽出 / 統計的モデル化 / ばらつきモデル / ワ-ストケース解析 / 回路シミュレーション / 統計的回路解析 / 比精度解析 / モデルパラメータ抽出 / 中間モデル / 統計モデル / MOSFET / Low Bit-rate / Vector Quantization / CAM / Functional Memory / 光通信 / 超並列処理 / Analog HDL / Analog CAD / Circuit Design / Layout Design / Optimization / Analog Layout / アナログHDL / 回路設計 / レイアウト設計 / 最適化 / アナログレイアウト / Gate Array / Standard Cell / LSI Design / Comprehenseve Benchmarks / LSI CAD / Standard Library / ゲートアレー / LSI設計 / 総合ベンチマークセット / LSIのCAD / 標準ライブラリ / LSI Design System / Reuse of Design Knowledge / Knowledge Aquisition / Analog ASIC / Design Methodology of Analog LSI / Analog LSI / Reuse of Design Procedure / アナログ回路最適化 / アナログレイアウト合成 / アナログ回路合成 / モジュールジェネレータ / 設計知識獲得 / LSI設計システム / 知識再利用 / 知識獲得 / アナログASIC / アナログ回路設計手法 / アナログLSI / 設計方法の再利用 / Geometrical processing / Content addressable memory / Hardware engine / Layout verification / LSI layout / Design rule check / ハードウエアエンジン / 図形演算 / 連想メモリ / ハードウェアエンジン / デザインルールチェック / レイアウト検証 / LSIレイアウト / 図形処理専用計算機 / システムオンチップ / ディペンダブルLSI / 低消費電力設計 / LSI設計技術 / ディペンダブル VLSI / 耐ばらつき設計 / 低電圧動作 / 製造容易性 / DFY / DFM / NBTI / 歩留まり / ディペンダブルVLSI / 高信頼化 / 動画像 / 動きベクトル / ジャイロセンサ Less
  • Research Projects

    (24 results)
  • Research Products

    (119 results)
  • Co-Researchers

    (23 People)
  •  Long-term NBTI measurement and its modeling

    • Principal Investigator
      Matsumoto Takashi
    • Project Period (FY)
      2018 – 2023
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Review Section
      Basic Section 60040:Computer system-related
    • Research Institution
      The University of Tokyo
  •  Intelligently controled device simulator utlizing small numer of dominant time constant approximation

    • Principal Investigator
      Kumashiro Shigetaka
    • Project Period (FY)
      2017 – 2020
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Research Field
      Computational science
    • Research Institution
      Kyoto Institute of Technology
  •  An IoT that can keep on running over years efficiently and reliablyPrincipal Investigator

    • Principal Investigator
      Kobayashi Kazutoshi
    • Project Period (FY)
      2015 – 2018
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      Computer system
    • Research Institution
      Kyoto Institute of Technology
  •  Integrated Circuit Design for Robust Operation under Low Supply Voltage

    • Principal Investigator
      ONODERA Hidetoshi
    • Project Period (FY)
      2010 – 2012
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      Computer system/Network
    • Research Institution
      Kyoto University
  •  Evaluation of Low-Cost Circuit-level Techniques to Compensate Temporal Errors.Principal Investigator

    • Principal Investigator
      KOBAYASHI Kazutoshi
    • Project Period (FY)
      2009 – 2011
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      Computer system/Network
    • Research Institution
      Kyoto Institute of Technology
  •  Variation and Defect Aware Design of Integrated Circuits

    • Principal Investigator
      ONODERA Hidetoshi
    • Project Period (FY)
      2007 – 2009
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      Computer system/Network
    • Research Institution
      Kyoto University
  •  Fablication-friendly Configurable Processors in a nanometer LSI processPrincipal Investigator

    • Principal Investigator
      KOBAYASHI Kazutoshi
    • Project Period (FY)
      2006 – 2008
    • Research Category
      Grant-in-Aid for Young Scientists (A)
    • Research Field
      Computer system/Network
    • Research Institution
      Kyoto University
  •  ハードソフト同時設計によるシステムLSIの設計効率化・開発期間短期化Principal Investigator

    • Principal Investigator
      小林 和淑
    • Project Period (FY)
      2002 – 2003
    • Research Category
      Grant-in-Aid for Young Scientists (B)
    • Research Field
      情報通信工学
    • Research Institution
      The University of Tokyo
  •  Research of a High-speed Signal Transmission Scheme for Integrated Circuits

    • Principal Investigator
      ONODERA Hidetoshi
    • Project Period (FY)
      2002 – 2004
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      電子デバイス・機器工学
    • Research Institution
      KYOTO UNIVERSITY
  •  動き補償を利用した動画像の実時間背景・対象物分離アルゴリズムとハードウエアの開発

    • Principal Investigator
      ONODERA Hidetoshi
    • Project Period (FY)
      2001 – 2002
    • Research Category
      Grant-in-Aid for Scientific Research on Priority Areas
    • Review Section
      Science and Engineering
    • Research Institution
      Kyoto University
  •  設計者のための統合型VLSIテスト環境の開発Principal Investigator

    • Principal Investigator
      小林 和淑
    • Project Period (FY)
      2000 – 2001
    • Research Category
      Grant-in-Aid for Encouragement of Young Scientists (A)
    • Research Field
      情報通信工学
    • Research Institution
      Kyoto University
  •  Development of Statistical Performance Analysis and Optimization Methods for Large Scale Integrated Circuits

    • Principal Investigator
      ONODERA Hidetoshi
    • Project Period (FY)
      1999 – 2001
    • Research Category
      Grant-in-Aid for Scientific Research (B)
    • Research Field
      電子デバイス・機器工学
    • Research Institution
      KYOTO UNIVERSITY
  •  機能メモリ上でのベクトル量子化を用いた画像圧縮法の検討Principal Investigator

    • Principal Investigator
      小林 和淑
    • Project Period (FY)
      1998 – 1999
    • Research Category
      Grant-in-Aid for Encouragement of Young Scientists (A)
    • Research Field
      情報通信工学
    • Research Institution
      Kyoto University
  •  Development of a Functional LSI Achieving Low-rate Multimedia Data Transmission.

    • Principal Investigator
      ONODERA Hidetoshi, 田丸 啓吉
    • Project Period (FY)
      1998 – 2000
    • Research Category
      Grant-in-Aid for Scientific Research (B).
    • Research Field
      電子デバイス・機器工学
    • Research Institution
      KYOTO UNIVERSITY
  •  Development of a Memory-Based Low-Energy Processor for Real-Time Motion

    • Principal Investigator
      MOSHNYAGA Vashily
    • Project Period (FY)
      1998 – 1999
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Research Field
      電子デバイス・機器工学
    • Research Institution
      Fukuoka University
  •  Optimization of detailed design for UDSM (ultra deep submicron) integrated circuits

    • Principal Investigator
      ONODERA Hidetoshi
    • Project Period (FY)
      1997 – 1998
    • Research Category
      Grant-in-Aid for Scientific Research (C)
    • Research Field
      電子デバイス・機器工学
    • Research Institution
      KYOTO UNIVERSITY
  •  機能メモリ上でのベクトル量子化を用いた画像圧縮手法の検討Principal Investigator

    • Principal Investigator
      小林 和淑
    • Project Period (FY)
      1996
    • Research Category
      Grant-in-Aid for Encouragement of Young Scientists (A)
    • Research Field
      計算機科学
    • Research Institution
      Kyoto University
  •  Statistical modeling method for scaled MOSFET

    • Principal Investigator
      ONODERA Hidetoshi
    • Project Period (FY)
      1996 – 1997
    • Research Category
      Grant-in-Aid for Scientific Research (A)
    • Research Field
      電子デバイス・機器工学
    • Research Institution
      KYOTO UNIVERSITY
  •  演算機能を持つメモリLSIを用いたプロセッサボードの制御方式の検討Principal Investigator

    • Principal Investigator
      小林 和淑
    • Project Period (FY)
      1995
    • Research Category
      Grant-in-Aid for Encouragement of Young Scientists (A)
    • Research Field
      計算機科学
    • Research Institution
      Kyoto University
  •  Development of a Computing System by a Functional Memory Type Parallel Processor.

    • Principal Investigator
      TAMARU Keikichi
    • Project Period (FY)
      1995 – 1997
    • Research Category
      Grant-in-Aid for Scientific Research (A)
    • Research Field
      計算機科学
    • Research Institution
      KYOTO UNIVERSITY
  •  Development of Comprehensive Set of LSI CAD Benchmarks

    • Principal Investigator
      ONODERA Hidetoshi
    • Project Period (FY)
      1994 – 1995
    • Research Category
      Grant-in-Aid for Developmental Scientific Research (B)
    • Research Field
      計算機科学
    • Research Institution
      KYOTO UNIVERSITY
  •  Simultaneous Circuit and Layout Design Method for Analog LSIs under Performance Constraints

    • Principal Investigator
      ONODERA Hidetoshi
    • Project Period (FY)
      1994 – 1995
    • Research Category
      Grant-in-Aid for General Scientific Research (C)
    • Research Field
      計算機科学
    • Research Institution
      KYOTO UNIVERSITY
  •  Effective Design Methodology for Analog LSIs that Acquires and Reuses Design

    • Principal Investigator
      TAMARU Keikichi
    • Project Period (FY)
      1993 – 1995
    • Research Category
      Grant-in-Aid for General Scientific Research (B)
    • Research Field
      電子デバイス・機器工学
    • Research Institution
      KYOTO UNIVERSITY
  •  Development of a Computer Specific to LSI Geometrical Processing

    • Principal Investigator
      TAMARU Keikichi
    • Project Period (FY)
      1992 – 1994
    • Research Category
      Grant-in-Aid for Developmental Scientific Research (B)
    • Research Field
      情報工学
    • Research Institution
      KYOTO UNIVERSITY

All 2020 2019 2018 2017 2016 2015 2013 2012 2011 2010 2009 2008 2007 2006

All Journal Article Presentation Patent

  • [Journal Article] Universal NBTI Compact Model Replicating AC Stress/Recovery from a Single-shot Long-term DC Measurement2020

    • Author(s)
      Hosaka Takumi、Nishizawa Shinichi、Kishida Ryo、Matsumoto Takashi、Kobayashi Kazutoshi
    • Journal Title

      IPSJ Transactions on System LSI Design Methodology

      Volume: 13 Issue: 0 Pages: 56-64

    • DOI

      10.2197/ipsjtsldm.13.56

    • NAID

      130007887399

    • Peer Reviewed / Open Access
    • Data Source
      KAKENHI-PROJECT-18K11210
  • [Journal Article] An Efficient and Accurate Time Step Control Method for Power Device Transient Simulation Utilizing Dominant Time Constant Approximation2020

    • Author(s)
      Kumashiro Shigetaka、Kamei Tatsuya、Hiroki Akira、Kobayashi Kazutoshi
    • Journal Title

      IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

      Volume: 39 Issue: 2 Pages: 451-463

    • DOI

      10.1109/tcad.2018.2889673

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-17K05142
  • [Journal Article] Evaluation of plasma-induced damage and bias temperature instability depending on type of antenna layer using current-starved ring oscillators2018

    • Author(s)
      Kishida Ryo、Furuta Jun、Kobayashi Kazutoshi
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: 57 Issue: 4S Pages: 04FD12-04FD12

    • DOI

      10.7567/jjap.57.04fd12

    • NAID

      210000148889

    • Data Source
      KAKENHI-PROJECT-15H02677
  • [Journal Article] A Low-Power Radiation-Hardened Flip-Flop with Stacked Transistors in a 65 nm FDSOI Process2018

    • Author(s)
      MARUOKA Haruki、HIFUMI Masashi、FURUTA Jun、KOBAYASHI Kazutoshi
    • Journal Title

      IEICE Trans. Electron.

      Volume: E101.C Issue: 4 Pages: 273-280

    • DOI

      10.1587/transele.E101.C.273

    • NAID

      130006602277

    • ISSN
      0916-8524, 1745-1353
    • Language
      English
    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-15H02677
  • [Journal Article] Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model2017

    • Author(s)
      T. Komawaki, M. Yabuuchi, R. Kishida, J. Furuta, T. Matsumoto, and K. Kobayashi
    • Journal Title

      IEICE Trans. Fundamentals

      Volume: E100.A Issue: 12 Pages: 2758-2763

    • DOI

      10.1587/transfun.E100.A.2758

    • NAID

      130006236533

    • ISSN
      0916-8508, 1745-1337
    • Language
      English
    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-15H02677
  • [Journal Article] A Radiation-Hardened Non-Redundant Flip-Flop, Stacked Leveling Critical Charge Flip-Flop in a 65 nm Thin BOX FD-SOI Process2016

    • Author(s)
      J. Furuta, J. Yamaguchi, and K. Kobayashi
    • Journal Title

      IEEE Trans. on Nuclear Science

      Volume: 63 Issue: 4 Pages: 2080-2086

    • DOI

      10.1109/tns.2016.2543745

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-15H02677
  • [Journal Article] Size Optimization Technique for Logic Circuits that Considers BTI and Process Variations2016

    • Author(s)
      M. Yabuuchi, and K. Kobayashi
    • Journal Title

      IPSJ Transactions on System LSI Design Methodology

      Volume: 9 Issue: 0 Pages: 72-78

    • DOI

      10.2197/ipsjtsldm.9.72

    • NAID

      130005255788

    • ISSN
      1882-6687
    • Language
      English
    • Peer Reviewed / Acknowledgement Compliant / Open Access
    • Data Source
      KAKENHI-PROJECT-15H02677
  • [Journal Article] A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode2015

    • Author(s)
      石橋, 杉井, 蒲原, 宇佐美, 天野, 小林, Pham Cong-Kha
    • Journal Title

      IEICE Trans. on Electronics

      Volume: E98-C Pages: 536-543

    • NAID

      130005086141

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-15H02677
  • [Journal Article] Impact of Cell Distance and Well-contact Density on Neutron-induced Multiple Cell Upsets2015

    • Author(s)
      古田, 小林, 小野寺
    • Journal Title

      IEICE Trans. Electron.

      Volume: E98.C Issue: 4 Pages: 298-303

    • DOI

      10.1587/transele.E98.C.298

    • NAID

      130005061834

    • ISSN
      0916-8524, 1745-1353
    • Language
      English
    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-15H02677
  • [Journal Article] Impact of Body-Biasing Technique on Random Telegraph Noise Induced Delay Fluctuation2013

    • Author(s)
      Takashi Matsumoto, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Journal Title

      Japanese Journal of Applied Physics (JJAP)

      Volume: vol 52, no 4 Issue: 4S Pages: 1-3

    • DOI

      10.7567/jjap.52.04ce05

    • NAID

      210000142035

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Journal Article] Variation-sensitive Monitor Circuits for Estimation of Global Process Parameter Variation2012

    • Author(s)
      Islam A.K.M. Mahfuzul, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Journal Title

      IEEE Trans. Semiconductor Manufacturing

      Volume: vol 25, no 4 Issue: 4 Pages: 571-580

    • DOI

      10.1109/tsm.2012.2198677

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Journal Article] Multicore Large-Scale Integration Lifetime Extention by Negative Bias Temperature Instability Recovery-Based Self-Healing2012

    • Author(s)
      Takashi Matsumoto, Hiroaki Makino, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: vol.51(印刷中)

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Journal Article] A 65 nm Complementary Metal-Oxide-Semiconductor 400 ns Measurement Delay Negative-Bias-Temperature-Instability Recovery Sensor with Minimum Assist Circuit2011

    • Author(s)
      松本, 牧野, 小林, 小野寺
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: vol.50 Issue: 4S Pages: 04DE06-04DE06

    • DOI

      10.1143/jjap.50.04de06

    • NAID

      210000070301

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-21300014
  • [Journal Article] A 65 nm Complementary Metal-Oxide-Semiconductor 400 ns Measurement Delay Negative-Bias-Temperature-Instability Recovery Sensor with Minimum Assist Circuit2011

    • Author(s)
      Takashi Matsumoto, Hiroaki Makino, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: vol.50

    • NAID

      210000070301

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Journal Article] Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures2011

    • Author(s)
      濱中, 山本, 古田, 久保田, 小林, 小野寺
    • Journal Title

      IEICE Trans. Fundamentals

      Volume: E94-A Issue: 12 Pages: 2669-2675

    • DOI

      10.1587/transfun.E94.A.2669

    • NAID

      10030533865

    • ISSN
      0916-8508, 1745-1337
    • Language
      English
    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-21300014
  • [Journal Article] An Area-efficient 65 nm Radiation-Hard Dual-Modular Flip-Flop to Avoid Multiple Cell Upsets2011

    • Author(s)
      山本, 濱中, 古田, 小林, 小野寺
    • Journal Title

      IEEE Trans. on Nuclear Science

      Volume: vol.58 Issue: 6 Pages: 3053-3059

    • DOI

      10.1109/tns.2011.2169457

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-21300014
  • [Journal Article] Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells2010

    • Author(s)
      H.Sunagawa, H.Terada, A.Tsuchiya, K.Kobayashi, H.Onodera
    • Journal Title

      IPSJ Trans.System LSI Design Methodology 3

      Pages: 130-139

    • NAID

      130000251502

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-21300014
  • [Journal Article] Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells2010

    • Author(s)
      H.Sunagawa, H.Terada, A.Tsuchiya, K.Kobayashi, H.Onodera
    • Journal Title

      IPSJ Transactions on System LSI Design Methodology Vol. 3

      Pages: 130-139

    • NAID

      130000251502

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-19300010
  • [Journal Article] An Area/Delay Efficient Dual-modular Flip-Flop with Higher SEU/SET Immunity2010

    • Author(s)
      J.Furuta, K.Kobayashi., et.al
    • Journal Title

      IEICE Trans.Electron. E93-C

      Pages: 340-346

    • NAID

      10026824857

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-21300014
  • [Journal Article] Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells2010

    • Author(s)
      Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Journal Title

      IPSJ Transactions on System LSI Design Methodology vol.3

      Pages: 130-139

    • NAID

      130000251502

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-19300010
  • [Journal Article] Micro/nanoimprinting of Glass under High Temperature Using a CVD Diamond Mold2008

    • Author(s)
      M. Komori, H. Uchiyama, H. Takebe, T. Kusuura, K. Kobayashi, H. Kuwahara, T. Tsuchiya
    • Journal Title

      JOURNAL OF MICROMECHANICS AND MICROENGINEERING no.18

      Pages: 65013-65013

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Journal Article] A 90nm 8x16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations2007

    • Author(s)
      Yuuri Sugihara, Manabu Kotani, Kazuya Katsuki, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Journal Title

      12th Asia and South Pacific Design Automation Conference

      Pages: 122-123

    • Data Source
      KAKENHI-PROJECT-18680005
  • [Journal Article] A 90nm 48x48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations2007

    • Author(s)
      K. Kobayashi, K. Katsuki, M. Kotani, Y.Sugihara, Y. Kume, H. Onodera
    • Journal Title

      IEICE Trans. on Electronics vol.E90-C, no.10

      Pages: 1919-1926

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Journal Article] A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations2007

    • Author(s)
      Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Journal Title

      IEICE Trans. on Electronics vol.E90-C, no.4

      Pages: 699-707

    • NAID

      110007522167

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Journal Article] A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations2007

    • Author(s)
      K. Katsuki, M. Kotani, K. Kobayashi, H. Onodera
    • Journal Title

      IEICE Transacition on Electronics vol E90-C

      Pages: 699-707

    • NAID

      110007522167

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Journal Article] A 90nm 48x48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations2007

    • Author(s)
      K. Kobayashi, K. Katsuki, M. Kotani, Y. Sugihara, Y. Kume, H. Onodera
    • Journal Title

      IEICE Transacition on Electronics vol E90-C

      Pages: 1919-1926

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Journal Article] A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations2007

    • Author(s)
      Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi
    • Journal Title

      IEICE Trans.on Electronics Vol.E90-C, No.4

      Pages: 699-707

    • NAID

      110007522167

    • Data Source
      KAKENHI-PROJECT-18680005
  • [Journal Article] A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era2006

    • Author(s)
      K.Kobayashi, A.Higuchi, H.Onodera
    • Journal Title

      IEICE Transaction on Electronics Vol.E89-C, No.6

      Pages: 838-843

    • NAID

      110007503175

    • Data Source
      KAKENHI-PROJECT-18680005
  • [Journal Article] A 90nm 8x16 LUT-based FPGA Enhancing Speed and Yield Utilizing Within-Die Variations2006

    • Author(s)
      M.Kotani, K.Katsuki, K.Kobayashi, H.Onodera
    • Journal Title

      European Solid State Circuit Conference

      Pages: 110-113

    • Data Source
      KAKENHI-PROJECT-18680005
  • [Journal Article] A Yield and Speed Enhancement Technique Using Reconfigurable Devices against Within-Die Variations on2006

    • Author(s)
      K.Kobayashi, M.Kotani, et al.
    • Journal Title

      International Conference on Field Programmable Logic and Applications

      Pages: 761-764

    • Data Source
      KAKENHI-PROJECT-18680005
  • [Journal Article] A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era2006

    • Author(s)
      K. Kobayashi, A. Higuchi, H. Onodera
    • Journal Title

      IEICE Transaction on Electronics vol.E89-C, no.6

      Pages: 838-843

    • NAID

      110007503175

    • Peer Reviewed
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Patent] 入出力回路、及びフリップフロップ回路2015

    • Inventor(s)
      小林,古田,山口
    • Industrial Property Rights Holder
      国立大学法人京都工芸繊維大学
    • Industrial Property Rights Type
      特許
    • Industrial Property Number
      2015-160642
    • Filing Date
      2015-08-17
    • Data Source
      KAKENHI-PROJECT-15H02677
  • [Patent] フリップフロップ回路2010

    • Inventor(s)
      古田潤、小林和淑、小野寺秀俊
    • Industrial Property Rights Holder
      京都工芸繊維大学
    • Industrial Property Number
      2010-134066
    • Filing Date
      2010-06-11
    • Data Source
      KAKENHI-PROJECT-21300014
  • [Patent] フリップフロップ回路2010

    • Inventor(s)
      古田潤、小林和淑、小野寺秀俊
    • Industrial Property Rights Holder
      京都工芸繊維大学
    • Filing Date
      2010-06-11
    • Data Source
      KAKENHI-PROJECT-21300014
  • [Patent] 半導体デバイス2008

    • Inventor(s)
      小林和淑, 杉原有理, 久米洋平, 小野寺秀俊
    • Industrial Property Rights Holder
      国立大学法人京都大学
    • Industrial Property Number
      2008-026588
    • Filing Date
      2008-02-06
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Patent] 多重化実行に対してスケーラブルなプロセッサのパイプライン2008

    • Inventor(s)
      嶋田創, 姚駿, 小林和淑
    • Industrial Property Rights Holder
      国立大学法人京都大学
    • Industrial Property Number
      2008-214900
    • Filing Date
      2008-08-25
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Patent] 半導体デバイス2008

    • Inventor(s)
      小林和淑 他
    • Industrial Property Rights Holder
      京都大学
    • Industrial Property Number
      2008-026588
    • Filing Date
      2008-02-06
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] Compact Modeling of NBTI Replicationg AC Stress / Recovery from a Single-shot Long-term DC Measurement2019

    • Author(s)
      Shinichi NISHIZAWA, Takumi HOSAKA, Ryo KISHIDA, Takashi MATSUMOTO, Kazutoshi KOBAYASHI
    • Organizer
      25th IEEE International Symposium on On-Line Testing and Robust System Design
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-18K11210
  • [Presentation] 単発DCストレス測定による負バイアス温度不安定性のAC特性を再現可能なモデル2019

    • Author(s)
      保坂 巧、西澤真一、岸田 亮、松本高士、小林和淑
    • Organizer
      電子情報通信学会 デザインガイア2019
    • Data Source
      KAKENHI-PROJECT-18K11210
  • [Presentation] Matrix Exponential法を用いた過渡解析の時間刻み制御とニュートン反復回数の削減2018

    • Author(s)
      亀井達也, 熊代成孝, 小林和淑, 廣木彰, 古田潤
    • Organizer
      第31回 回路とシステムワークショップ
    • Data Source
      KAKENHI-PROJECT-17K05142
  • [Presentation] Matrix Exponential法を用いたパワーMOSFETの過渡解析の高速化2018

    • Author(s)
      亀井達也、熊代成孝、小林和淑
    • Organizer
      電子情報通信学会ICD研究会
    • Data Source
      KAKENHI-PROJECT-17K05142
  • [Presentation] Sensitivity to Soft Errors of NMOS and PMOS Transistors Evaluated by Latches with Stacking Structures in a 65 nm FDSOI Proces2018

    • Author(s)
      K. Yamada, H. Maruoka, J. Furuta, and K. Kobayashi
    • Organizer
      IEEE International Reliability Physics Symposium
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-15H02677
  • [Presentation] Circuit-level Simulation Methodology for Random Telegraph Noise by Using Verilog-AMS2017

    • Author(s)
      T. Komawaki, M. Yabuuchi, R. Kishida, J. Furuta, T. Matsumoto, and K. Kobayashi
    • Organizer
      Circuit-level Simulation Methodology for Random Telegraph Noise by Using Verilog-AMS
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-15H02677
  • [Presentation] The Impact of RTN-Induced Temporal Performance Fluctuation Against Static Performance Variation2017

    • Author(s)
      T. Matsumoto, K. Kobayashi, and H. Onodera
    • Organizer
      Electron Devices Technology and Manufacturing
    • Place of Presentation
      Toyama, Japan
    • Year and Date
      2017-03-01
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-15H02677
  • [Presentation] Radiation-Hardened Flip-Flops with Low Delay Overheads Using PMOS Pass-Transistors to Suppress a SET Pulse in a 65 nm FDSOI Process2017

    • Author(s)
      K. Yamada, H. Maruoka, J. Furuta, and K. Kobayashi
    • Organizer
      The conference on Radiation and its Effects on Components and Systems
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-15H02677
  • [Presentation] A Flip-Flop with High Soft-error Tolerance and Small Power and Delay Overheads2017

    • Author(s)
      K. Yamada, H. Maruoka, J. Furuta, and K. Kobayashi
    • Organizer
      Symposium on Low-Power and High-Speed Chips (COOL Chips)
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-15H02677
  • [Presentation] 行列指数法によるデバイス過渡シミュレーションの正確な時間刻み指標2017

    • Author(s)
      熊代成孝、亀井達也、廣木彰、小林和淑
    • Organizer
      電子情報通信学会SDM研究会
    • Invited
    • Data Source
      KAKENHI-PROJECT-17K05142
  • [Presentation] Degradation Caused by Negative Bias Temperature Instability Depending on Body Bias on NMOS or PMOS in 65 nm Bulk and Thin-BOX FDSOI Processes2017

    • Author(s)
      R. Kishida, and K. Kobayashi
    • Organizer
      Electron Devices Technology and Manufacturing
    • Place of Presentation
      Toyama, Japan
    • Year and Date
      2017-03-01
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-15H02677
  • [Presentation] An Accurate Metric to Control Time Step of Transient Device Simulation by Matrix Exponential Method2017

    • Author(s)
      Shigetaka Kumashiro, Tatsuya Kamei, Akira Hiroki, Kazutoshi Kobayashi
    • Organizer
      SISPAD 2017
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-17K05142
  • [Presentation] Highly-reliable Integrated Circuits for Ground and Space Applications2017

    • Author(s)
      ,K. Kobayashi
    • Organizer
      International Conference on ASIC
    • Invited / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-15H02677
  • [Presentation] Plasma Induced Damage Depending on Antenna Layers in Ring Oscillators2017

    • Author(s)
      R. Kishida, J. Furuta, and K. Kobayashi
    • Organizer
      International Conference on Solid State Devices and Materials
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-15H02677
  • [Presentation] A 16 nm FinFET Radiation-hardened Flip-Flop, Bistable Cross-coupled Dual-Modular-Redundancy FF for Terrestrial and Outer-Space Highly-reliable Systems2017

    • Author(s)
      K. Kobayashi, J. Furuta, H. Maruoka, M. Hifumi, S. Kumashiro, T. Kato, and S. Kohri
    • Organizer
      IEEE International Reliability Physics Symposium
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-15H02677
  • [Presentation] Influence of Layout Structures to Soft Errors Caused by Higher-energy Particles on 28/65 nm FDSOI Flip-Flops2017

    • Author(s)
      M. Hifumi, H. Maruoka, S. Umehara, K. Yamada, J. Furuta, and K. Kobayashi
    • Organizer
      IEEE International Reliability Physics Symposium
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-15H02677
  • [Presentation] A Radiation-hard Layout Structure to Control Back-Gate Biases in a 65 nm Thin-BOX FDSOI Process2016

    • Author(s)
      J. Yamaguchi, J. Furuta, and K. Kobayashi
    • Organizer
      SOI-3D-Subthreshold Microelectronics Technology Unified Conference
    • Place of Presentation
      Burlingame, CA, USA
    • Year and Date
      2016-10-10
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-15H02677
  • [Presentation] A Non-Redundant Low-Power Flip Flop with Stacked Transistors in a 65 nm Thin BOX FDSOI Process2016

    • Author(s)
      H. Maruoka, M. Hifumi, J. Furuta, and K. Kobayashi
    • Organizer
      The conference on Radiation and its Effects on Components and Systems
    • Place of Presentation
      Bremen, Germany
    • Year and Date
      2016-09-19
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-15H02677
  • [Presentation] Impact of Random Telegraph Noise on Ring Oscillators Evaluated by Circuit-level Simulations2015

    • Author(s)
      大島, Pieter Weckx, Ben Kaczer, 小林, 松本
    • Organizer
      International Conference on IC Design and Technology
    • Place of Presentation
      Leuven, Belgium
    • Year and Date
      2015-06-02
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-15H02677
  • [Presentation] A Radiation-Hardened Non-redundant Flip-Flop, Stacked Leveling Critical Charge Flip-Flop in a 65 nm Thin BOX FD-SOI Process2015

    • Author(s)
      山口, 古田, 小林
    • Organizer
      The conference on Radiation and its Effects on Components and Systems
    • Place of Presentation
      Moscow, Russia
    • Year and Date
      2015-09-10
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-15H02677
  • [Presentation] Analysis of the Soft Error Rates on 65-nm SOTB and 28-nm UTBB FD-SOI Structures by a PHITS- TCAD Based Simulation Tool2015

    • Author(s)
      張, 神田, 山口, 古田, 小林
    • Organizer
      International Conference on Simulation of Semiconductor Processes and Devices
    • Place of Presentation
      Washington DC, USA
    • Year and Date
      2015-09-10
    • Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-15H02677
  • [Presentation] Defect-Oriented Degradations in Recent VLSIs: Random Telegraph Noise, Bias Temperature Instability and Total Ionizing Dose2015

    • Author(s)
      小林
    • Organizer
      International Workshop on Radiation Effects on Semiconductor Devices for Space Applications, pp. 110-113
    • Place of Presentation
      Kiryu, Gunma, Japan
    • Year and Date
      2015-11-12
    • Invited / Int'l Joint Research
    • Data Source
      KAKENHI-PROJECT-15H02677
  • [Presentation] ランダム・テレグラフ・ノイズに起因したディジタル回路遅延ゆらぎについて2011

    • Author(s)
      松本高士, 伊東恭佑, 小林和淑, 小野寺秀俊
    • Organizer
      DAシンポジウム
    • Place of Presentation
      下呂市
    • Year and Date
      2011-08-31
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] Impact of RTN and NBTI on Synchorous Circuit Reliability2011

    • Author(s)
      Takashi Matsumoto, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Organizer
      IEEE/ACM Workshop on Variability Modeling and Characterization
    • Place of Presentation
      San Jose(アメリカ合衆国)
    • Year and Date
      2011-11-10
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] ディジタル回路遅延の経年劣化とそのモデル化について2011

    • Author(s)
      松本高士, 小林和淑, 小野寺秀俊
    • Organizer
      電子情報通信学会基礎・境界ソサイエティ大会
    • Place of Presentation
      札幌
    • Year and Date
      2011-09-13
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] 微細化によるLSIの信頼性諸問題とその解決策2011

    • Author(s)
      小林和淑
    • Organizer
      広島大学先端物質科学研究科半導体集積科学専攻講演会
    • Place of Presentation
      東広島市(広島大学)(招待講演)
    • Year and Date
      2011-11-22
    • Data Source
      KAKENHI-PROJECT-21300014
  • [Presentation] 微細化FPGAの信頼性諸問題2011

    • Author(s)
      小林和淑
    • Organizer
      関西FPGAカンファレンス
    • Place of Presentation
      大阪市(梅田センタービル)(招待講演)
    • Year and Date
      2011-10-28
    • Data Source
      KAKENHI-PROJECT-21300014
  • [Presentation] FPGA配線構造におけるRTNモデルを用いたNBTI遅延解析手法の検討2011

    • Author(s)
      籔内, 小林
    • Organizer
      DAシンポジウム
    • Place of Presentation
      下呂
    • Year and Date
      2011-09-01
    • Data Source
      KAKENHI-PROJECT-21300014
  • [Presentation] Correlations between Well Potential and SEUs Measured by Well-Potential Perturbation Detectors in 65nm2011

    • Author(s)
      古田, 山本, 小林, 小野寺
    • Organizer
      Solid-State Circuits Conference
    • Place of Presentation
      Jeju, Korea
    • Year and Date
      2011-11-16
    • Data Source
      KAKENHI-PROJECT-21300014
  • [Presentation] Measurement of Neutron-induced SET Pulse Width Using Propagation-induced Pulse Shrinking2011

    • Author(s)
      古田, 濱中, 小林, 小野寺
    • Organizer
      IEEE International Reliability Physics Symposium
    • Place of Presentation
      Monterey, CA, USA
    • Year and Date
      2011-04-13
    • Data Source
      KAKENHI-PROJECT-21300014
  • [Presentation] A 65nm Flip-Flop Array to Measure Soft Error Resiliency against High-Energy Neutron and Alpha Particles2011

    • Author(s)
      古田, 濱中, 小林, 小野寺
    • Organizer
      Asia and South Pacific Design Automation Conference
    • Place of Presentation
      Yokohama, Japan
    • Year and Date
      2011-01-26
    • Data Source
      KAKENHI-PROJECT-21300014
  • [Presentation] NBTI回復現象を利用したマルチコアLSIの自己特性補償法2011

    • Author(s)
      松本高士, 牧野紘明, 小林和淑, 小野寺秀俊
    • Organizer
      電子情報通信学会技術報告(集積回路設計)
    • Place of Presentation
      宮崎
    • Year and Date
      2011-11-29
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] Variation-sensitive Monitor Circuits for Estimation of Die-to-Die Process Variation2011

    • Author(s)
      Islam A.K.M Mahfuzul, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Organizer
      2011 IEEE International Conference on Microelectronic Test structure
    • Place of Presentation
      Amsterdam(オランダ)
    • Year and Date
      2011-04-06
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] トランジスタレベルでの経年劣化補償技術におけるNBTI回復特性の利用について2011

    • Author(s)
      松本高士、牧野裕明、小林和淑、小野寺秀俊
    • Organizer
      LSIとシステムのワークショップ2011
    • Place of Presentation
      小倉
    • Year and Date
      2011-05-18
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] The Impact of RTN on Performance Fluctuation in CMOS Logic Circuits2011

    • Author(s)
      伊東, 松本, 西澤, 砂川, 小林, 小野寺
    • Organizer
      IEEE International Reliability Physics Symposium
    • Place of Presentation
      Monterey, CA, USA
    • Year and Date
      2011-04-13
    • Data Source
      KAKENHI-PROJECT-21300014
  • [Presentation] Multi-core LSI Lifetime Extension by NBTI-Recovery-bases Self-healing2011

    • Author(s)
      Takashi Matsumoto, Hiroaki Makino, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Organizer
      International Conference on Solid state Devices and Materials
    • Place of Presentation
      名古屋
    • Year and Date
      2011-09-29
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] トランジスタレベルでの経年劣化補償技術におけるNBTI回復特性の利用について2011

    • Author(s)
      松本高士, 牧野紘明, 小林和淑, 小野寺秀俊
    • Organizer
      システムLSIワークショップ
    • Place of Presentation
      北九州市
    • Year and Date
      2011-05-17
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] The Impact of RTN on Performance Flucuation in CMOS Logic Circuits2011

    • Author(s)
      Kyosuke Ito, Takahi Matsumoto, Shinichi Nishizawa, Hiroki Sunagawa, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Organizer
      2011 IEEE International Reliability Physics Symposium
    • Place of Presentation
      Monterey(アメリカ合衆国)
    • Year and Date
      2011-04-13
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] Modeling of Random Telegraph Noise under Circuit Operation-Simulation and Measurement of RTN-induced delay fluctuation-2011

    • Author(s)
      Kyosuke Ito, Takashi Matsumoto, Shinichi Nishizawa, Hiroki Sunagawa, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Organizer
      2011 International Symposium on Quality Electronic Design (ISQED)
    • Place of Presentation
      Santa Clara(アメリカ合衆国)
    • Year and Date
      2011-03-15
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] Modeling of Random Telegraph Noise under Circuit Operation-Simulation and Measurement of RTN-induced delay fluctuation2011

    • Author(s)
      伊東, 松本, 西澤, 砂川, 小林, 小野寺
    • Organizer
      International Symposium on Quality Electronic Design
    • Place of Presentation
      Santa Clala, CA, USA
    • Year and Date
      2011-03-15
    • Data Source
      KAKENHI-PROJECT-21300014
  • [Presentation] パッケージとの接続抵抗を考慮したチップ内電源ネットワークの構成手法2011

    • Author(s)
      西澤真一, 小林和淑, 小野寺秀俊
    • Organizer
      DAシンポジウム
    • Place of Presentation
      下呂市
    • Year and Date
      2011-08-31
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] Variability Characterization Using an RO-array Test Structure2010

    • Author(s)
      Shinichi Nishizawa, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Organizer
      4th IEEE International Workshop on Design for Manufacturability & Yield
    • Place of Presentation
      Anaheim(アメリカ合衆国)
    • Year and Date
      2010-06-14
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] 組み合わせ回路におけるランダム・テレグラフ・ノイズの影響の評価2010

    • Author(s)
      伊東恭佑、松本高士、小林和淑、小野寺秀俊
    • Organizer
      DAシンポジウム2010
    • Place of Presentation
      豊橋
    • Year and Date
      2010-09-03
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] A 65nm CMOS 400ns Measurement Delay NBTI-Recovery Sensor by Minimum Assist Circuit2010

    • Author(s)
      松本, 牧野, 小林, 小野寺
    • Organizer
      International Conference on Solid State Devices and Materials
    • Place of Presentation
      東京
    • Year and Date
      2010-09-23
    • Data Source
      KAKENHI-PROJECT-21300014
  • [Presentation] A 65nm CMOS 400ns Measurement Delay NBTI-Recovery Sensor by Minimum Assist Circuit2010

    • Author(s)
      Takashi Matsumoto, Hiroaki Makino, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Organizer
      International Conference on Solid State Devices and Materials (SSDM 2010)
    • Place of Presentation
      東京
    • Year and Date
      2010-09-23
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] バッファチェインにおけるパルス幅縮小現象を利用したSETパルス幅測定回路2010

    • Author(s)
      古田潤、小林和淑、小野寺秀俊
    • Organizer
      DAシンポジウム2010
    • Place of Presentation
      豊橋
    • Year and Date
      2010-09-03
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] Process-sensitive Monitor Circuits for Estimation of Die-to-Die Process Variability2010

    • Author(s)
      A.K.M. Mahfuzul Islam, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Organizer
      TAU Workshop 2010
    • Place of Presentation
      San Francisco
    • Year and Date
      2010-03-18
    • Data Source
      KAKENHI-PROJECT-19300010
  • [Presentation] Evaluation of FPGA design guardband caused by inhomogeneous NBTI degradation considering process variations2010

    • Author(s)
      籔内, 小林
    • Organizer
      International Conference on Field Programmable Technologies
    • Place of Presentation
      Beijing, China
    • Year and Date
      2010-12-09
    • Data Source
      KAKENHI-PROJECT-21300014
  • [Presentation] A 65nm Bistable Cross-coupled Dual Modular Redundancy Flip-Flop Capable of Protecting Soft Errors on the C-element2010

    • Author(s)
      古田, 濱中, 小林, 小野寺
    • Organizer
      VLSI Circuits Symposium
    • Place of Presentation
      Honolulu, Hawaii, USA
    • Year and Date
      2010-06-17
    • Data Source
      KAKENHI-PROJECT-21300014
  • [Presentation] Modeling of Random Telegraph Noise under Circuit Operation-Simulation and Measurement of RTN-induced Delay Fluctuation2010

    • Author(s)
      Kyosuke Ito, Takashi Matsumoto, Shinichi Nishizawa, Hiroki Sunagawa, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Organizer
      Workshop on variability modeling and characterization (VMC)
    • Place of Presentation
      San Jose, CA(アメリカ合衆国)
    • Year and Date
      2010-11-11
    • Data Source
      KAKENHI-PROJECT-22300016
  • [Presentation] Embedded Delay Detectors to Choose the Fastest Route in FPGAs for Variation-aware Reconfiguration2009

    • Author(s)
      Y. Kume, Y. Sugihara, C. Ngo, K. Kobayashi, H. Onodera
    • Organizer
      The 15th workshop on Synthesis And System Integration of Mixed Information technologies
    • Place of Presentation
      Okinawa, Japan
    • Year and Date
      2009-03-09
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] リーク電流によるNBTI特性の実測による評価2009

    • Author(s)
      牧野紘明、小林和淑、小野寺秀俊
    • Organizer
      2009年電子情報通信学会総合大会 エレクトロニクス講演論文集2,no.C-12-18, pp.106
    • Place of Presentation
      愛媛大学
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] Soft-error Resiliency Evaluation on Delayed Multiple-modular Flip-Flops2009

    • Author(s)
      Jun Furuta, Yusuke Moritani, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Organizer
      The 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009)
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] Embedded Delay Detectors to Choose the Fastest Route in FPGAs for Variation-aware Reconfiguration2009

    • Author(s)
      Yohei Kume, Yuuri Sugihara, Camlai Ngo, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Organizer
      The 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009)
    • Place of Presentation
      Okinawa, Japan
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] A Scalable Pipeline Design for Modularizing High Dependable Framework via Spatial Redundancy2008

    • Author(s)
      Jun Yao, Hajime Shimada, Kazutoshi Kobayashi
    • Organizer
      DA Symposium 2008
    • Place of Presentation
      Hamamatsu, Japan
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] Performance Optimization by Track.Swapping on Critical Paths Utilizing Random Variations for FPGAs2008

    • Author(s)
      Y. Sugihara, Y. Kume, K. Kobayashi. H. Onodera
    • Organizer
      International Conference on Field Programmable Logic and_Applications
    • Place of Presentation
      Heidelberg, Germany
    • Year and Date
      2008-09-09
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] レイアウト規則性が回路性能とばらつきに及ぼす影響の評価2008

    • Author(s)
      砂川洋輝, 寺田晴彦, 土谷亮, 小林和淑, 小野寺秀俊
    • Organizer
      DAシンポジウム2008
    • Place of Presentation
      浜松
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] Performance Optimization by Track Swapping on Critical Paths Utilizing Random Variations for FPAs2008

    • Author(s)
      Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Organizer
      2008 International Conference on Field Programmable Logic and Applications
    • Place of Presentation
      Heidelberg, Germany
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] SETパルスによる誤動作を防止する遅延挿入フリップフロップのソフトエラー耐性の検討2008

    • Author(s)
      小林和淑, 森谷祐介, 小野寺秀俊
    • Organizer
      DAシンポジウム2008
    • Place of Presentation
      浜松
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] Best Ways to Use Billions of Devices on a Chip-Error Predictive, Defect Tolerant and Error Recovery Designs2008

    • Author(s)
      K. Kobayashi, K. Katsuki, M. Kotani, Y. Sugihara, Y. Kume, H.
    • Organizer
      ASP-DAC
    • Place of Presentation
      ソウル
    • Year and Date
      2008-01-25
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] A Variation-aware Constant-Order Optimization Scheme Utilizing Delay Detectors to Search for Fastest Paths on FPGAs2008

    • Author(s)
      Kazutoshi Kobayashi, Yohei Kume, Cam Lai Ngo, Yuuri Sugihara, Hidetoshi Onodera
    • Organizer
      2008 Internation Conference on Field Programmable Logic and Applications
    • Place of Presentation
      Heidelberg, Germany
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] A Ring-Oscillator Array Circuit for Measurement and Modeling of Gate Delay Variability2008

    • Author(s)
      Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi. Hidetoshi Onodera
    • Organizer
      Workshop on Test Structure Design for Variability Characterization
    • Place of Presentation
      San Jose
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] 遅延比較器を用いた低コストなFPGAの速度・歩留まり向上手法2008

    • Author(s)
      久米洋平, 杉原有理, Ngo Cam Lai, 小林和淑, 小野寺秀俊
    • Organizer
      電子情報通信学会技術報告, vol.VLD2007-163, ICD-2007-186
    • Place of Presentation
      沖縄
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] リングオシレータアレイによるゲート遅延ばらつきの評価とモデル化2008

    • Author(s)
      寺田晴彦, 土谷亮, 小林和淑, 小野寺秀俊
    • Organizer
      DAシンポジウム2008
    • Place of Presentation
      浜松
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] Speed and Yield Enhancement by Track Swaing on Critical Paths Utilizing Random Variations for FPGAs2008

    • Author(s)
      Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Organizer
      FPGA
    • Place of Presentation
      Monterey, California, USA
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] Best Ways to Use Billions of Devices on a Chip - Error Predictive, Defect Tolerant and Error Recovery Designs2008

    • Author(s)
      Kazutoshi Kobayashi, Hidetoshi Onodera
    • Organizer
      The 13th Asia and South Pacific Design Automation Conference
    • Place of Presentation
      Seoul
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] A Variation-aware Constant-Order Optimization Scheme Utilizing Delay Detectors to Search for Fastest Paths on FPGAs2008

    • Author(s)
      K. Kobayashi, Y. Kume, C. L. Ngo, Y. Sugihara, H. Onodera
    • Organizer
      International Conference on Field Programmable Logic and Applications
    • Place of Presentation
      Heidelberg, Germany
    • Year and Date
      2008-09-09
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] 卓上テスト環境によるばらつき測定の高速化2007

    • Author(s)
      久米洋平, 小林和淑, 小野寺秀俊
    • Organizer
      電子情報通信学会総合大会予稿集
    • Place of Presentation
      名城大学
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] A 90nm 8x16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations2007

    • Author(s)
      Yuuri Sugihara, Manabu Kotani, Kazuya Katsuki, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Organizer
      12th Asia and South Pacific Design Automation Conference
    • Place of Presentation
      Yokohama
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] チップ内ばらつきを利用して歩留まりと速度を向上させるFPGA2007

    • Author(s)
      久米洋平、杉原有理、香月和也、小林和淑、小野寺秀俊
    • Organizer
      第11回システムLSIワークショップ予稿集
    • Place of Presentation
      北九州国際会議場
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] ランダムばらつきを利用したトラック入れ替えによるFPGAの速度と歩留まり向上2007

    • Author(s)
      杉原有理、久米洋平、小林和淑、小野寺秀俊
    • Organizer
      電子情報通信学会技術報告(RECONF2007-34),vol.107, no.340
    • Place of Presentation
      北九州国際会議場
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] Estimation of Yield Enhancement by Critical Path Reconfiguration Utilizing Random Variations on Deep-submicron FPGAs,2007

    • Author(s)
      Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Organizer
      SASIMI 2007
    • Place of Presentation
      Sapporo, Japan
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] 配線自由度によるばらつきを利用したFPGAの速度向上2007

    • Author(s)
      杉原有理、小林和淑、小野寺秀俊
    • Organizer
      DAシンポジウム2007
    • Place of Presentation
      浜松
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] ダイアモンドシールドを用いたガラスマイクロ・ナノインプリントの加工法の研究2006

    • Author(s)
      小森雅晴, 内山裕陽, 武部博倫, 楠浦崇央, 前川忠彦, 小林和淑
    • Organizer
      第6回生産加工・工作機械部門講演会講演論文集
    • Place of Presentation
      神奈川
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] Extracting a Random Component of Variation from Measurement Results of a 90 nm LUT Array2006

    • Author(s)
      Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Organizer
      SASIMI2006
    • Place of Presentation
      Nagoya
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] FPGAのチップ内ばらつきを利用した再配置による高速化の検討2006

    • Author(s)
      尾形幸亮, 小谷学, 香月和也, 小林和淑, 小野寺秀俊
    • Organizer
      信学技報リコンフィギャラブルシステム,vol.106, no.50(RECONF2006-14)
    • Place of Presentation
      仙台
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] A 90nm 8x16 LUT-based FPGA Enhancing Speed and Yield Utilizing Within-Die Variations2006

    • Author(s)
      M. Kotani, K. Katsuki, K. Kobayashi, H. Onodera
    • Organizer
      European Solid State Circuit Conference
    • Place of Presentation
      Montreux, Switzerland
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] Deterministic/Probablistic Noise and Bit Error Rate Modeling on On-chip Global Interconnect2006

    • Author(s)
      Yoichi Yuyama, Kazutoshi Kobayashi, Hidetoshi Onodera
    • Organizer
      SASIMI2006
    • Place of Presentation
      Nagoya
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] VDEC利用者から見たスターシャトル2006

    • Author(s)
      小林和淑
    • Organizer
      STARCフォーラム2006
    • Place of Presentation
      横浜
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] 微細プロセスを用いたFPGA設計手法2006

    • Author(s)
      小林和淑
    • Organizer
      信学技報リコンフィギャラブルシステム,vol.106, no.246(RECONF 2006-26)
    • Place of Presentation
      熊本
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] チップ内ばらつきを考慮したFPGA内配線モデルの検討2006

    • Author(s)
      杉原有理, 高務祐哲, 小林和淑, 小野寺秀俊
    • Organizer
      第19回 回路とシステム軽井沢ワークショップ
    • Place of Presentation
      軽井沢プリンスホテル
    • Data Source
      KAKENHI-PROJECT-18680005
  • [Presentation] A Yield and Speed Enhancement Technique Using Reconfigurable Devices against Within-Die Variations on the Nanometer Regime2006

    • Author(s)
      K. Kobayashi, M. Kotani, K. Katsuki, Y. Takatsukasa, K. Ogata, Y. Sugihara, H. Onodera
    • Organizer
      2006 International Conference on Field Programmable Logic and Applications
    • Place of Presentation
      Madrid, spain
    • Data Source
      KAKENHI-PROJECT-18680005
  • 1.  ONODERA Hidetoshi (80160927)
    # of Collaborated Projects: 15 results
    # of Collaborated Products: 23 results
  • 2.  TAMARU Keikichi (10127102)
    # of Collaborated Projects: 9 results
    # of Collaborated Products: 0 results
  • 3.  MOSHNYAGA Vasily (40243050)
    # of Collaborated Projects: 7 results
    # of Collaborated Products: 0 results
  • 4.  HASHIMOTO Masanori (80335207)
    # of Collaborated Projects: 3 results
    # of Collaborated Products: 0 results
  • 5.  YASUURA H (80135540)
    # of Collaborated Projects: 2 results
    # of Collaborated Products: 0 results
  • 6.  TSUCHIYA Akira (20432411)
    # of Collaborated Projects: 2 results
    # of Collaborated Products: 5 results
  • 7.  Matsumoto Takashi (70417369)
    # of Collaborated Projects: 2 results
    # of Collaborated Products: 6 results
  • 8.  西澤 真一 (40757522)
    # of Collaborated Projects: 2 results
    # of Collaborated Products: 3 results
  • 9.  KANBARA Hiroyuki
    # of Collaborated Projects: 2 results
    # of Collaborated Products: 0 results
  • 10.  UESAKA T (30213333)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 11.  TSURUTA Naoyuki (60227478)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 12.  SHUDO Kosho (70078632)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 13.  Kumashiro Shigetaka (60791473)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 5 results
  • 14.  古田 潤 (30735767)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 13 results
  • 15.  吉河 武文 (60636702)
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 16.  YOSHIDA Toyohiko
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 17.  MATSUZAWA Akira
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 18.  寺井 正幸
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 19.  TERAI M
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 20.  Stoffels Steve
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 21.  Posthuma Niels
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 22.  Li Xiangdong
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results
  • 23.  Decoutere Stefaan
    # of Collaborated Projects: 1 results
    # of Collaborated Products: 0 results

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